Texas Instruments | SN74LVCH16T245 16-bit Dual-supply Bus Transceiver With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs (Rev. B) | Datasheet | Texas Instruments SN74LVCH16T245 16-bit Dual-supply Bus Transceiver With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs (Rev. B) Datasheet

Texas Instruments SN74LVCH16T245 16-bit Dual-supply Bus Transceiver With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs (Rev. B) Datasheet
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SN74LVCH16T245
SCES635B – JULY 2005 – REVISED APRIL 2015
SN74LVCH16T245 16-bit Dual-supply Bus Transceiver
With Configurable Level-Shifting/Voltage Translation and Tri-State Outputs
1 Features
3 Description
•
This 16-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The A port
is designed to track VCCA. VCCA accepts any supply
voltage from 1.65 V to 5.5 V. The B port is designed
to track VCCB. VCCB accepts any supply voltage from
1.65 V to 5.5 V. This allows for universal low-voltage
bidirectional translation between any of the 1.8-V,
2.5-V, 3.3-V, and 5-V voltage nodes.
1
•
•
•
•
•
•
•
Control Inputs VIH/VIL Levels are Referenced to
VCCA Voltage
VCC Isolation Feature – If Either VCC Input is at
GND, All Outputs are in the High-Impedance State
Overvoltage-Tolerant Inputs and Outputs Allow
Mixed-Voltage-Mode Data Communications
Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.65 V to 5.5 V
Power-Supply Range
Bus Hold on Data Inputs Eliminates the Need for
External Pullup and Pulldown Resistors
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
2 Applications
•
•
•
•
Personal Electronics
Industrial
Enterprise
Telecom
The SN74LVCH16T245 device control pins (1DIR,
2DIR, 1OE, and 2OE) are supplied by VCCA.
The SN74LVCH16T245 device is designed for
asynchronous communication between two data
buses. The logic levels of the direction-control (DIR)
input and the output-enable (OE) input activate either
the B-port outputs or the A-port outputs or place both
output ports into the high-impedance mode. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated, and from the B
bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is
always active and must have a logic HIGH or LOW
level applied to prevent excess ICC and ICCZ.
Device Information(1)
PART NUMBER
SN74LVCH16T245
PACKAGE
BODY SIZE (NOM)
SSOP (48)
15.88 mm × 7.49 mm
TSSOP (48)
12.50 mm × 6.10 mm
TVSOP (48)
9.70 mm × 4.40 mm
BGA (56)
7.00 mm × 4.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
To Seven Other Channels
24
2OE
36
13
1B1
2B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCH16T245
SCES635B – JULY 2005 – REVISED APRIL 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
8
1
1
1
2
3
4
6
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions ...................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Switching Characteristics for VCCA = 1.8 V ±0.15 V . 9
Switching Characteristics for VCCA = 2.5 V ±0.2 V . 10
Switching Characteristics for VCCA = 3.3 V ±0.3 V . 10
Switching Characteristics for VCCA = 5 V ±0.5 V .... 11
Operating Characteristics...................................... 11
Typical Characteristics .......................................... 12
Parameter Measurement Information ................ 13
9
Detailed Description ............................................ 14
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
14
14
14
15
10 Application and Implementation........................ 16
10.1 Application Information.......................................... 16
10.2 Typical Application ............................................... 17
11 Power Supply Recommendations ..................... 19
12 Layout................................................................... 19
12.1 Layout Guidelines ................................................. 19
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
Changes from Revision A (August 2005) to Revision B
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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5 Description (continued)
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended. The bus-hold circuitry on the powered-up side always
stays active.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, then all outputs are in the high-impedance
state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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6 Pin Configuration and Functions
DGG and DGV Packages
48-Pin TSSOP and TVSOP
(Top View)
1DIR
1B1
1B2
GND
1B3
1B4
VCCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCCB
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
GQL and ZQL Packages
56-Pin BGA
(Top View)
1
1OE
1A1
1A2
GND
1A3
1A4
VCCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCCA
2A5
2A6
GND
2A7
2A8
2OE
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DGG / DGV
GQL / ZQL
1A1
47
B5
I/O
Input/Output. Referenced to VCCA
1A2
46
B6
I/O
Input/Output. Referenced to VCCA
1A3
44
C5
I/O
Input/Output. Referenced to VCCA
1A4
43
C6
I/O
Input/Output. Referenced to VCCA
1A5
41
D5
I/O
Input/Output. Referenced to VCCA
1A6
40
D6
I/O
Input/Output. Referenced to VCCA
1A7
38
E5
I/O
Input/Output. Referenced to VCCA
1A8
37
E6
I/O
Input/Output. Referenced to VCCA
1B1
2
B2
I/O
Input/Output. Referenced to VCCB
1B2
3
B1
I/O
Input/Output. Referenced to VCCB
1B3
5
C2
I/O
Input/Output. Referenced to VCCB
1B4
6
C1
I/O
Input/Output. Referenced to VCCB
1B5
8
D2
I/O
Input/Output. Referenced to VCCB
1B6
9
D1
I/O
Input/Output. Referenced to VCCB
1B7
11
E2
I/O
Input/Output. Referenced to VCCB
1B8
12
E1
I/O
Input/Output. Referenced to VCCB
1DIR
1
A1
I
4
Direction-control signal
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Pin Functions (continued)
PIN
NAME
I/O
DESCRIPTION
DGG / DGV
GQL / ZQL
1OE
48
A6
I
2A1
36
F6
I/O
Input/Output. Referenced to VCCA
2A2
35
F5
I/O
Input/Output. Referenced to VCCA
2A3
33
G6
I/O
Input/Output. Referenced to VCCA
2A4
32
G5
I/O
Input/Output. Referenced to VCCA
2A5
30
H6
I/O
Input/Output. Referenced to VCCA
2A6
29
H5
I/O
Input/Output. Referenced to VCCA
2A7
27
J6
I/O
Input/Output. Referenced to VCCA
2A8
26
J5
I/O
Input/Output. Referenced to VCCA
2B1
13
F1
I/O
Input/Output. Referenced to VCCB
2B2
14
F2
I/O
Input/Output. Referenced to VCCB
2B3
16
G1
I/O
Input/Output. Referenced to VCCB
2B4
17
G2
I/O
Input/Output. Referenced to VCCB
2B5
19
H1
I/O
Input/Output. Referenced to VCCB
2B6
20
H2
I/O
Input/Output. Referenced to VCCB
2B7
22
J1
I/O
Input/Output. Referenced to VCCB
2B8
23
J2
I/O
Input/Output. Referenced to VCCB
2DIR
24
K1
I
Direction-control signal
2OE
25
K6
I
Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State
mode. Referenced to VCCA
4
10
GND
B3
B4
D3
15
D4
21
G3
28
G4
34
J3
45
Tri-State output-mode enables. Pull OE high to place all outputs in Tri-State
mode. Referenced to VCCA
—
Ground
J4
A2
A3
A4
NC (1)
—
A5
K2
—
K3
K4
K5
VCCA
VCCB
(1)
31
C4
42
H4
7
C3
18
H3
—
A-port supply. 1.65 V ≤ VCCA≤ 5.5 V
—
B-port supply. 1.65 V ≤ VCCB≤ 5.5 V
NC – No internal connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCCA
VCCB
Supply voltage
VI
Input voltage (2)
VO
Voltage applied to any output
in the high-impedance or power-off state (2)
(3)
MIN
MAX
UNIT
–0.5
6.5
V
I/O ports (A port)
–0.5
6.5
I/O ports (B port)
–0.5
6.5
Control inputs
–0.5
6.5
A port
–0.5
6.5
B port
–0.5
6.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
V
V
VO
Voltage applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through each VCCA, VCCB, and GND
±100
mA
V
TJ
Junction temperature
-40
150
°C
Tstg
Storage temperature
–65
150
°C
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input (VI ) and output (VO) negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 6.5 V maximum if the output current rating is observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
6
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
Machine Model (MM), Per JEDEC specification JESD22-A115-A
±200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
See
(1) (2) (3)
.
VCCI
VCCA
VCCB
VCCO
Supply voltage
1.65 V to 1.95 V
High-level
input voltage
VIH
MAX
1.65
5.5
1.65
5.5
1.7
3 V to 3.6 V
4.5 V to 5.5 V
Low-level
input voltage
Data inputs (4)
VCCI × 0.7
VCCI × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
4.5 V to 5.5 V
VIH
Control inputs
(referenced to VCCA) (5)
VCCA × 0.65
2.3 V to 2.7 V
1.7
3 V to 3.6 V
V
2
4.5 V to 5.5 V
VCCA × 0.7
1.65 V to 1.95 V
VCCA × 0.35
2.3 V to 2.7 V
0.7
3 V to 3.6 V
0.8
VIL
Low-level
input voltage
Control inputs
(referenced to VCCA) (5)
VI
Input voltage
Control inputs
0
5.5
Input/output
voltage
Active state
0
VCCO
Tri-State
0
5.5
4.5 V to 5.5 V
VI/O
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition
rise or fall rate
TA
Operating free-air temperature
Data inputs
(4)
(5)
V
V
–4
2.3 V to 2.7 V
–8
3 V to 3.6 V
–24
4.5 V to 5.5 V
–32
1.65 V to 1.95 V
4
2.3 V to 2.7 V
8
3 V to 3.6 V
24
4.5 V to 5.5 V
32
1.65 V to 1.95 V
20
2.3 V to 2.7 V
20
3 V to 3.6 V
10
4.5 V to 5.5 V
(1)
(2)
(3)
V
VCCA × 0.3
1.65 V to 1.95 V
IOH
V
VCCI × 0.3
1.65 V to 1.95 V
High-level
input voltage
V
V
2
1.65 V to 1.95 V
VIL
UNIT
VCCI × 0.65
2.3 V to 2.7 V
Data inputs (4)
MIN
mA
mA
ns/V
5
–40
85
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the output port.
All unused control inputs of the device must be held at VCCA GND to ensure proper device operation and minimize power consumption.
Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCA values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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7.4 Thermal Information
SN74LVCH16T245
THERMAL METRIC
RθJA
(1)
DGG (TSSOP)
DGV
(TVSOP)
GQL / ZQL
(BGA)
48 PINS
48 PINS
48 PINS
56 PINS
UNIT
92.9
60
82.5
64.6
°C/W
RθJC(top) Junction-to-case (top) thermal resistance
29.5
13.9
34.2
16.6
°C/W
RθJB
Junction-to-board thermal resistance
35.5
27.1
45.1
30.8
°C/W
ψJT
Junction-to-top characterization parameter
8.1
0.5
2.7
0.9
°C/W
ψJB
Junction-to-board characterization parameter
34.9
26.8
44.6
64.6
°C/W
(1)
Junction-to-ambient thermal resistance
DL (SSOP)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (1) (2)
PARAMETER
TEST CONDITIONS
VCCB
MIN
1.65 V to 4.5 V
1.65 V to 4.5 V
VCCO
– 0.1
VI = VIH
1.65 V
1.65 V
1.2
VI = VIH
2.3 V
2.3 V
1.9
IOH = –24 mA,
VI = VIH
3V
3V
2.4
IOH = –32 mA,
VI = VIH
4.5 V
4.5 V
3.8
IOL = 100 μA,
VI = VIL
1.65 V to 4.5 V
1.65 V to 4.5 V
0.1
IOL = 4 mA,
VI = VIL
1.65 V
1.65 V
0.45
IOL = 8 mA,
VI = VIL
2.3 V
2.3 V
0.3
IOL = 24 mA,
VI = VIL
3V
3V
0.55
IOL = 32 mA,
VI = VIL
4.5 V
4.5 V
0.55
1.65 V to 5.5 V
1.65 V to 5.5 V
VI = 0.58 V
1.65 V
1.65 V
15
VI = 0.7 V
2.3 V
2.3 V
45
VI = 0.8 V
3V
3V
75
VI = VIH
IOH = –4 mA,
IOH = –8 mA,
IOH = –100 μA,
VOH
VOL
Control
inputs
II
IBHL (3)
IBHH (4)
VI = VCCA or GND
4.5 V
4.5 V
100
VI = 1.07 V
1.65 V
1.65 V
–15
VI = 1.7 V
2.3 V
2.3 V
–45
3V
3V
–75
VI = 3.15 V
VI = 0 to VCC
IBHHO (6)
(1)
(2)
(3)
(4)
(5)
(6)
8
VI = 0 to VCC
TYP
4.5 V
4.5 V
–100
1.95 V
1.95 V
200
2.7 V
2.7 V
300
3.6 V
3.6 V
500
5.5 V
5.5 V
900
1.95 V
1.95 V
–200
2.7 V
2.7 V
–300
3.6 V
3.6 V
–500
5.5 V
5.5 V
–900
MAX
UNIT
V
±0.5
VI = 0.1.35 V
VI = 2 V
IBHLO (5)
VCCA
±2
V
μA
μA
μA
μA
μA
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. IBHL should be measured after lowering VIN to GND
and then raising it to VIL max.
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. IBHH should be measured after raising VIN to
VCC and then lowering it to VIH min.
An external driver must source at least IBHLO to switch this node from low to high.
An external driver must sink at least IBHHO to switch this node from high to low.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)(1)(2)
PARAMETER
A port
Ioff
B port
A or B
port
IOZ
B port
TEST CONDITIONS
OE = VIH
ICCA
VI = VCCI or GND,
ICCB
ICCA +
ICCB
IO = 0
MAX
±0.5
±2
0V
±0.5
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
±2
0V
5.5 V
±2
UNIT
μA
μA
5.5 V
0V
±2
1.65 V to 5.5 V
1.65 V to 5.5 V
20
5V
0V
20
0V
5V
–2
1.65 V to 5.5 V
1.65 V to 5.5 V
20
5V
0V
–2
0V
5V
20
1.65 V to 5.5 V
1.65 V to 5.5 V
30
3 V to 5.5 V
3 V to 5.5 V
50
μA
IO = 0
VI = VCCI or GND,
TYP
0 to 5.5 V
IO = 0
VI = VCCI or GND,
MIN
0V
OE = don't
care
A port
VCCB
0 to 5.5 V
VI or VO = 0 to 5.5 V
VO = VCCO or GND,
VI = VCCI or GND
VCCA
μA
μA
μA
ΔICCA
DIR
DIR at VCCA – 0.6 V,
B port = open,
A port at VCCA or GND
Ci
Control
inputs
VI = VCCA or GND
3.3 V
3.3 V
4
5
pF
Cio
A or B
port
VO = VCCA/B or GND
3.3 V
3.3 V
8.5
10
pF
7.6 Switching Characteristics for VCCA = 1.8 V ±0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.7
21.9
1.3
9.2
1
7.4
0.4
7.1
ns
B
A
0.9
23.8
0.8
23.8
0.7
23.4
0.7
23.4
ns
OE
A
1.5
29.6
1.5
29.4
1.5
29.3
1.4
29.2
ns
OE
B
2.4
32.2
1.9
13.1
1.7
12
1.3
10.3
ns
OE
A
0.4
24
0.4
23.8
0.4
23.7
0.4
23.7
ns
OE
B
1.8
32
1.5
18
1.2
12.6
0.9
10.8
ns
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7.7 Switching Characteristics for VCCA = 2.5 V ±0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
MIN
MAX
B
1.5
21.4
1.2
B
A
1.2
9.3
OE
A
1.4
OE
B
OE
OE
VCCB = 3.3 V
±0.3 V
MIN MAX
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
9
0.8
6.2
0.6
4.8
ns
1
9.1
1
8.9
0.9
8.8
ns
9
1.4
9
1.4
9
1.4
9
ns
2.3
29.6
1.8
11
1.7
9.3
0.9
6.9
ns
A
1
10.9
1
10.9
1
10.9
1
10.9
ns
B
1.7
28.2
1.5
12.9
1.2
9.4
1
6.9
ns
7.8 Switching Characteristics for VCCA = 3.3 V ±0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
10
FROM
(INPUT)
TO
(OUTPUT)
A
VCCB = 1.8 V
±0.15 V
VCCB = 2.5 V
±0.2 V
VCCB = 3.3 V
±0.3 V
VCCB = 5 V
±0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.6
21.2
1.1
8.8
0.8
6.2
0.6
4.4
ns
B
A
0.8
7.2
0.8
6.2
0.7
6.1
0.6
6
ns
OE
A
1.6
8.2
1.6
8.2
1.6
8.2
1.6
8.2
ns
OE
B
2.1
29
1.7
10.3
1.5
8.8
0.8
6.3
ns
OE
A
0.8
7.8
0.8
8.1
0.8
8.1
0.8
8.1
ns
OE
B
1.8
27.7
1.4
12.4
1.1
8.5
0.8
6.4
ns
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7.9 Switching Characteristics for VCCA = 5 V ±0.5 V
over recommended operating free-air temperature range, VCCA = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
tPZH
tPZL
tPZH
tPZL
FROM
(INPUT)
TO
(OUTPUT)
A
VCC = 1.8 V
±0.15 V
VCC = 2.5 V
±0.2 V
MIN MAX
VCC = 3.3 V
±0.3 V
MIN MAX
VCC = 5 V
±0.5 V
UNIT
MIN
MAX
MIN MAX
B
1.5
21.4
1
8.8
0.7
6
0.4
4.2
ns
B
A
0.7
7
0.4
4.8
0.3
4.5
0.3
4.3
ns
OE
A
0.3
5.4
0.3
5.4
0.3
5.4
0.3
5.4
ns
OE
B
2
28.7
1.8
9.7
1.4
8
0.7
5.7
ns
OE
A
0.7
6.4
0.7
6.4
0.7
6.4
0.7
6.4
ns
OE
B
1.5
27.6
1.3
11.4
1
8.1
0.9
6
ns
7.10 Operating Characteristics
TA = 25°C
PARAMETER
CpdA (1)
CpdB
(1)
(1)
TEST
CONDITIONS
A-port input, B-port output
B-port input, A-port output
A-port input, B-port output
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
B-port input, A-port output
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
VCCA =
VCCB = 5 V
UNIT
TYP
TYP
TYP
TYP
2
2
2
3
18
19
19
22
18
19
20
22
2
2
2
2
pF
Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation,
SCAA035
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1.4
5.6
1.2
5.4
1.0
5.2
VOH Voltage (V)
VOL Voltage (V)
7.11 Typical Characteristics
0.8
0.6
0.4
4.8
4.6
o
-40 C
o
25 C
0.2
5.0
o
-40 C
o
25 C
4.4
o
o
85 C
85 C
4.2
0
0
12
20
40
60
80
100
0
-20
-40
-60
-80
IOL Current (mA)
IOH Current (mA)
Figure 1. VOL Voltage vs IOL Current
Figure 2. VOH Voltage vs IOH Current
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8 Parameter Measurement Information
2 Ψ VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 Ψ VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 Ψ VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLH and tPHL are the same as tpd.
F. VCCI is the VCC associated with the input port.
G. VCCO is the VCC associated with the output port.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVCH16T245 is a 16-bit, dual-supply noninverting bidirectional voltage level translation. Pins AX and
control pins (DIR and OE) are supported by VCCA and pins BX are supported by VCCB. The A port is able to
accept I/O voltages ranging from 1.65 V to 5.5 V, while the B port can accept I/O voltages from 1.65 V to 5.5 V.
A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when
OE is set to low. When OE is set to high, both A and B are in the high-impedance state.
This device has Active bus-hold circuitry that holds unused or undriven inputs at a valid logic state. This device is
fully specified for partial-power-down applications using off output current (Ioff).
The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state.
9.2 Functional Block Diagram
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
9.3 Feature Description
9.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage from 1.65 V to 5.5 V making the device suitable for
translating between any of the low voltage nodes (1.8-V, 2.5-V, and 3.3-V).
9.3.2 Support High-Speed Translation
SN74LVCH16T245 can support high data rate application. Data rates can be calculated form the maximum
propagation delay. This is also dependant on the output load. For example, for a 3.3-V to 5-V conversion, the
maximum frequency is 200 MHz.
9.3.3 Partial-Power-Down Mode Operation
This device is fully specified for partial-power-down applications using off output current (Ioff). Ioff will prevent
backflow current by disabling I/O output circuits when device is in partial power-down mode.
9.3.4 VCC Isolation
The VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedance
state (IOZ shown in Electrical Characteristics). This prevents false logic levels from being presented to either bus.
9.3.5 Bus Hold on Data Inputs
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
14
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9.4 Device Functional Modes
The SN74LVCH16T245 is a voltage level translator that can operate from 1.65 V to 5.5 V (VCCA) and 1.65 V to
5.5 V (VCCB). The signal translation between 1.65 V and 5.5 V requires direction control and output enable
control. When OE is low and DIR is high, data transmission is from A to B. When OE is low and DIR is low, data
transmission is from B to A. When OE is high, both output ports will be high-impedance.
Table 1. Function Table (Each Transceiver) (1)
CONTROL INPUTS
OE
(1)
OUTPUT CIRCUITS
B PORT
OPERATION
DIR
A PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os are always active.
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LVCH16T245 device can be used in level-shifting applications for interfacing devices and addressing
mixed voltage incompatibility. The SN74LVCH16T245 device is ideal for data transmission where direction is
different for each channel.
10.1.1 Enable Times
Calculate the enable times for the SN74LVCH16T245 using the following formulas:
tPZH (DIR to A) = tPLZ
tPZL (DIR to A) = tPHZ
tPZH (DIR to B) = tPLZ
tPZL (DIR to B) = tPHZ
(DIR
(DIR
(DIR
(DIR
to
to
to
to
B) +
B) +
A) +
A) +
tPLH (B to
tPHL (B to
tPLH (A to
tPHL (A to
A)
A)
B)
B)
(1)
(2)
(3)
(4)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74LVCH16T245 initially is transmitting from A to B,
then the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the
B port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
16
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10.2 Typical Application
1.8 V
3.3 V
0.1 µF
0.1 µF
VCCA
1 µF
VCCB
1DIR/2DIR
1OE/2OE
1.8-V
Controller
SN74LVCH16T245
Data
1A1/2A1
1B1/2B1
1A2/2A2
1B2/2B2
1A3/2A3
1B3/2B3
1A4/2A4
1B4/2B4
1A5/2A5
1B5/2B5
1A6/2A6
1B6/2B6
1A7/2A7
1B7/2B7
1A8/2A8
1B8/2B8
GND
3.3-V
System
Data
GND
GND
Figure 4. Application Schematic
10.2.1 Design Requirements
This device uses drivers which are enabled depending on the state of the DIR pin. The designer must know the
intended flow of data and take care not to violate any of the high or low logic levels. It is important that unused
data inputs not be floating, as this can cause excessive internal leakage on the input CMOS structure. Make sure
to tie any unused input and output ports directly to ground. For this design example, use the parameters listed in
Table 2.
Table 2. Design Parameters
DESIGN PARAMETERS
EXAMPLE VALUE
Input voltage range
1.65 V to 5.5 V
Output voltage
1.65 V to 5.5 V
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10.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74LVCH16T245 device to determine the input
voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74LVCH16T245 device is driving to determine the output
voltage range.
10.2.3 Application Curve
Voltage (V)
Output (5 V)
Input (1.8 V)
Time (200 ns/div)
Figure 5. Translation Up (1.8 V to 5 V) at 2.5 MHz
18
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11 Power Supply Recommendations
The SN74LVCH16T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.65 V to 5.5 V and VCCB accepts any supply voltage from 1.65 V to 5.5 V. The A port
and B port are designed to track VCCA and VCCB, respectively, allowing for low-voltage bidirectional translation
between any of the 1.8-V, 2.5-V and 3.3-V voltage nodes.
The output-enable OE input circuit is designed so that it is supplied by VCCA and when the OE input is high, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by
the current-sinking capability of the driver.
12 Layout
12.1 Layout Guidelines
To
•
•
•
ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals depending on the system requirements.
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12.2 Layout Example
LEGEND
Polygonal Copper Pour
VIA to Power Plane
VIA to GND Plane (Inner Layer)
Keep OE high until VCCA and
VCCB are powered up
VCCA
1DIR
1OE
48
To
System
2
1B1
1A1
47
From
Controller
To
System
3
1B2
1A2
46
From
Controller
4
GND
GND
45
To
System
5
1B3
1A3
44
From
Controller
To
System
6
1B4
1A4
43
From
Controller
VCCA
42
7
VCCB
8
1B5
1A5
41
From
Controller
To
System
9
1B6
1A6
40
From
Controller
10
GND
GND
39
11
1B7
1A7
38
From
Controller
12
1B8
1A8
37
From
Controller
To
System
13
2B1
2A1
36
From
Controller
To
System
14
2B2
2A2
35
15
GND
GND
34
To
System
16
2B3
2A3
33
From
Controller
To
System
17
2B4
2A4
32
From
Controller
18
VCCB
To
System
SN74AVCH16T245
VCCA
VCCA
Bypass Capacitor
To
System
To
System
VCCB
VCCA
VCCB
1
From
Controller
VCCA
31
Bypass Capacitor
From
Controller
From
Controller
19
2B5
2A5
To
System
20
2B6
2A6
29
21
GND
GND
28
To
System
22
2B7
2A7
27
From
Controller
To
System
23
2B8
2A8
26
From
Controller
24
2DIR
2OE
25
VCCA
To
System
VCCA
31
Keep OE high until VCCA and
VCCB are powered up
Figure 6. SN74LVCH16T245 Layout Example
20
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13 Device and Documentation Support
13.1 Documentation Support
13.1.1 Related Documentation
For related documentation see the following:
• CMOS Power Consumption and Cpd Calculation, SCAA035
• Implications of Slow or Floating CMOS Inputs, SCBA004
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVCH16T245DGGRE4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCH16T245
74LVCH16T245DLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCH16T245
74LVCH16T245ZQLR
NRND
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
NL245
SN74LVCH16T245DGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCH16T245
SN74LVCH16T245DGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LDHT245
SN74LVCH16T245DL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCH16T245
SN74LVCH16T245DLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVCH16T245
SN74LVCH16T245KR
NRND
BGA
MICROSTAR
JUNIOR
GQL
56
1000
TBD
SNPB
Level-1-240C-UNLIM
-40 to 85
LDHT245
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVCH16T245 :
• Enhanced Product: SN74LVCH16T245-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74LVCH16T245ZQLR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
SN74LVCH16T245DGGR TSSOP
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
SN74LVCH16T245DGVR TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
GQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
SN74LVCH16T245DLR
SN74LVCH16T245KR
SSOP
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74LVCH16T245ZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
350.0
350.0
43.0
SN74LVCH16T245DGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74LVCH16T245DGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74LVCH16T245DLR
SSOP
DL
48
1000
367.0
367.0
55.0
SN74LVCH16T245KR
BGA MICROSTAR
JUNIOR
GQL
56
1000
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
GQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219710/A 03/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
4. This package is tin-lead (SnPb).
www.ti.com
EXAMPLE BOARD LAYOUT
GQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219710/A 03/2017
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
GQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219710/A 03/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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