Texas Instruments | SNx4HC594 8-Bit Shift Registers With Output Registers (Rev. G) | Datasheet | Texas Instruments SNx4HC594 8-Bit Shift Registers With Output Registers (Rev. G) Datasheet

Texas Instruments SNx4HC594 8-Bit Shift Registers With Output Registers (Rev. G) Datasheet
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SN54HC594, SN74HC594
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
SNx4HC594 8-Bit Shift Registers With Output Registers
1 Features
3 Description
•
•
The SNx4HC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (RCLR, SRCLR) inputs are provided
on both the shift and storage registers. A serial (QH’)
output is provided for cascading purposes.
1
•
•
•
•
•
•
•
Wide Operating Voltage Range of 2 V to 6 V
High-Current Outputs Can Drive up to
15 LSTTL Loads
Low Power Consumption, 80-µA Maximum ICC
Typical tpd = 15 ns
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Maximum
8-Bit Serial-In, Parallel-Out Shift Registers With
Storage
Independent Direct Overriding Clears on Shift and
Storage Registers
Independent Clocks for Both Shift and
Storage Registers
2 Applications
•
•
•
•
•
•
Pro Audio Mixer
Elevators and Escalators
Human Machine Interface (HMI): Industrial
Monitor
Entertainment Systems
Grid Infrastructure: Grid Control
Access Control and Security: DVR and DVS
Both the shift register (SRCLK) and storage
(RCLK) clocks are positive edge triggered.
clocks are connected together, the shift
always is one count pulse ahead of the
register.
register
If both
register
storage
The parallel (QA − QH) outputs have high-current
capability. QH’ is a standard output.
Device Information(1)
PART NUMBER
SN74HC594
PACKAGE
BODY SIZE (NOM)
PDIP (16)
19.30 mm × 6.35 mm
SOIC (16)
9.00 mm × 9.00 mm
10.30 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Logic Diagram (Positive Logic)
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
1D
C1
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
14
15
1
QB
2
QC
3
4
5
6
7
9
Pin numbers shown are for the D, DW, J, N, and W packages.
QA
QD
QE
QF
QG
QH
QH′
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54HC594, SN74HC594
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
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Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Switching Characteristics: CL = 50 pF....................... 6
Switching Characteristics: CL = 150 pF .................... 6
Timing Requirements ................................................ 7
Operating Characteristics.......................................... 7
Typical Characteristics ............................................ 9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 15
11 Layout................................................................... 15
11.1 Layout Guidelines ................................................. 15
11.2 Layout Example .................................................... 15
12 Device and Documentation Support ................. 16
12.1
12.2
12.3
12.4
Documentation Support ........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
16
13 Mechanical, Packaging, and Orderable
Information ........................................................... 16
4 Revision History
Changes from Revision F (October 2003) to Revision G
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Removed ordering information. .............................................................................................................................................. 1
•
ESD warning added................................................................................................................................................................ 1
2
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5 Pin Configuration and Functions
D, DW, or N Package
16-PIN PDIP or SOIC
Top View
QB
QC
QD
QE
QF
QG
QH
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
QA
SER
RCLR
RCLK
SRCLK
SRCLR
QH′
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
QB
O
Output B
2
QC
O
Output C
3
QD
O
Output D
4
QE
O
Output E
5
QF
O
Output F
6
QG
O
Output G
7
QH
O
Output H
8
GND
–
Ground
9
QH'
O
QH inverted
10
SRCLR
I
Serial clear
11
SRCLK
I
Serial clock
12
RCLK
I
Storage clock
13
RCLK
I
Storage clear
14
SER
I
Serial input
15
QA
O
Output A
16
Vcc
–
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage
(2)
MIN
MAX
UNIT
–0.5
7
V
IIK
Input clamp current
VI < 0 or VI > VCC
–20
20
mA
IOK
Output clamp current (2)
VO < 0 or VO > VCC
–20
20
mA
IO
Continuous output current
VO = 0 to VCC
–35
35
mA
–70
70
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature
D package
73
DW package
57
N package
(1)
(2)
(3)
°C/W
67
–60
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54HC594 (2)
VCC
VIH
NOM
MAX
2
5
6
Supply voltage
VCC = 2 V
High-level input voltage
VCC = 4.5 V
VCC = 6 V
Low-level input voltage
MIN
NOM
MAX
2
5
6
1.5
1.5
3.15
3.15
4.2
4.2
VCC = 2 V
VIL
SN74HC594
MIN
VCC = 4.5 V
VCC = 6 V
UNIT
V
V
0.5
0.5
1.35
1.35
1.8
1.8
V
VI
Input voltage
0
VCC
0
VCC
V
VO
Output voltage
0
VCC
0
VCC
V
VCC = 2 V
tt
TA
(1)
(2)
4
Input transition (rise and fall) rate
Operating free-air temperature
1000
1000
VCC = 4.5 V
500
500
VCC = 6 V
400
400
–55
125
–40
125
ns
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
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6.4 Thermal Information
SN74HC594
THERMAL METRIC (1)
N (PDIP)
D (SOIC)
DW (SOIC)
16 PINS
16 PINS
16 PINS
41.3
72.3
71
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
28
33.2
32.3
RθJB
Junction-to-board thermal resistance
21.3
29.9
35.9
ψJT
Junction-to-top characterization parameter
12.6
5.3
6.7
ψJB
Junction-to-board characterization parameter
21.1
29.6
35.3
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VOH
VI = VIH
or VIL
QH’
IOH = –4 mA
QA – QH
IOH = –6 mA
QH’
IOH = –5.2
mA
QA – QH
IOH = –7.8
mA
IOL = 20 µA
VOL
VI = VIH
or VIL
QH’
IOL = 4 mA
QA – QH
IOL = 6 mA
QH’
IOL = 5.2
mA
QA – QH
IOL = 7.8
mA
VCC
MAX
MIN
MAX
MIN
MAX
MIN
1.9
1.998
1.9
1.9
1.9
4.4
4.499
4.4
4.4
4.4
6V
5.9
5.999
5.9
5.9
5.9
3.98
4.3
3.7
3.84
3.84
3.98
4.3
3.7
3.84
3.84
5.48
5.8
5.2
5.34
5.34
5.48
5.8
5.2
5.34
5.34
4.5 V
UNIT
MAX
V
6V
2V
0.002
0.1
0.1
0.1
0.1
4.5 V
0.001
0.1
0.1
0.1
0.1
6V
0.001
0.1
0.1
0.1
0.1
0.17
0.26
0.4
0.33
0.33
0.17
0.26
0.4
0.33
0.33
0.15
0.26
0.4
0.33
0.33
0.15
0.26
0.4
0.33
0.33
±0.1
±100
±1000
±1000
±1000
nA
8
160
80
80
µA
10
10
10
4.5 V
V
6V
6V
ICC
VI = VCC
or 0,
6V
(1)
TYP
SN74HC594
–40°C to 125°C
2V
VI = VCC or 0
2 V to
6V
Ci
MIN
SN74HC594
–40°C to 85°C
4.5 V
II
IO = 0
SN54HC594 (1)
–55°C to 125°C
TA = 25°C
3
pF
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6.6 Switching Characteristics: CL = 50 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
SRCLK
QH’
tpd
RCLK
SRCLR
QA – QH
QH’
tPHL
RCLR
QA – QH
QH’
tt
QA – QH
(1)
SN54HC594 (1)
–55°C to 125°C
TA = 25°C
VCC
MIN
TYP
MAX
MIN
MAX
SN74HC594
–40°C to 85°C
MIN
MAX
SN74HC594
–40°C to 125°C
MIN
2V
5
8
3.3
4
4
4.5 V
25
35
17
20
20
6V
29
40
20
24
24
UNIT
MAX
MHz
2V
50
150
225
185
200
4.5 V
20
30
45
37
42
6V
15
25
38
31
36
2V
50
150
225
185
200
4.5 V
20
30
45
37
42
6V
15
25
38
31
36
2V
50
150
225
185
200
4.5 V
20
30
45
37
42
6V
15
25
38
31
36
2V
50
125
185
155
170
4.5 V
20
25
37
31
36
6V
15
21
31
26
31
2V
38
75
110
95
110
4.5 V
8
15
22
19
21
6V
6
13
19
16
18
2V
38
60
90
75
85
4.5 V
8
12
18
15
17
6V
6
10
15
13
15
ns
ns
ns
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6.7 Switching Characteristics: CL = 150 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
PARAMETER
tpd
tPHL
6
TO
(OUTPUT)
VCC
RCLK
QA – QH
RCLR
tt
(1)
FROM
(INPUT)
QA – QH
QA – QH
SN54HC594 (1)
–55°C to 125°C
TA = 25°C
MIN
MIN
MAX
SN74HC594
–40°C to 85°C
MIN
MAX
SN74HC594
–40°C to 125°C
TYP
MAX
MIN
2V
90
200
300
250
270
4.5 V
23
40
60
50
55
6V
19
34
51
43
48
UNIT
MAX
2V
90
200
300
250
270
4.5 V
23
40
60
50
55
6V
19
34
51
43
48
2V
45
210
315
265
285
4.5 V
17
42
63
53
58
6V
13
36
53
45
50
ns
ns
ns
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6.8 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
VCC
MIN
fclock
Clock frequency
SRCLK or RCLK high or low
tw
Pulse
duration
SRCLR or RCLR low
SER before SRCLK↑
SRCLK↑ before RCLK↑ (2)
tsu
Setup time
SRCLR low before RCLK↑
before CLK↑
SRCLR high (inactive) before
SRCLK↑
RCLR high (inactive) before
SRCLK↑
th
(1)
(2)
Hold time, SER after SRCLK↑
SN54HC594 (1)
–55°C to 125°C
TA = 25°C
MAX
MIN
MAX
SN74HC594
–40°C to 85°C
MIN
SN74HC594
–40°C to 125°C
MAX
MIN
UNIT
MAX
2V
5
3.3
4
4
4.5 V
25
17
20
20
6V
29
20
24
24
2V
100
150
125
130
4.5 V
20
30
25
27
6V
17
25
21
23
2V
100
150
125
130
4.5 V
20
30
25
27
6V
17
25
21
23
2V
90
135
110
115
4.5 V
18
27
22
24
6V
15
23
19
21
2V
90
135
110
115
4.5 V
18
27
22
24
6V
15
23
19
21
2V
50
75
63
68
4.5 V
10
15
13
15
6V
9
13
11
13
2V
20
20
20
20
4.5 V
10
10
10
10
6V
10
10
10
10
2V
5
5
5
5
4.5 V
5
5
5
5
6V
5
5
5
5
2V
5
5
5
5
4.5 V
5
5
5
5
6V
5
5
5
5
MHz
ns
ns
ns
ns
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This setup time ensures that the output register receives stable data from the shift-register outputs. The clocks may be tied together, in
which case the output register is one clock pulse behind the shift register.
6.9 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
TYP
UNIT
No load
395
pF
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SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH′
Figure 1. Timing Diagram
8
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30
60
25
50
20
40
TPD (ns)
TPD (ns)
6.10 Typical Characteristics
15
30
10
20
5
10
0
-100
0
-50
0
50
Temperature
100
150
D001
Figure 2. SN74HC594 TPD vs. Temperature
0
2
4
VCC
6
8
D002
Figure 3. SN74HC594 TPD vs. VCC
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7 Parameter Measurement Information
From Output
Under Test
V CC
High-Level
Pulse
Test
Point
50%
50%
0V
tw
CL
(see Note A)
VCC
Low-Level
Pulse
50%
50%
0V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
VCC
50%
50%
0V
tPLH
Reference
Input
VCC
50%
In-Phase
Output
0V
tsu
Data
Input 50%
10%
90%
tr
tPHL
VCC
50%
10% 0 V
Out-of-Phase
Output
90%
90%
VOH
50%
10%
VOL
tf
tPLH
50%
10%
50%
10%
tf
tf
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
90%
tr
th
90%
50%
10%
tPHL
90%
VOH
VOL
tr
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
A.
CL includes probe and test-fixture capacitance.
B.
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having
the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
C.
For clock inputs, fmax is measured when the input duty cycle is 50%.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
tPLH and tPHL are the same as tpd.
F.
tf and tr are the same as tt.
Figure 4. Load Circuit and Voltage Waveforms
10
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8 Detailed Description
8.1 Overview
The SNx4HC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding clear (RCLR, SRCLR) inputs are provided on both the shift and
storage registers. A serial (QH’) output is provided for cascading purposes.
Both the shift register (SRCLK) and storage register (RCLK) clocks are positive edge triggered. If both clocks are
connected together, the shift register always is one count pulse ahead of the storage register.
The parallel (QA − QH) outputs have high-current capability. QH’ is a standard output.
8.2 Functional Block Diagram
RCLR
RCLK
SRCLR
SRCLK
SER
13
12
10
11
1D
C1
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
2S
2R
C2
R
R
3R
C3
3S
14
15
1
QB
2
QC
3
4
5
6
7
9
Pin numbers shown are for the D, DW, J, N, and W packages.
QA
QD
QE
QF
QG
QH
QH′
Figure 5. Logic Diagram (Positive Logic)
8.3 Feature Description
The wide operating range allows the device to be used in a variety of systems that use different logic levels. The
high-current outputs allow the device to drive medium loads without significant drops in output voltage. In
addition, the low power consumption makes this device a good choice for portable and battery power-sensitive
applications.
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8.4 Device Functional Modes
Table 1. Function Table
INPUTS
SER
12
SRCLK SRCLR
RCLK
RCLR
FUNCTION
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L
↓
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
↑
H
Shift register data is stored in the storage register.
X
X
X
↓
H
Storage register state is not changed.
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Copyright © 1982–2015, Texas Instruments Incorporated
SN74HC594
SN54HC594, SN74HC594
www.ti.com
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HC594 is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs.
9.2 Typical Application
Figure 6. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
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Copyright © 1982–2015, Texas Instruments Incorporated
SN74HC594
13
SN54HC594, SN74HC594
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Rise time and fall time specs see (Δt/ΔV) in Recommended Operating Conditions table.
– Specified High and low levels. See (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
• Recommended output conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part
– Outputs should not be pulled above VCC
9.2.3 Application Curves
Figure 7. Switching Characteristics Comparison
14
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Copyright © 1982–2015, Texas Instruments Incorporated
SN74HC594
SN54HC594, SN74HC594
www.ti.com
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF
or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor
should be installed as close as possible to the power terminal for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.
11.2 Layout Example
Figure 8. Layout Recommendation
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Copyright © 1982–2015, Texas Instruments Incorporated
SN74HC594
15
SN54HC594, SN74HC594
SCLS040G – DECEMBER 1982 – REVISED MARCH 2015
www.ti.com
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
Implications of Slow or Floating CMOS Inputs, SCBA004
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
16
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Copyright © 1982–2015, Texas Instruments Incorporated
SN74HC594
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74HC594D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DW
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DWE4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DWG4
ACTIVE
SOIC
DW
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DWR
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DWRE4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594DWRG4
ACTIVE
SOIC
DW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HC594
SN74HC594N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74HC594N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74HC594DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74HC594DWR
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
SN74HC594DWRG4
SOIC
DW
16
2000
330.0
16.4
10.75
10.7
2.7
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74HC594DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74HC594DWR
SOIC
DW
16
2000
350.0
350.0
43.0
SN74HC594DWRG4
SOIC
DW
16
2000
350.0
350.0
43.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
DW 16
SOIC - 2.65 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT
7.5 x 10.3, 1.27 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224780/A
www.ti.com
PACKAGE OUTLINE
DW0016A
SOIC - 2.65 mm max height
SCALE 1.500
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
14X 1.27
16
1
2X
8.89
10.5
10.1
NOTE 3
8
9
0.51
0.31
0.25
C A B
16X
B
7.6
7.4
NOTE 4
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0.3
0.1
0 -8
1.27
0.40
DETAIL A
(1.4)
TYPICAL
4220721/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SEE
DETAILS
SYMM
16
1
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
LAND PATTERN EXAMPLE
SCALE:7X
METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
0.07 MAX
ALL AROUND
METAL
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220721/A 07/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0016A
SOIC - 2.65 mm max height
SOIC
16X (2)
SYMM
1
16
16X (0.6)
SYMM
14X (1.27)
9
8
R0.05 TYP
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:7X
4220721/A 07/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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