Texas Instruments | SN74AHCT1G00 Single 2-Input Positive-NAND Gate (Rev. N) | Datasheet | Texas Instruments SN74AHCT1G00 Single 2-Input Positive-NAND Gate (Rev. N) Datasheet

Texas Instruments SN74AHCT1G00 Single 2-Input Positive-NAND Gate (Rev. N) Datasheet
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SN74AHCT1G00
SCLS316N – MARCH 1995 – REVISED MARCH 2015
SN74AHCT1G00 Single 2-Input Positive-NAND Gate
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
1
•
Operating Range of 4.5 V to 5.5 V
Maximum tpd of 7.1 ns at 5 V
Low Power Consumption, 10-μA Maximum ICC
±8-mA Output Drive at 5 V
Inputs Are TTL-Voltage Compatible
Latch-up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
IP Phones
Notebook PCs
Printers
Access Control and Security
Solar Inverters
3 Description
The SN74AHCT1G00 device performs the Boolean
function Y = A × B or Y = A + B in positive logic.
Device Information(1)
PART NUMBER
SN74AHCT1G00
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SC-70 (5)
2.00 mm × 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
B
1
2
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHCT1G00
SCLS316N – MARCH 1995 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
3
4
4
4
5
5
5
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1
8.2
8.3
8.4
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
7
7
7
7
Application and Implementation .......................... 8
9.1 Application Information.............................................. 8
9.2 Typical Application ................................................... 8
10 Power Supply Recommendations ..................... 10
11 Layout................................................................... 10
11.1 Layout Guidelines ................................................. 10
11.2 Layout Example .................................................... 10
12 Device and Documentation Support ................. 11
12.1 Trademarks ........................................................... 11
12.2 Electrostatic Discharge Caution ............................ 11
12.3 Glossary ................................................................ 11
13 Mechanical, Packaging, and Orderable
Information ........................................................... 11
4 Revision History
Changes from Revision M (January 2003) to Revision N
Page
•
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Extended operating temperature range to 125°C................................................................................................................... 4
2
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5 Pin Configuration and Functions
DBV or DCK Package
5-PIN SOT-23 OR SC-70
Top View
A
B
GND
1
5
VCC
4
Y
2
3
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
A
I
Input A
2
B
I
Input B
3
GND
—
Ground Pin
4
Y
O
Output Y
5
VCC
—
Power Pin
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VCC
Supply voltage
–0.5
7
V
VI
Input voltage (2)
–0.5
7
V
VO
Output voltage (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
–20
20
mA
IO
Continuous output current
VO = 0 to VCC
–25
25
mA
Tstg
(1)
(2)
Continuous current through VCC or GND
–50
50
mA
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
–8
mA
IOL
Low-level output current
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
V
2
V
0.8
V
0
5.5
V
0
VCC
–40
V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
6.4 Thermal Information
SN74AHCT1G00
THERMAL METRIC
(1)
DBV (SOT-23)
DCK (SC-70)
5 PINS
5 PINS
RθJA
Junction-to-ambient thermal resistance
208.2
287.6
RθJC(top)
Junction-to-case (top) thermal resistance
76.1
97.7
RθJB
Junction-to-board thermal resistance
52.5
65
ψJT
Junction-to-top characterization parameter
4
2
ψJB
Junction-to-board characterization parameter
51.8
64.2
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
IOH = –8 mA
IOL = 50 µA
VOL
IOL = 8 mA
TA = 25°C
VCC
4.5 V
MIN
TYP
4.4
4.5
–40°C to 85°C
MAX
3.94
4.5 V
MIN
–40°C to 125°C
MAX
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.1
0.36
0.44
0.44
±0.1
±1
±1
µA
V
II
VI = 5.5 V or GND
0 V to 5.5 V
ICC
VI = VCC or GND,
IO = 0
5.5 V
1
10
10
µA
ΔICC (1)
One input at 3.4 V,
Other inputs at VCC or
GND
5.5 V
1.35
1.5
1.5
mA
Ci
VI = VCC or GND
10
10
10
pF
(1)
4
5V
2
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
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6.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 15 pF
tPLH
tPHL
tPLH
tPHL
TA = 25°C
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
5
6.2
1
7.1
1
8
5
6.2
1
7.1
1
8
5.5
7.9
1
9
1
10
5.5
7.9
1
9
1
10
UNIT
ns
ns
6.7 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
TYP
UNIT
10.5
pF
6.8 Typical Characteristics
5
4.5
4
TPD (ns)
3.5
3
2.5
2
1.5
1
0.5
0
-100
-50
0
50
Temperature
100
150
D001
Figure 1. TPD vs Temperature
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuits and Voltage Waveforms
6
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8 Detailed Description
8.1 Overview
The SN74AHCT1G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.
The device has TTL inputs that allow up translation from 3.3 V to 5 V. The inputs are high impedance when
Vcc = 0 V.
8.2 Functional Block Diagram
A
B
1
4
2
Y
Figure 3. Logic Diagram (Positive Logic)
8.3 Feature Description
The device is ideal for operating in a 5-V logic system. The low propagation delay allows fast switching and
higher speeds of operation. In addition, the low power consumption makes this device a good choice for portable
and battery power-sensitive applications.
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUT
A
B
Y
H
H
L
L
X
H
X
L
H
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AHCT1G00 is a low drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The TTL inputs can except voltages down to 3.3 V and translate up to 5 V.
9.2 Typical Application
Figure 4. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
8
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Typical Application (continued)
9.2.3 Application Curves
Figure 5. Switching Characteristics Comparison
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF
or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different
frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor
should be installed as close as possible to the power terminal for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.
11.2 Layout Example
Figure 6. Layout Recommendation
10
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74AHCT1G00DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
B00G
74AHCT1G00DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
B00G
74AHCT1G00DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BA3
74AHCT1G00DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BA3
74AHCT1G00DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
BA3
SN74AHCT1G00DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(B003, B00G, B00J,
B00S)
SN74AHCT1G00DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(B003, B00G, B00J,
B00S)
SN74AHCT1G00DCK3
ACTIVE
SC70
DCK
5
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 85
BAY
SN74AHCT1G00DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(BA3, BAG, BAJ, BA
S)
SN74AHCT1G00DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(BA3, BAG, BAJ, BA
S)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
4-Apr-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
74AHCT1G00DBVRG4
SOT-23
3000
178.0
9.0
DBV
5
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
74AHCT1G00DBVTG4
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
74AHCT1G00DCKRG4
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
74AHCT1G00DCKTG4
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74AHCT1G00DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHCT1G00DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHCT1G00DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHCT1G00DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHCT1G00DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHCT1G00DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74AHCT1G00DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
74AHCT1G00DBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
74AHCT1G00DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
74AHCT1G00DCKTG4
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHCT1G00DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHCT1G00DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHCT1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHCT1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHCT1G00DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHCT1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHCT1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHCT1G00DCKT
SC70
DCK
5
250
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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