Texas Instruments | SNx4LV594A 8-Bit Shift Registers With Output Registers (Rev. J) | Datasheet | Texas Instruments SNx4LV594A 8-Bit Shift Registers With Output Registers (Rev. J) Datasheet

Texas Instruments SNx4LV594A 8-Bit Shift Registers With Output Registers (Rev. J) Datasheet
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SN54LV594A, SN74LV594A
SCLS413J – APRIL 2005 – REVISED MARCH 2015
SNx4LV594A 8-Bit Shift Registers With Output Registers
1 Features
3 Description
•
•
•
The SN74LV594A devices are 8-bit shift registers
designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
•
•
2-V to 5.5-V VCC Operation
Maximum tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
8-Bit Serial-In, Parallel-Out Shift Registers With
Storage
Independent Direct Overriding Clears on Shift and
Storage Registers
Independent Clocks for Shift and Storage
Registers
Latch-up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
SN74LV594A
PACKAGE
BODY SIZE (NOM)
SSOP (16)
6.20 mm × 5.30 mm
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
2 Applications
•
•
•
•
ECG Electrocardiograms
Storage Servers
EPOS, ECR, and Cash Drawers
Servers and High-Performance Computing
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV594A, SN74LV594A
SCLS413J – APRIL 2005 – REVISED MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics: VCC = 2.5 V ± 0.2 V ........ 6
Switching Characteristics: VCC = 3.3 V ± 0.3 V ........ 7
Switching Characteristics: VCC = 5 V ± 0.5 V ........... 7
Timing Requirements: VCC = 2.5 V ± 0.2 V .............. 8
Timing Requirements: VCC = 3.3 V ± 0.3 V ............ 8
Timing Requirements: VCC = 5 V ± 0.5 V ............... 9
Noise Characteristics .............................................. 9
Operating Characteristics........................................ 9
Typical Characteristics .......................................... 10
7
8
Parameter Measurement Information ................ 11
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
13
14
14
Application and Implementation ........................ 15
9.1 Application Information............................................ 15
9.2 Typical Application ................................................. 15
10 Power Supply Recommendations ..................... 17
11 Layout................................................................... 17
11.1 Layout Guidelines ................................................. 17
11.2 Layout Example .................................................... 17
12 Device and Documentation Support ................. 18
12.1 Trademarks ........................................................... 18
12.2 Electrostatic Discharge Caution ............................ 18
12.3 Glossary ................................................................ 18
13 Mechanical, Packaging, and Orderable
Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (April 2005) to Revision J
•
2
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
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SN74LV594A
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SCLS413J – APRIL 2005 – REVISED MARCH 2015
5 Pin Configuration and Functions
D, DB, or PW Package
16-Pin SOIC, SSOP, or TSSOP
Top View
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
QB
O
Output B
2
QC
O
Output C
3
QD
O
Output D
4
QE
O
Output E
5
QF
O
Output F
6
QG
O
Output G
7
QH
O
Output H
8
GND
–
Ground pin
9
QH'
O
QH inverted
10
SRCLR
I
Serial clear
11
SRCLK
I
Serial clock
12
RCLK
I
Storage clock
13
RCLR
I
Storage clear
14
SER
I
Serial input
15
QA
O
Output A
16
Vcc
–
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
VCC
(1)
MIN
MAX
UNIT
Supply voltage
−0.5
7
V
(2)
VI
Input voltage
−0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
−0.5
7
V
VO
Output voltage (2) (3)
−0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
−20
IOK
Output clamp current
VO< 0
−50
IO
Continuous output current
VO = 0 to VCC
−25
25
mA
Tstg
Storage temperature
−65
150
°C
(1)
(2)
(3)
mA
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LV594A (2)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
SN74LV594A
MIN
MAX
2
5.5
Low-level input voltage
MAX
2
5.5
1.5
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
UNIT
V
V
VCC × 0.7
VCC = 2 V
VIL
MIN
0.5
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
V
VI
Input voltage
0
5.5
0
5.5
VO
Output voltage
0
VCC
0
VCC
V
–50
–50
µA
–2
–2
VCC = 2 V
IOH
High-level input current
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
6
6
–12
–12
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
6
6
12
12
200
200
100
100 ns/V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOL
Low-level output current
VCC = 4.5 V to 5.5 V
Δt/Δv
Input transition rise or fall rate VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
20
TA
(1)
(2)
V
Operating free-air temperature
–55
125
mA
µA
mA
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report
Implications of Slow or Floating CMOS Inputs, SCBA004.
Product Preview
6.4 Thermal Information
SN74LV594A
THERMAL METRIC (1)
RθJA
Junction-to-ambient thermal resistance
RθJC(top) Junction-to-case (top) thermal resistance
D (SOIC)
DB (SSOP)
PW (TSSOP)
16 PINS
16 PINS
16 PINS
80.2
97.8
106.1
40.3
48.1
40.8
RθJB
Junction-to-board thermal resistance
38
48.5
51.1
ψJT
Junction-to-top characterization parameter
9
10
3.8
ψJB
Junction-to-board characterization parameter
37.7
47.9
50.6
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
SN74LV594A
–40°C TO 85°C
SN54LV594A
VCC
MIN
TYP
MAX
MIN
TYP
SN74LV594A
–40°C TO 125°C
MAX
MIN
2 V to 5.5 V
IOH = –2 µA
2.3 V
IOH = –6 µA
3V
IOH = –12 µA
4.5 V
IOH = –50 µA
2 V to 5.5 V
0.1
0.1
IOH = –2 µA
2.3 V
0.4
0.4
0.4
IOH = –6 µA
3V
0.44
0.44
0.44
IOH = –12 µA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or
GND
0 to 5.5 V
±1
±1
±1
µA
ICC
VI = VCC of
GND, IO = 0
5.5 V
20
20
20
µA
Ioff
VI or VO = 0
to 5.5 V
0
5
5
5
µA
Ci
VI = VCC or
GND
3.3 V
VOL
VCC – 0.1
2
2
2
2.48
2.48
2.48
MAX
IOH = –50 µA
VOH
VCC – 0.1
UNIT
TYP
3.8
VCC – 0.1
3.8
V
3.8
3.5
0.1
3.5
V
pF
6.6 Switching Characteristics: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted). See Figure 1.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
LOAD
CAPACITANCE
TA = 25°C
TYP
CL = 15 pF
65 (1)
80 (1)
45 (1)
45
35
CL = 50 pF
60
70
40
40
30
6.4 (1)
MAX
10.6 (1)
MIN
1 (1)
QA – QH
6.3 (1)
10.4 (1)
1 (1)
7.4 (1)
12.1 (1)
1 (1)
7.2 (1)
11.6 (1)
1 (1)
QA – QH
7.9 (1)
12.7 (1)
1 (1)
QH’
7.4 (1)
11.9 (1)
1 (1)
SRCLK
tPLH
QH’
CL = 15 pF
tPHL
RCLK
tPHL
tPLH
tPHL
SRCLR
tPLH
tPHL
(1)
6
RCLR
11.1
(1
11.1
(1
MIN
MAX
MIN
MHz
1
11.1
1
12.5
1
11.1
1
12.5
1
12.8
1
15
1
12.8
1
15
1
13.6
1
15.5
)
1
13.1
1
15.5
)
)
12.8 (1
)
12.8 (1
)
13.6 (1
)
13.1 (1
ns
9.5
14.1
1
14.6
1
14.6
1
17
15.5
1
17.2
1
17.2
1
19.5
10.6
15.7
1
16.5
1
16.5
1
18.5
11.3
16.1
1
18.6
1
18.6
1
20.5
QA – QH
12.1
17.4
1
19
1
19
1
21
QH’
11.6
16.5
1
18.6
1
18.6
1
20.6
CL = 50 pF
UNIT
MAX
10.8
QA – QH
QH’
tPHL
MAX
SN74LV594A
–40°C TO 125°C
MIN
tPLH
tPHL
SN74LV594A
–40°C TO 85°C
SN54lv594A
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.7 Switching Characteristics: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted). See Figure 1.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CL = 15 pF
fmax
CL = 50 pF
tPLH
tPHL
SRCLK
tPLH
RCLK
tPHL
TA = 25°C
MIN
55
tPHL
SRCLR
tPLH
RCLR
tPHL
MIN
(1)
MIN
MAX
SN74LV594A
–40°C TO 125°C
MIN
70 (1)
70
60
50
50
40
MHz
1
8.5
1
10.5
8.8 (1)
1
8.8
1
10.5
5.4 (1)
9.1 (1)
1 (1)
9.7 (1)
1
9.7
1
11.5
5.5 (1)
9.2 (1)
1 (1)
9.9 (1)
1
9.9
1
11.6
6 (1)
9.8 (1)
1 (1)
10.6 (1)
1
10.6
1
12.1
5.6 (1)
9.2 (1)
1 (1)
10 (1)
1
10
1
12
1
11.1
1
11.1
1
12.5
1
13.1
1
13.1
1
15
1
12.4
1
12.4
1
14
1
13.9
1
13.9
1
15.5
QA – QH
1
14.4
1
14.4
1
16.1
QH’
1
14
1
14
1
16
QA – QH
CL = 50 pF
8.5
(1)
1 (1)
QA – QH
1
(1)
UNIT
MAX
8.2 (1)
CL = 15 pF
8
(1)
MAX
SN74LV594A
–40°C TO 85°C
4.9 (1)
QH’
tPHL
MAX
105
4.6
QH’
tPLH
TYP
SN54LV594A
80 (1) 120 (1)
QA – QH
QH’
tPHL
(1)
LOAD
CAPACITANCE
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.8 Switching Characteristics: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted). See Figure 1.
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CL = 15 pF
fmax
CL = 50 pF
tPLH
tPHL
SRCLK
tPLH
RCLK
SRCLR
tPLH
tPHL
(1)
CL = 15 pF
QA – QH
QA – QH
QH’
tPHL
RCLR
TA = 25°C
MIN
TYP
CL = 50 pF
QA – QH
QH’
SN54LV594A
MAX
135 (1) 170 (1)
120
MIN
MAX
SN74LV594A
–40°C TO 85°C
MIN
SN74LV594A
–40°C TO 125°C
UNIT
MAX
115 (1)
115
105
95
95
85
140
MHz
3.3 (1)
6.2 (1)
1 (1)
6.5 (1)
1
6.5
1
8
(1)
(1)
(1)
6.9 (1)
1
6.9
1
8.5
3.7
QH’
tPLH
tPHL
QA – QH
QH’
tPHL
tPHL
LOAD
CAPACITANCE
6.5
1
3.7 (1)
6.8 (1)
1 (1)
7.2 (1)
1
7.2
1
8.5
4.1
(1)
7.2
(1)
1
(1)
7.6 (1)
1
7.6
1
9
4.5
(1)
7.6
(1)
1
(1)
(1)
9.5
1
8.2
1
4.1 (1)
7.1 (1)
1 (1)
8.2
7.6 (1)
1
7.6
1
9
4.9
7.8
1
8.3
1
8.3
1
9.6
5.8
8.9
1
9.7
1
9.7
1
11
5.5
8.6
1
9.1
1
9.1
1
10.5
6
9.2
1
10.1
1
10.1
1
11.5
6.6
10
1
10.7
1
10.7
1
12
6
9.2
1
10.1
1
10.1
1
11.5
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.9 Timing Requirements: VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V. See Figure 1.
TA = 25°C
MIN
tw
Pulse duration
(1)
Hold time
MAX
MIN
MAX
MIN
7
7.5
7.5
8.5
6
6.5
6.5
7.5
5.5
5.5
5.5
6
8
9
9
10
8.5
9.5
9.5
10.5
6
6.8
6.8
7.5
RCLK high (inactive) before RCLK↑
6.7
7.6
7.6
8.5
SER after SRCLK↑
1.5
1.5
1.5
2
SCRCLR low before RCLK↑ (1)
SRCLR high (inactive) before
SRCLK↑
th
MIN
RCKR or SCRCLR low
SRCLK↑ before RCLK↑
Setup time
MAX
SN74LV594A
–40°C TO 125°C
RCLK or SRCLK high or low
SER before SRCLK↑
tsu
SN74LV594A
–40°C TO 85°C
SN54LV594A
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.10 Timing Requirements: VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V. See Figure 1.
TA = 25°C
MIN
tw
Pulse duration
RCLK or SRCLK high or low
RCKR or SCRCLR low
SER before SRCLK↑
SRCLK↑ before RCLK↑
tsu
th
(1)
8
Setup time
Hold time
SCRCLR low before RCLK↑ (1)
SN74LV594A
–40°C TO 85°C
SN54LV594A
MAX
MIN
MAX
MIN
MAX
SN74LV594A
–40°C TO 125°C
MIN
5.5
5.5
5.5
6.5
5
5
5
6
3.5
3.5
3.5
4
8
8.5
8.5
9.5
8
9
9
10
SRCLR high (inactive) before
SRCLK↑
4.2
4.8
4.8
5.5
RCLK high (inactive) before RCLK↑
4.6
5.3
5.3
6
SER after SRCLK↑
1.5
1.5
1.5
2
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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6.11 Timing Requirements: VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V. See Figure 1.
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time
th
(1)
Hold time
RCLK or SRCLK high or low
MAX
SN54LV594A
MIN
MAX
SN74LV594A
–40°C TO 85°C
MIN
SN74LV594A
–40°C TO 125°C
MAX
MIN
5
5
5
6
5.2
5.2
5.2
6.2
SER before SRCLK↑
3
3
3
3.5
SRCLK↑ before RCLK↑
5
5
5
6
SCRCLR low before RCLK↑ (1)
5
5
5
5.5
SRCLR high (inactive) before
SRCLK↑
2.9
3.3
3.3
4
RCLK high (inactive) before RCLK↑
3.2
3.7
3.7
4.5
2
2
2
2.5
RCKR or SCRCLR low
SER after SRCLK↑
UNIT
MAX
ns
ns
ns
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.12 Noise Characteristics (1)
over operating free-air temperature range (unless otherwise noted), VCC = 3.3 V, CL = 50 pF, TA = 25°C
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.5
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.1
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.8
VIH(V)
High-level dynamic input voltage
VIL(V)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
6.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
f = 10 MHz
VCC
TYP
3.3 V
93
5V
112
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Figure 1. Timing Diagram
6.14 Typical Characteristics
6
7
5
6
5
TPD (ns)
TPD (ns)
4
3
2
1
0
-50
0
50
Temperature
100
150
D001
Figure 2. TPD vs. Temperature at 3.3 V
10
3
2
1
0
-100
4
0
1
2
3
Vcc
4
5
6
D002
Figure 3. TPD vs. Vcc at 25°C
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7 Parameter Measurement Information
Figure 4. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV594A devices are 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
These devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register.
Separate clocks (RCLK, SRCLK) and direct overriding clear (RCLR, SRCLR) inputs are provided on the shift and
storage registers. A serial output (QH′) is provided for cascading purposes. The shift-register (SRCLK) and
storage-register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register
always is one clock pulse ahead of the storage register.
12
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8.2 Functional Block Diagram
Figure 5. Logic Diagram (Positive Logic)
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8.3 Feature Description
The device’s wide operating range allows it to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
14
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of shift register goes low. Other stages
store the data of previous stage, repectively.
H
↑
H
X
X
First stage of shift register goes high. Other stages
store the data of previous stage, respectively.
L
↓
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
↑
H
Shift register data is stored in the storage register.
X
X
X
↓
H
Storage register state is not changed.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV594A is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs.
9.2 Typical Application
Figure 6. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads
so consider routing and load conditions to prevent ringing.
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Typical Application (continued)
9.2.2 Detailed Design Procedure
• Recommended input conditions:
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
• Recommended output conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
9.2.3 Application Curves
Figure 7. Switching Characteristics Comparison
16
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC
terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal
for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that should be applied to any particular unused input depends on the function of the device. Generally they
will be tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs
section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float
when disabled.
11.2 Layout Example
Figure 8. Layout Example
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
18
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SN74LV594A
PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV594AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594ADE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWRE4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
SN74LV594APWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV594A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
5-Mar-2015
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV594ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV594APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV594APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV594APWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV594APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV594ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV594APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV594APWR
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV594APWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV594APWT
TSSOP
PW
16
250
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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