Texas Instruments | SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs (Rev. I) | Datasheet | Texas Instruments SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs (Rev. I) Datasheet

Texas Instruments SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs (Rev. I) Datasheet
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SN54LV240A, SN74LV240A
SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
SNx4LV240A Octal Inverting Buffers/Drivers With 3-State Outputs
1 Features
3 Description
•
•
•
These octal buffers/drivers with inverted outputs are
designed for 2-V to 5.5-V VCC operation.
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V at
VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Latch-Up Performance Exceeds 250 mA per
JESD 17
Ioff Supports Live Insertion, Partial Power-Down
Mode, and Back Drive Protection
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
The ’LV240A devices are designed specifically to
improve both the performance and density of 3-state
memory address drivers, clock drivers, and busoriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line
drivers with separate output-enable (OE) inputs.
When OE is low, the device passes inverted data
from the A inputs to the Y outputs. When OE is high,
the outputs are in the high-impedance state.
Device Information(1)
PART NUMBER
LV240A
2 Applications
•
•
•
PACKAGE
BODY SIZE (NOM)
TVSOP (14)
3.60 mm × 4.40 mm
SOIC (14)
8.65 mm × 3.91 mm
SOP (14)
10.30 mm × 5.30 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
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Network Switch
Health and Fitness / Wearables
4 Logic Diagram (Positive Logic)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
1Y4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV240A, SN74LV240A
SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Logic Diagram (Positive Logic) ............................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
7
7
7
8
8
8
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ±0.2 V .........
Switching Characteristics, VCC = 3.3 V ±0.3 V .........
Switching Characteristics, VCC = 5 V ±0.5 V ............
Noise Characteristics for SN74LV240A ....................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 14
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 15
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
14 Mechanical, Packaging, and Orderable
Information ........................................................... 15
5 Revision History
Changes from Revision H (April 2005) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Updated operating free-air temperature maximum from 85°C to 125°C for SN74LV240A ................................................... 5
2
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SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
6 Pin Configuration and Functions
SN54LV240A: J or W Package
SN74LV240A: DB, DGV, DW, NS, or PW Package
(Top View)
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
1A2
2Y3
1A3
2Y2
1A4
2OE
20
2
2Y4
1A1
1OE
VCC
1
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
1Y1
2A4
1Y2
2A3
1Y3
2Y1
GND
2A1
1Y4
2A2
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
SN54LV240A: FK Package
(Top View)
Pin Functions
PIN
I/O
1
1OE
Output enable 1
DESCRIPTION
2
1A1
1A1 input
3
2Y4
2Y4 output
4
1A2
1A2 input
5
2Y3
2Y3 output
6
1A3
1A3 input
7
2Y2
2Y2 output
8
1A4
1A4 input
9
2Y1
2Y1 output
10
GND
Ground pin
11
2A1
2A1 input
12
1Y4
1Y4 output
13
2A2
2A2 input
14
1Y3
1Y3 output
15
2A3
2A3 input
16
1Y2
1Y2 output
17
2A4
2A4 input
18
1Y1
1Y1 output
19
2OE
Output enable 2
20
VCC
Power pin
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature (unless otherwise noted)
VCC
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
VI
Input voltage
–0.5
7
V
VO
Voltage applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
35
mA
Tstg
(1)
(2)
(3)
(3)
–35
Continuous current through VCC or GND
–70
70
mA
Storage temperature
–65
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value is limited to 5.5-V maximum.
7.2 ESD Ratings
VALUE
V(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (A115-A)
(1)
(2)
4
UNIT
V
200
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
see
(1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 to 2.7 V
VCC × 0.7
VCC = 3 to 3.6 V
VCC × 0.7
VCC = 4.5 to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 to 2.7 V
VCC × 0.3
VCC = 3 to 3.6 V
VCC × 0.3
VCC = 4.5 to 5.5 V
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 3 to 3.6 V
Δt/Δv
–8
(1)
Operating free-air temperature
µA
2
VCC = 3 to 3.6 V
8
VCC = 4.5 to 5.5 V
16
VCC = 2.3 to 2.7 V
200
VCC = 3 to 3.6 V
100
VCC = 4.5 to 5.5 V
TA
mA
50
VCC = 2.3 to 2.7 V
Input transition rise or fall rate
µA
–16
VCC = 2 V
Low-level output current
V
–2
VCC = 4.5 to 5.5 V
IOL
V
–50
VCC = 2.3 to 2.7 V
High-level output current
V
VCC × 0.3
0
VCC = 2 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
SN54LV240A
–55
125
SN74LV240A
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, SCBA004.
7.4 Thermal Information
DW
THERMAL METRIC (1)
DB
DGV
NS
PW
20 PINS
RθJA
Junction-to-ambient thermal resistance (2)
79.2
94.5
116.2
76.7
102.4
RθJC(top)
Junction-to-case (top) thermal resistance
43.7
56.4
31.2
43.2
36.5
RθJB
Junction-to-board thermal resistance
47.0
49.7
57.7
44.2
53.6
ψJT
Junction-to-top characterization parameter
18.6
18.5
0.9
16.8
2.4
ψJB
Junction-to-board characterization parameter
46.5
49.3
57.0
43.8
52.9
(1)
(2)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TEST CONDITIONS
VCC
MIN
TYP
MAX
IOH = –50 µA
2 to 5.5 V
IOH = –2 mA
2.3 V
IOH = –8 mA
3V
IOH = –16 mA
4.5 V
IOL = 50 µA
2 to 5.5 V
IOL = 2 mA
2.3 V
IOL = 8 mA
3V
0.44
0.55
UNIT
VCC – 0.1
2
V
2.48
3.8
0.1
0.4
V
IOL = 16 mA
4.5 V
II
VI = 5.5 V or GND
0 to 5.5 V
±1
µA
IOZ
VO = VCC or GND
5.5 V
±5
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
µA
Ci
VI = VCC or GND
3.3 V
6
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2.3
pF
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7.6 Switching Characteristics, VCC = 2.5 V ±0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see )
PARAMETER
tpd
FROM (INPUT)
TO (OUTPUT)
LOAD
CAPACITANCE
TA = 25°C
MIN
A
ten
OE
tdis
OE
tpd
A
ten
OE
tdis
OE
Y
Y
CL = 15 pF
MAX UNIT
11.6 (1)
1 (2)
14 (2)
(1)
(2)
17 (2)
MAX
6.3 (1)
(1)
8.5
CL = 50 pF
MIN
TYP
14.6
9.7 (1)
14.1 (1)
1 (2)
16 (2)
8.2
14.4
1
17
10.3
17.8
1
21
14.2
19.2
1
21
tsk(o)
(1)
(2)
(3)
1
ns
ns
2 (3)
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
Value applies for SN74LV240A only
7.7 Switching Characteristics, VCC = 3.3 V ±0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see )
PARAMETER
FROM (INPUT)
tpd
A
ten
OE
tdis
OE
tpd
A
ten
OE
tdis
OE
TO (OUTPUT)
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
CL = 15 pF
CL = 50 pF
4.6 (1)
7.5 (1)
1 (2)
9 (2)
6.2 (1)
10.6 (1)
1 (2)
12.5 (2)
(1)
(1)
(2)
(2)
12.5
1
13.5
5.9
11
1
12.5
7.5
14.1
1
16
11.8
15
1
17
tsk(o)
(1)
(2)
(3)
MAX UNIT
MAX
8.3
Y
MIN
TYP
ns
ns
1.5 (3)
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
Value applies for SN74LV240A only
7.8 Switching Characteristics, VCC = 5 V ±0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see )
PARAMETER
FROM (INPUT)
tpd
A
ten
OE
tdis
TO (OUTPUT)
Y
LOAD
CAPACITANCE
CL = 15 pF
OE
tpd
A
ten
OE
tdis
OE
TA = 25°C
MIN
MIN
MAX UNIT
5.5 (1)
1 (2)
6.5 (2)
4.6 (1)
7.3 (1)
1 (2)
8.5 (2)
(1)
(1)
(2)
13.5 (2)
TYP
MAX
3.4 (1)
7.4
Y
CL = 50 pF
tsk(o)
(1)
(2)
(3)
12.2
1
4.4
7.5
1
8.5
5.6
9.3
1
10.5
9.7
14.2
1
15.5
1
ns
ns
1 (3)
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This note applies to SN54LV240A only: On products compliant to MIL-PRF-38535, this parameter is not production tested.
This values applies for SN74LV240A only
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7.9 Noise Characteristics for SN74LV240A
VCC = 3.3 V, CL = 50 pF, TA = 25°C (see
(1)
)
PARAMETER
MIN
TYP
VOL(P)
Quiet output, maximum dynamic VOL
0.56
VOL(V)
Quiet output, minimum dynamic VOL
–0.49
VOH(V)
Quiet output, minimum dynamic VOH
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
MAX
2.82
UNIT
V
2.31
0.99
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF, ƒ = 10 MHz
VCC
TYP
3.3 V
14
5V
16.4
UNIT
pF
7.11 Typical Characteristics
6
7
5
6
5
tpd (ns)
tpd (ns)
4
3
4
3
2
2
1
0
-100
1
0
-50
0
50
Temperature (°C)
100
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0
1
2
D001
Figure 1. tpd vs Temperature at 3.3-V VCC
8
150
3
VCC (V)
4
5
6
D002
Figure 2. tpd vs VCC at 25°C
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8 Parameter Measurement Information
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
VOH
50% VCC
VOL
50% VCC
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPLZ
Output
Waveform 1
S1 at VCC
(see Note B)
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
50% VCC
tPZL
tPHL
tPLH
In-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH
0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the
output control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
These octal buffers/drivers with inverted outputs are designed for 2-V to 5.5-V VCC operation.
The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When OE
is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in
the high-impedance state.
9.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
2
18
4
16
6
14
8
12
1Y1
1Y2
1Y3
1Y4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
10
Wide operating voltage range operates from 2-V to 5.5-V operation
Allow down voltage translation inputs accept voltages to 5.5 V
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
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9.4 Device Functional Modes
Table 1. Function Table
(Each Buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
L
L
L
H
H
X
Z
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV240A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where the data needs to be retained or latched. It can produce 8 mA of drive current at 3.3 V making it ideal for
driving multiple outputs and low-noise applications. The inputs are 5.5-V tolerant allowing it to translate down to
VCC.
10.2 Typical Application
Regulated 5 V
OE
VCC
OE
A1
Microcontroller or
System Logic
A8
Y1
Microcontroller
System Logic
LEDs
Y8
GND
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specifications see (Δt/ΔV) in Recommended Operating Conditions.
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 35 mA per output and 70 mA total for the part
– Outputs should not be pulled above VCC
12
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV240A SN74LV240A
SN54LV240A, SN74LV240A
www.ti.com
SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
Typical Application (continued)
10.2.3 Application Curve
Figure 6. Switching Characteristics Comparison
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV240A SN74LV240A
Submit Documentation Feedback
13
SN54LV240A, SN74LV240A
SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
www.ti.com
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in Recommended
Operating Conditions.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, TI recommends 0.1 µF and if there are multiple VCC terminals, then TI recommends .01 µF or .022 µF for
each power terminal. It is okay to parallel multiple bypass capacitors to reject different frequencies of noise. A 0.1
µF and 1 µF are commonly used in parallel. The bypass capacitor should be installed as close to the power
terminal as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC whichever make more sense or is more convenient. It is generally okay to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when
asserted. This does not disable the input section of the IOs so they cannot float when disabled.
12.2 Layout Example
VCC
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Recommendation
14
Submit Documentation Feedback
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV240A SN74LV240A
SN54LV240A, SN74LV240A
www.ti.com
SCLS384I – SEPTEMBER 1997 – REVISED FEBRUARY 2015
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV240A
Click here
Click here
Click here
Click here
Click here
SN74LV240A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1997–2015, Texas Instruments Incorporated
Product Folder Links: SN54LV240A SN74LV240A
Submit Documentation Feedback
15
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV240ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV240A
SN74LV240APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
SN74LV240APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV240A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LV240ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LV240ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV240ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV240ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV240APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LV240APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV240APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV240ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LV240ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LV240ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV240ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV240APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LV240APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV240APWT
TSSOP
PW
20
250
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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