Texas Instruments | SN74LVC4245A Octal Bus Transceiver and 3.3-V to 5-V Shifter With 3-State Outputs (Rev. I) | Datasheet | Texas Instruments SN74LVC4245A Octal Bus Transceiver and 3.3-V to 5-V Shifter With 3-State Outputs (Rev. I) Datasheet

Texas Instruments SN74LVC4245A Octal Bus Transceiver and 3.3-V to 5-V Shifter With 3-State Outputs (Rev. I) Datasheet
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SN74LVC4245A
SCAS375I – MARCH 1994 – REVISED JANUARY 2015
SN74LVC4245A Octal Bus Transceiver and 3.3-V to 5-V Shifter
With 3-State Outputs
1 Features
3 Description
•
•
•
This 8-bit (octal) noninverting bus transceiver
contains two separate supply rails; B port has VCCB,
which is set at 3.3 V, and A port has VCCA, which is
set at 5 V. This allows for translation from a 3.3-V to
a 5-V environment, and vice versa.
1
•
•
Bidirectional Voltage Translator
5.5 V on A Port and 2.7 V to 3.6 V on B Port
Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
ATCA Solutions
CPAP Machines
Cameras: Surveillance Analog
Chemical or Gas Sensors
CT Scanners
DLP 3D Machine Vision and Optical Networking
Digital Signage
ECGs: Electrocardiograms
Field Transmitters: Pressure Sensors and
Temperature Sensors
High-Speed Data Acquisition and Generation
HMI (Human Machine Interface)
RF4CE Remote Controls
Server Motherboards
Software Defined Radios (SDR)
Wireless LAN Cards and Data Access Cards
X-ray: Medical, Dental, and Baggage Scanners
The SN74LVC4245A device is designed for
asynchronous communication between data buses.
The device transmits data from the A bus to the B
bus or from the B bus to the A bus, depending on the
logic level at the direction-control (DIR) input. The
output-enable (OE) input can be used to disable the
device so the buses are effectively isolated. The
control circuitry (DIR, OE) is powered by VCCA.
The SN74LVC4245A device terminal out allows the
designer to switch to a normal all-3.3-V or all-5-V 20terminal SN74LVC4245 device without board relayout. The designer uses the data paths for pins
2–11 and 14–23 of the SN74LVC4245A device to
align with the conventional '245 terminal out.
Device Information(1)
PART NUMBER
PACKAGE
SN74LVC4245A
BODY SIZE (NOM)
SSOP (24)
8.20 mm × 5.30 mm
SOIC (24)
15.40 mm × 7.50 mm
TSSOP (24)
7.80 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC4245A
SCAS375I – MARCH 1994 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
4
5
5
5
6
6
7
7
7
Absolute Maximum Ratings ......................................
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
8.1 A Port ........................................................................ 8
8.2 B Port ........................................................................ 9
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 13
11.1 Power-Up Consideration ...................................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1 Trademarks ........................................................... 14
13.2 Electrostatic Discharge Caution ............................ 14
13.3 Glossary ................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision H (March 2005) to Revision I
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
2
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6 Pin Configuration and Functions
DB, DW, OR PW PACKAGE
(TOP VIEW)
(5 V) VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB (3.3 V)
VCCB (3.3 V)
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
Pin Functions
PIN
NO.
NAME
TYPE
—
DESCRIPTION
1
VCCA
Power supply for side A
2
DIR
I
3
A1
I/O
Transceiver I/O pin
4
A2
I/O
Transceiver I/O pin
5
A3
I/O
Transceiver I/O pin
6
A4
I/O
Transceiver I/O pin
7
A5
I/O
Transceiver I/O pin
8
A6
I/O
Transceiver I/O pin
9
A7
I/O
Transceiver I/O pin
10
A8
I/O
Transceiver I/O pin
11
GND
—
Ground
12
GND
—
Ground
13
GND
—
Ground
14
B8
I/O
Transceiver I/O pin
15
B7
I/O
Transceiver I/O pin
16
B6
I/O
Transceiver I/O pin
17
B5
I/O
Transceiver I/O pin
18
B4
I/O
Transceiver I/O pin
19
B3
I/O
Transceiver I/O pin
20
B2
I/O
Transceiver I/O pin
21
B1
I/O
Transceiver I/O pin
Direction control
22
OE
I
23
VCCB
—
Output Enable
Power supply for side B
24
VCCB
—
Power supply for side B
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted) (1)
VCCA
MIN
MAX
–0.5
6.5
(2)
–0.5
VCCA + 0.5
Control inputs
–0.5
6
–0.5
VCCA + 0.5
Supply voltage range
A port
UNIT
V
VI
Input voltage range
VO
Output voltage range
A port (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through each VCCA or GND
Tstg
(1)
(2)
Storage temperature range
–65
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 6 V maximum.
7.2 Absolute Maximum Ratings
over operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted) (1)
MIN
MAX
UNIT
VCCB
Supply voltage range
–0.5
4.6
V
VI
Input voltage range
B port (2)
–0.5
VCCB + 0.5
V
VO
Output voltage range
B port (2)
–0.5
VCCB + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCCB or GND
Tstg
(1)
(2)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 4.6 V maximum.
7.3 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.4 Recommended Operating Conditions
for VCCA = 4.5 V to 5.5 V (1)
VCCA
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VIA
Input voltage
VOA
Output voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
MIN
MAX
4.5
5.5
UNIT
V
2
V
0.8
V
0
VCCA
V
0
VCCA
V
–24
mA
24
mA
85
°C
–40
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.5 Recommended Operating Conditions
for VCCB = 2.7 V to 3.6 V (1)
MIN
MAX
2.7
3.6
UNIT
VCCB
Supply voltage
VIH
High-level input voltage
VCCB = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCCB = 2.7 V to 3.6 V
0.8
V
VIB
Input voltage
0
VCCB
V
VOB
Output voltage
0
VCCB
V
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
V
2
V
VCCB = 2.7 V
–12
VCCB = 3 V
–24
VCCB = 2.7 V
12
VCCB = 3 V
24
–40
mA
mA
85
°C
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI
application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.6 Thermal Information
SN74LVC4245A
THERMAL METRIC (1)
DB
DW
PW
UNIT
88
°C/W
24 PINS
RθJA
(1)
Junction-to-ambient thermal resistance
63
46
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.7 Electrical Characteristics
over recommended operating free-air temperature range for VCCA = 4.5 V to 5.5 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
IOH = –24 mA
VCCA
MIN
4.5 V
4.3
5.5 V
5.3
4.5 V
3.7
5.5 V
4.7
TYP (2) MAX
V
4.5 V
IOL = 100 μA
VOL
IOL = 24 mA
UNIT
0.2
5.5 V
0.2
4.5 V
0.55
V
5.5 V
0.55
II
Control inputs
VI = VCCA or GND
5.5 V
±1
μA
IOZ (3)
A port
VO = VCCA or GND
5.5 V
±5
μA
ICCA
VI = VCCA or GND,
IO = 0
5.5 V
80
μA
ΔICCA (4)
One input at 3.4 V,
Other inputs at VCCA or GND
5.5 V
1.5
mA
Ci
Control inputs
VI = VCCA or GND
Open
5
pF
Cio
A port
VO = VCCA or GND
5V
11
pF
(1)
(2)
(3)
(4)
VCCB = 2.7 V to 3.6 V.
All typical values are measured at VCC = 5 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
7.8 Electrical Characteristics
over recommended operating free-air temperature range for VCCB = 2.7 V to 3.6 V (unless otherwise noted) (1)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
2.7 V to 3.6 V
IOZ (3)
B port
2.4
IOH = –24 mA
3V
2
IOL = 100 μA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VO = VCCB or GND
IO = 0
ΔICCB (4)
One input at VCCB – 0.6
V,
Other inputs at VCCB or GND
(1)
(2)
(3)
(4)
6
VO = VCCB or GND
UNIT
VCC – 0.2
2.2
VI = VCCB or GND,
B port
MAX
3V
ICCB
Cio
MIN TYP (2)
2.7 V
IOH = –12 mA
VOL
VCCB
V
0.2
V
3.6 V
±5
μA
3.6 V
50
μA
2.7 V to 3.6 V
0.5
mA
3.3 V
11
pF
VCCA = 5 V ± 0.5 V.
All typical values are measured at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the associated
VCC.
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7.9 Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
VCCA = 5 V ± 0.5 V,
VCCB = 2.7 V to 3.6 V
UNIT
MIN
MAX
1
6.3
1
6.7
1
6.1
1
5
1
9
1
8.1
1
8.8
1
9.8
1
7
1
5.8
1
7.7
1
7.8
ns
ns
ns
ns
ns
ns
7.10 Operating Characteristics
VCCA = 4.5 V to 5.5 V, VCCB = 2.7 V to 3.6 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Outputs enabled
Power dissipation capacitance per transceiver
CL = 0,
Outputs disabled
TYP
f = 10 MHz
39.5
5
UNIT
pF
7.11 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
8.1 A Port
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
50% VCC
1.5 V
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
0V
tPZL
VCC
Input
3V
Output
Control
tPLZ
VCC
50% VCC
tPZH
50% VCC
VOL + 0.3 V
VOL
tPHZ
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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8.2 B Port
7V
S1
500 Ω
From Output
Under Test
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
Output
1.5 V
1.5 V
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
0V
tPLZ
tPZL
3V
Input
3V
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
3.5 V
1.5 V
VOL + 0.3 V
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
SN74LVC4245A is an 8-bit (octal) noninverting bus transceiver contains two separate supply rails; B port has
VCCB, which is set at 3.3 V, and A port has VCCA, which is set at 5 V. This allows for translation from a 3.3-V to a
5-V environment, and vice versa, designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated. The control circuitry (DIR, OE) is powered by VCCA.
9.2 Functional Block Diagram
Figure 5. Logic Diagram (Positive Logic)
2
DIR
22
OE
3
A1
21
B1
To Seven Other Channels
9.3 Feature Description
•
•
24 mA drive at 3-V supply
– Good for heavier loads and longer traces
Low VIH
– Allows 3.3-V to 5-V translation
9.4 Device Functional Modes
Function Table
INPUTS
10
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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10 Application and Implementation
10.1 Application Information
The SN74LVC4245A device pinout allows the designer to switch to a normal all-3.3-V or all-5-V 20-pin '245
device without board re-layout. The designer uses the data paths for pins 2–11 and 14–23 of the
SN74LVC4245A to align with the conventional SN74LVC4245 device's pinout. SN74LVC4245A is a high drive
CMOS device that can be used for a multitude of bus interface type applications where output drive or PCB trace
length is a concern.
10.2 Typical Application
3V
5V
VCCA
DIR
VCCB
B1
C/System
Logic/LEDs
OE
C or System
Logic
B8
A1
A8
GND
Figure 6. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
2. Recommend Output Conditions:
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
– Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
output current.
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Product Folder Links: SN74LVC4245A
11
SN74LVC4245A
SCAS375I – MARCH 1994 – REVISED JANUARY 2015
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
100
60
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
80
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
VOL – V
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 7. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
12
0.5
Figure 8. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
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Product Folder Links: SN74LVC4245A
SN74LVC4245A
www.ti.com
SCAS375I – MARCH 1994 – REVISED JANUARY 2015
11 Power Supply Recommendations
11.1 Power-Up Consideration
(1)
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device terminals. Take these precautions to guard against such powerup problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B bus),
ramp it with VCCA. Otherwise, keep DIR low.
(1)
Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 9 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 9. Layout Diagram
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Product Folder Links: SN74LVC4245A
13
SN74LVC4245A
SCAS375I – MARCH 1994 – REVISED JANUARY 2015
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1994–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC4245A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC4245ADBR
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245ADBRE4
ACTIVE
SSOP
DB
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245ADW
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245ADWE4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245ADWG4
ACTIVE
SOIC
DW
24
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245ADWR
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245ADWRE4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245ADWRG4
ACTIVE
SOIC
DW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LVC4245A
SN74LVC4245APW
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWG4
ACTIVE
TSSOP
PW
24
60
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWR
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWRE4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWRG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWT
ACTIVE
TSSOP
PW
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
SN74LVC4245APWTG4
ACTIVE
TSSOP
PW
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LJ245A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC4245A :
• Enhanced Product: SN74LVC4245A-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC4245ADBR
SSOP
DB
24
2000
330.0
16.4
8.2
8.8
2.5
12.0
16.0
Q1
SN74LVC4245ADWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74LVC4245ADWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74LVC4245ADWRG4
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
SN74LVC4245APWR
TSSOP
PW
24
2000
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
SN74LVC4245APWT
TSSOP
PW
24
250
330.0
16.4
6.95
8.3
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC4245ADBR
SSOP
DB
24
2000
367.0
367.0
38.0
SN74LVC4245ADWR
SOIC
DW
24
2000
350.0
350.0
43.0
SN74LVC4245ADWR
SOIC
DW
24
2000
364.0
361.0
36.0
SN74LVC4245ADWRG4
SOIC
DW
24
2000
350.0
350.0
43.0
SN74LVC4245APWR
TSSOP
PW
24
2000
367.0
367.0
38.0
SN74LVC4245APWT
TSSOP
PW
24
250
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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