Texas Instruments | SN74LVC245A Octal Bus Transceiver With 3-State Outputs (Rev. X) | Datasheet | Texas Instruments SN74LVC245A Octal Bus Transceiver With 3-State Outputs (Rev. X) Datasheet

Texas Instruments SN74LVC245A Octal Bus Transceiver With 3-State Outputs (Rev. X) Datasheet
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SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015
SN74LVC245A Octal Bus Transceiver With 3-State Outputs
1 Features
2 Applications
•
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•
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•
•
•
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1
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Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 6.3 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode and Back Drive protection
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With 3.3-V VCC)
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 1000-V Charged-Device Model
Cable Modem Termination Systems
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
These octal bus transceivers are designed for 1.65-V
to 3.6-V VCC operation. The ’LVC245A devices are
designed for asynchronous communication between
data buses.
Device Information(1)
PART NUMBER
SN74LVC245A
PACKAGE (PIN)
BODY SIZE
VQFN (20)
4.50 mm × 3.50 mm
SSOP (20)
7.50 mm × 5.30 mm
TSSOP (20)
6.50 mm × 4.40 mm
TVSOP (20)
5.00 mm × 4.40 mm
SOIC (20)
12.80 mm × 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
4
4
5
5
6
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision W (May 2013) to Revision X
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
Changes from Revision V (September 2010) to Revision W
•
2
Page
Added –40°C to 125°C temperature specification to Recommended Operating Conditions table. ...................................... 5
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6 Pin Configuration and Functions
GQN OR ZQN PACKAGE
(TOP VIEW)
1
2
3
4
A
B
C
D
E
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
VCC
1
1
20
19 OE
18 B1
2
3
17 B2
16 B3
4
5
15 B4
14 B5
6
7
13 B6
12 B7
8
9
GND
10
11
B8
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
DIR
RGY PACKAGE
(TOP VIEW)
DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NAME
DB, DGV,
DW, NS, PW,
and RGY
GQN or ZQN
A1
2
A1
I/O
Transceiver I/O pin
A2
3
B3
I/O
Transceiver I/O pin
A3
4
B1
I/O
Transceiver I/O pin
A4
5
C2
I/O
Transceiver I/O pin
A5
6
C1
I/O
Transceiver I/O pin
A6
7
D3
I/O
Transceiver I/O pin
A7
8
D1
I/O
Transceiver I/O pin
A8
9
E2
I/O
Transceiver I/O pin
B1
18
B4
I/O
Transceiver I/O pin
B2
17
B2
I/O
Transceiver I/O pin
B3
16
C4
I/O
Transceiver I/O pin
B4
15
C3
I/O
Transceiver I/O pin
B5
14
D4
I/O
Transceiver I/O pin
B6
13
D2
I/O
Transceiver I/O pin
B7
12
E4
I/O
Transceiver I/O pin
B8
11
E3
I/O
Transceiver I/O pin
DIR
1
A2
I
Direction control. When high, the signal propagates from A to B. When low, the signal
propagates from B to A.
Output enable
TYPE
DESCRIPTION
OE
19
A4
I
GND
10
E1
—
Ground
VCC
20
A3
—
Power pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
PARAMETER
V(ESD)
(1)
(2)
4
Electrostatic
discharge
DEFINITION
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
TA = 25°C
VCC
Supply voltage
VIH
High-level input
voltage
Operating
Data retention only
MIN
MAX
MIN
MAX
MIN
MAX
1.65
3.6
1.65
3.6
1.65
3.6
1.5
1.5
0.65 × VCC
0.65 × VCC
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
1.7
1.7
VCC = 2.7 V to 3.6 V
2
2
2
VCC = 1.65 V to 1.95 V
Low-level input
voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
High-level output
current
IOH
0.35 ×
VCC
0.35 ×
VCC
0.7
0.7
0.7
0.8
0.8
0
5.5
0
5.5
V
0
VCC
0
VCC
0
VCC
V
–4
–4
–4
VCC = 2.3 V
–8
–8
–8
VCC = 2.7 V
–12
–12
–12
VCC = 3 V
–24
–24
–24
4
4
4
VCC = 2.3 V
8
8
8
VCC = 2.7 V
12
12
12
VCC = 3 V
24
24
24
10
10
10
Low-level output
current
Δt/Δv
Input transition rise or fall rate
V
5.5
VCC = 1.65 V
IOL
V
V
0.35 × VCC
0.8
UNIT
0
VCC = 1.65 V
(1)
–40°C TO 125°C
1.5
VCC = 1.65 V to 1.95 V
VIL
–40°C TO 85°C
mA
mA
ns/V
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC245A
THERMAL METRIC
(1)
DB
(2)
DGV
(2)
DW
(2)
GQN or
ZQN (2)
N (2)
NS (2)
PW (2)
RGY (3)
59.2
83.6
108.1
44.0
UNI
T
20 PINS
RθJA
Junction-to-ambient thermal
resistance
106.5
124.1
92.9
RθJC(t
Junction-to-case(top) thermal
resistance
68.1
39.5
60.6
44.9
49.4
43.0
53.0
RθJB
Junction-to-board thermal
resistance
61.7
65.5
60.4
40.1
51.2
59.1
22.1
ψJT
Junction-to-top characterization
parameter
28.5
2.1
28.2
29.9
21.9
4.7
3.0
ψJB
Junction-to-board
characterization parameter
61.2
64.9
60.0
39.9
50.8
58.6
22.2
—
—
—
—
—
—
16.6
op)
RθJC(b Junction-to-case(bottom)
thermal resistance
ot)
(1)
(2)
(3)
78
°C/
W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
Control
inputs
II
MIN
TYP
–40°C TO 85°C
MAX
–40°C TO 125°C
MIN MAX
MIN
IOH = –100 μA
1.65 V
to
3.6 V
VCC – 0.2
VCC – 0.2
VCC – 0.2
IOH = –4 mA
1.65 V
1.29
1.2
1.1
IOH = –8 mA
2.3 V
1.9
1.7
1.6
2.7 V
2.2
2.2
2.1
IOH = –12 mA
VOL
TA = 25°C
VCC
MAX
UNIT
V
3V
2.4
2.4
2.3
IOH = –24 mA
3V
2.3
2.2
2.1
IOL = 100 μA
1.65 V
to
3.6 V
0.1
0.2
0.2
IOL = 4 mA
1.65 V
0.24
0.45
0.60
IOL = 8 mA
2.3 V
0.3
0.7
0.75
IOL = 12 mA
2.7 V
0.4
0.4
0.6
IOL = 24 mA
3V
0.55
0.55
0.75
3.6 V
±1
±5
±10
μA
VI = 0 to 5.5 V
V
Ioff
VI or VO = 5.5 V
0
±1
±10
±20
μA
IOZ (1)
VO = 0 to 5.5 V
3.6 V
±1
±10
±20
μA
1
10
30
1
10
30
500
500
5000
VI = VCC or GND
ICC
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
One input at VCC – 0.6 V,
Other inputs at VCC or GND
ΔICC
3.6 V
2.7 V to
3.6 V
μA
μA
Ci
Control
inputs
VI = VCC or GND
3.3 V
4
pF
Cio
A or B
ports (3)
VI = VCC or GND
3.3 V
5.5
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25 C.
This applies in the disabled state only.
For I/O ports, the parameter Ioz includes the input leakage current.
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
TO
(OUTPUT)
A or B
OE
OE
B or A
A or B
A or B
VCC
6
–40°C TO
85°C
–40°C TO
125°C
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
1.8 V ± 0.15 V
1
6
12.2
1
12.7
1
13.7
2.5 V ± 0.2 V
1
3.9
7.8
1
8.3
1
9.1
2.7 V
1
4.2
7.1
1
7.3
1
8.3
3.3 V ± 0.3 V
1.5
3.8
6.1
1.5
6.3
1.5
7.3
1.8 V ± 0.15 V
1
7
14.8
1
15.3
1
16.8
2.5 V ± 0.2 V
1
4.5
10
1
10.5
1
12
2.7 V
1
5.4
9.3
1
9.5
1
11
3.3 V ± 0.3 V
1.5
4.4
8.3
1.5
8.5
1.5
10
1.8 V ± 0.15 V
1
7.8
16.5
1
17
1
18
2.5 V ± 0.2 V
1
4
9
1
9.5
1
10.5
2.7 V
1
4.4
8.3
1
8.5
1
9.5
1.7
4.1
7.3
1.7
7.5
1.7
8.5
3.3 V ± 0.3 V
tsk(o)
TA = 25°C
3.3 V ± 0.3 V
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1
1.5
ns
ns
ns
ns
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7.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Outputs enabled
Cpd
Power dissipation capacitance per transceiver
f = 10 MHz
Outputs disabled
VCC
TYP
1.8 V
42
2.5 V
43
3.3 V
45
1.8 V
1
2.5 V
1
3.3 V
2
UNIT
pF
7.8 Typical Characteristics
10
14
12
VCC = 3 V,
TA = 25°C
tpd – Propagation Delay Time – ns
tpd – Propagation Delay Time – ns
VCC = 3 V,
TA = 25°C
One Output Switching
Four Outputs Switching
Eight Outputs Switching
10
8
6
4
One Output Switching
Four Outputs Switching
Eight Outputs Switching
8
6
4
2
2
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 1. Propagation Delay (Low to High Transition)
vs Load Capacitance
0
50
100
150
200
250
300
CL – Load Capacitance – pF
Figure 2. Propagation Delay (High to Low Transition)
vs Load Capacitance
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
This octal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC245A device is designed for asynchronous communication between data buses. This device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses
effectively are isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a
pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a
translator in a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
1
DIR
19
OE
A1
2
18
B1
To Seven Other Channels
Pin numbers shown are for the DB, DGV, DW, N, NS, PW, and RGY packages.
9.3 Feature Description
•
•
Allows down voltage translation
– 5 V to 3.3 V
– 5 V or 3.3 V to 1.8 V
Inputs accept voltage levels up to 5.5 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74LVC245A is a high drive CMOS device that can be used for a multitude of bus interface type applications
where output drive or PCB trace length is a concern. The inputs can accept voltages to 5.5 V at any valid VCC
making it ideal for down translation.
10.2 Typical Application
Regulated 1.8 V
Regulated 1.65 V to 3.6 V
Regulated 5 V
SN74LVC245A
1OE
A1
uC
SN74LVC245A
1OE VCC
DIR
A1
B1
VCC
DIR
B1
uC
System Logic
LEDs/Relays
or
Other System
Boards
A8
B8
uC
System Logic
LEDs/Relays
uC
System Logic
LEDs/Relays
A8
GND
B8
GND
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifcations, see (Δt/ΔV) in the Recommended Operating Conditions table.
– For specified high and low levels, see (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed (Continuous current through
VCC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above VCC.
10
Submit Documentation Feedback
Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC245A
SN74LVC245A
www.ti.com
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015
Typical Application (continued)
10.2.3 Application Curves
100
80
60
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
40
TA = 25°C, VCC = 3 V,
VIH = 3 V, VIL = 0 V,
All Outputs Switching
20
I OH – mA
I OL – mA
60
40
0
–20
–40
20
–60
0
–80
–20
–0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
–100
–1
–0.5 0.0
VOL – V
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VOH – V
Figure 5. Output Drive Current (IOL)
vs LOW-level Output Voltage (VOL)
Figure 6. Output Drive Current (IOH)
vs HIGH-level Output Voltage (VOH)
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. Multiple bypass capacitors may be paralleled to reject different frequencies of
noise. The bypass capacitor should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
Submit Documentation Feedback
Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC245A
11
SN74LVC245A
SCAS218X – JANUARY 1993 – REVISED JANUARY 2015
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser based versions of this data sheet, refer to the left hand navigation.
12
Submit Documentation Feedback
Copyright © 1993–2015, Texas Instruments Incorporated
Product Folder Links: SN74LVC245A
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC245ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC245A
SN74LVC245ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC245A
SN74LVC245ADWRG4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC245A
SN74LVC245AN
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC245AN
SN74LVC245ANE4
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74LVC245AN
SN74LVC245ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC245A
SN74LVC245APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWRG3
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
27-Dec-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC245APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC245A
SN74LVC245ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC245A
SN74LVC245AZQNR
NRND
BGA
MICROSTAR
JUNIOR
ZQN
20
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 125
LC245A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
OTHER QUALIFIED VERSIONS OF SN74LVC245A :
• Enhanced Product: SN74LVC245A-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LVC245ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LVC245ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC245ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC245ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LVC245APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC245APWRG3
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC245APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC245ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
SN74LVC245AZQNR
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC245ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LVC245ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LVC245ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LVC245ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LVC245APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC245APWRG3
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC245APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LVC245ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
SN74LVC245AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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