Texas Instruments | SN74LV273A Octal D-Type Flip-Flops With Clear (Rev. K) | Datasheet | Texas Instruments SN74LV273A Octal D-Type Flip-Flops With Clear (Rev. K) Datasheet

Texas Instruments SN74LV273A Octal D-Type Flip-Flops With Clear (Rev. K) Datasheet
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SN74LV273A
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
SN74LV273A Octal D-Type Flip-Flops With Clear
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 10.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Voltage Operation
on All Ports
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 3000-V Human-Body Model
– 200-V Machine Model
– 2000-V Charged-Device Model
Power Sub-station Controls
I/O Modules; Analog PLC/DCS Inputs
Human Machine Interfaces (HMI)
Flow Meters
Patient Monitoring
Test and Measurement Solutions
3 Description
The SN74LV273A device is an octal D-type flip-flop
designed for 2-V to 5.5-V VCC operation.
Device Information(1)
PART NUMBER
PACKAGE
SN74LV273A
BODY SIZE (NOM)
VQFN (20)
4.50 x 3.50 mm
SSOP (20)
7.50 x 5.30 mm
TSSOP (20)
6.50 x 4.40 mm
TVSOP (20)
5.00 x 4.40 mm
SOIC (20)
12.80 x 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1D
2D
3
4
3D
4D
7
5D
8
6D
13
7D
14
8D
17
18
11
CLK
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
2
5
6
1Q
2Q
3Q
9
4Q
12
5Q
15
6Q
16
7Q
19
8Q
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV273A
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
5
5
6
6
7
7
7
7
8
8
8
9
9
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, VCC = 2.5 V ± 0.2 V ..............
Timing Requirements, VCC = 3.3 V ± 0.3 V ..............
Timing Requirements, VCC = 5 V ± 0.5 V .................
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........
Switching Characteristics, VCC = 3.3 V ± 0.3 V ......
Switching Characteristics, VCC = 5 V ± 0.5 V .........
Noise Characteristics .............................................
Operating Characteristics........................................
7.14 Typical Characteristics ............................................ 9
8
9
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 14
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision J (April 2005) to Revision K
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6
2
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SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
6 Pin Configurations and Functions
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
20
1
20
2
19 8Q
3
18 8D
17 7D
4
5
16 7Q
6
15 6Q
7
14 6D
13 5D
8
12 5Q
9
10
11
CLK
1
CLR
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
SN74LV273A...RGY PACKAGE
(TOP VIEW)
GND
SN74LV273A...DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
CLR
I
Clear Pin
2
1Q
O
1Q Output
3
1D
I
1D Input
4
2D
I
2D Input
5
2Q
O
2Q Output
6
3Q
O
3Q Output
7
3D
I
3D Input
8
4D
I
4D Input
9
4Q
O
4Q Output
10
GND
—
Ground Pin
11
CLK
I
Clock Pin
12
5Q
O
5Q Output
13
5D
I
5D Input
14
6D
I
6D Input
15
6Q
O
6Q Output
16
7Q
O
7Q Output
17
7D
I
7D Input
18
8D
I
8D Input
19
8Q
O
8Q Output
20
VCC
—
Power Pin
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SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
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GQN or ZQN PACKAGE
(TOP VIEW)
1 2 3 4
A
B
C
D
E
Table 1. GQN or ZQN Pin Assignments
4
1
2
3
4
A
1Q
CLR
VCC
8Q
B
2D
7D
1D
8D
C
3Q
2Q
6Q
7Q
D
4D
5D
3D
6D
E
GND
4Q
CLK
5Q
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
VI
Input voltage range
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions() is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
3000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
2000
Machine Model (MM)
200
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
VCC = 2 V
VIL
UNIT
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
V
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 2 V
IOH
VCC = 2.3 V to 2.7 V
High-level output current
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Δt/Δv
50
VCC = 2.3 V to 2.7 V
Low-level output current
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
µA
2
VCC = 3 V to 3.6 V
Input transition rise or fall rate
mA
–12
VCC = 2 V
IOL
V
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LV273A
THERMAL METRIC (1)
DB
DGV
DW
NS
PW
RGY
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
98.7
118.1
81.8
79.4
104.7
37.1
RθJC(top)
Junction-to-case (top) thermal resistance
60.4
33.4
47.8
45.9
38.8
46.1
RθJB
Junction-to-board thermal resistance
56.9
59.6
49.4
46.9
55.7
14.9
ψJT
Junction-to-top characterization
parameter
21.6
1.1
20.1
19.1
2.9
1.3
ψJB
Junction-to-board characterization
parameter
53.5
58.9
49.0
46.5
55.1
15.0
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
9.8
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN
–40°C to 85°C
TYP
MAX
MIN
–40°C to 125°C
MAX
MIN
MAX
UNIT
IOH = –50 µA
2 V to
5.5 V
VCC –
0.1
VCC –
0.1
VCC –
0.1
IOH = –2 mA
2.3 V
2
2
2
IOH = –6 mA
3V
2.48
2.48
2.48
IOH = –12 mA
4.5 V
3.8
3.8
3.8
IOL = –50 µA
2 V to
5.5 V
IOL = –2 mA
2.3 V
0.4
0.4
0.4
IOL = –6 mA
3V
0.44
0.44
0.44
IOL = –12 mA
4.5 V
0.55
0.55
0.55
II
VI = 5.5 V or GND
0 to
5.5 V
±1
±1
±1
µA
ICC
VI = VCC or GND,
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
5
5
5
µA
Ci
VI = VCC or GND
VOH
VOL
IO = 0
0.1
0V
3.3 V
V
0.1
0.1
2
V
pF
7.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
CLR low
CLK high or low
Data
CLR inactive
MAX
–40°C to 85°C
MIN
MAX
–40°C to 125°C
MIN
6.5
7
7.5
7
8.5
9
8.5
10.5
12
4
4
4.5
0.5
1
2.5
MAX
UNIT
ns
ns
ns
7.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
MAX
–40°C to 85°C
MIN
MAX
–40°C to 125°C
MIN
CLR low
5
6
6.5
CLK high or low
5
6.5
7
Data
5.5
6.5
8
CLR inactive
2.5
2.5
3
1
1
2.5
MAX
UNIT
ns
ns
ns
7.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time, data before CLK↑
th
Hold time, data after CLK↑
MAX
–40°C to 85°C
MIN
MAX
–40°C to 125°C
MIN
CLR low
5
5
5.5
CLK high or low
5
5
5.5
4.5
4.5
6
2
2
2.5
1
1
2
Data
CLR inactive
MAX
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UNIT
ns
ns
ns
7
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SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
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7.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
TA = 25°C
–40°C to 85°C
MIN
TYP
CL = 15 pF
55 (1)
95 (1)
45
45
CL = 50 pF
45
75
40
40
CL = 15 pF
MIN
MAX
MIN
MAX
UNIT
MHz
10.4 (1)
18.3 (1)
1
20.5
1
22.5
ns
(1)
(1)
1
21
1
23
ns
12.9
22.1
1
25
1
27
ns
13.1
22.8
1
25.5
1
27.5
ns
2
ns
10.3
CL = 50 pF
MAX
19
tsk(o)
(1)
–40°C to 125°C
LOAD
CAPACITANCE
2
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
TA = 25°C
–40°C to 85°C
MIN
TYP
CL = 15 pF
75 (1)
140 (1)
65
65
CL = 50 pF
50
110
45
45
CL = 15 pF
MIN
MAX
MIN
MAX
UNIT
MHz
7.1 (1)
13.6 (1)
1
16
1
17.5
ns
(1)
13.6 (1)
1
16
1
17.5
ns
9.1
17.1
1
19.5
1
21
ns
8.7
17.1
1
19.5
1
21
ns
1.5
ns
6.9
CL = 50 pF
MAX
tsk(o)
(1)
–40°C to 125°C
LOAD
CAPACITANCE
1.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
CLK
Q
tPHL
CLR
Q
tpd
CLK
Q
tPHL
CLR
Q
LOAD
CAPACITANCE
TA = 25°C
–40°C to 85°C
TYP
CL = 15 pF
120 (1)
20 (1)5
100
100
CL = 50 pF
80
160
70
70
CL = 15 pF
CL = 50 pF
MAX
4.8 (1)
9 (1)
1
(1)
(1)
6.2
11
6
10.5
4.7
8.5
tsk(o)
(1)
8
MIN
1
MAX
–40°C to 125°C
MIN
MIN
MAX
UNIT
MHz
10.5
1
11.5
ns
1
10
1
11
ns
1
12.5
1
14
ns
1
12
1
13.5
ns
1
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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7.12 Noise Characteristics (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV273A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
VCC
TYP
UNIT
3.3 V
15.9
5V
17.1
Characteristics for surface-mount packages only.
7.13 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
f = 10 MHz
pF
7.14 Typical Characteristics
12
8
7
10
6
TPD (ns)
TPD (ns)
8
6
5
4
3
4
2
2
1
TPD in ns
TPD in ns
0
0
1
2
3
VCC
4
5
6
0
-100
D001
Figure 1. TPD vs VCC at 25°C
-50
0
50
Temperature (qC)
100
150
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D002
Figure 2. TPD vs Temperature
9
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8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
VCC
50% VCC
50% VCC
Input
0V
th
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPLH
In-Phase
Output
50% VCC
tPHL
Out-of-Phase
Output
0V
tPHL
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH – 0.3 V
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
F.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
Figure 3. Load Circuit and Voltage Waveforms
10
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN74LV273A
SN74LV273A
www.ti.com
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
9 Detailed Description
9.1 Overview
The SN74LV273A device is an octal D-type flip-flop designed for 2-V to 5.5-V VCC operation.
This device is a positive-edge-triggered flip-flop with direct clear (CLR) input. Information at the data (D) inputs
meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock
pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect
at the output.
The SN74LV273A device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow through the devices when they are powered down.
9.2 Functional Block Diagram
1D
2D
3
4
3D
4D
7
5D
8
6D
13
7D
14
8D
17
18
11
CLK
1D
1D
C1
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
C1
R
R
1
CLR
2
5
6
1Q
2Q
3Q
9
4Q
12
15
5Q
6Q
16
7Q
19
8Q
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
Slow edges reduce noise
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 2. Function Table
(Each Flip-Flop)
INPUTS
CLR
CLK
D
OUTPUT
Q
L
X
X
L
H
↑
H
H
H
↑
L
L
H
L
X
Q0
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Product Folder Links: SN74LV273A
11
SN74LV273A
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
www.ti.com
10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV273A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where the data needs to be retained or latched. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The inputs are tolerant to 5.5 V at any valid VCC. This feature makes it Ideal for
translating down to the VCC level. Figure 6 shows the reduction in ringing compared to higher drive parts such as
AC.
10.2 Typical Application
Regulated 5 V
CLR
VCC
CLK
1D
1Q
µC
System Logic
LEDs
µC or
System Logic
8D
8Q
GND
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions (1) table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions (1) table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC
(1)
12
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN74LV273A
SN74LV273A
www.ti.com
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
Typical Application (continued)
10.2.3 Application Curves
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions (1) table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN74LV273A
13
SN74LV273A
SCLS399K – APRIL 1998 – REVISED DECEMBER 2014
www.ti.com
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 7. Layout Diagram
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74LV273A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN74LV273A
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV273ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADBRE4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADWG4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV273A
SN74LV273APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWE4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV273A
SN74LV273ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV273A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
27-Dec-2019
Status
(1)
SN74LV273AZQNR
NRND
Package Type Package Pins Package
Drawing
Qty
BGA
MICROSTAR
JUNIOR
ZQN
20
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
LV273A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LV273ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LV273ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV273ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV273ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV273APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV273APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LV273APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LV273ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
SN74LV273AZQNR
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV273ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LV273ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LV273ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV273ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV273APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV273APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LV273APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LV273ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
SN74LV273AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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