Texas Instruments | SN74AHCT367 Hex Buffer and Line Driver with 3-State Output (Rev. H) | Datasheet | Texas Instruments SN74AHCT367 Hex Buffer and Line Driver with 3-State Output (Rev. H) Datasheet

Texas Instruments SN74AHCT367 Hex Buffer and Line Driver with 3-State Output (Rev. H) Datasheet
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SN74AHCT367
SCLS418H – JUNE 1998 – REVISED DECEMBER 2014
SN74AHCT367 Hex Buffer and Line Driver with 3-State Output
1 Features
3 Description
•
•
•
The SN74AHCT367 device is designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
1
•
Inputs are TTL-Voltage Compatible
True Outputs
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 2000-V Charged-Device Model
Device Information(1)
PART NUMBER
SN74AHCT367
2 Applications
•
•
•
•
•
•
Telecom Infrastructure
TVs
Set Top Boxes
Network Switches
Wireless Infrastructure
Electronic Points of Sale
PACKAGE
BODY SIZE (NOM)
PDIP (16)
19.30 mm x 6.35
mm
SSOP (16)
6.50 mm x 5.30 mm
TSSOP (16)
5.00 mm x 4.40 mm
SOP (16)
10.20 mm x 5.30
mm
SOIC (16)
9.00 mm x 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
2OE
1Y1
1A1
To Three Other Channels
2Y1
2A1
To One Other Channel
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHCT367
SCLS418H – JUNE 1998 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
4
4
4
5
5
5
6
6
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 7
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
10.2 Typical Application ................................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 11
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
11
11
11
11
14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision G (July 2003) to Revision H
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................................... 4
2
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6 Pin Configuration and Functions
SN74AHCT367 . . . D, DB, DGV, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
2OE
2A2
2Y2
2A1
2Y1
1A4
1Y4
Pin Functions
PIN
NO.
NAME
1
1OE
2
3
TYPE
DESCRIPTION
I
Output Enable 1
1A1
I
1A1 Input
1Y1
O
1Y1 Output
4
1A2
I
1A2 Input
5
1Y2
O
1Y2 Output
6
1A3
I
1A3 Input
7
1Y3
O
1Y3 Output
8
GND
—
Ground Pin
9
1Y4
O
1Y4 Output
10
1A4
I
1A4 Input
11
2Y1
O
2Y1 Output
12
2A1
I
2A1 Input
13
2Y2
O
2Y2 Output
14
2A2
I
2A2 Input
15
2OE
I
Output Enable 2
16
VCC
—
Power Pin
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SN74AHCT367
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
150
°C
Continuous current through VCC or GND
Tstg
(1)
(2)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
2000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74AHCT367
MIN
MAX
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output current
–8
IOL
Low-level output current
8
mA
Δt/Δv
Input transition rise or fall rate
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
4
2
–40
V
V
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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7.4 Thermal Information
SN74AHCT367
THERMAL METRIC (1)
D
DB
DGV
PW
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
85.1
103.9
124.5
111.5
RθJC(top)
Junction-to-case (top) thermal resistance
46.5
54.3
49.8
46.5
RθJB
Junction-to-board thermal resistance
42.6
54.6
56.2
56.6
ψJT
Junction-to-top characterization parameter
13.2
14.3
5.8
5.8
ψJB
Junction-to-board characterization parameter
42.4
54.0
55.7
56.0
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
IOH = –50 µA
TA = 25°C
VCC
4.5 V
IOH = –8 mA
IOL = 50 µA
MIN
TYP
4.4
4.5
–40°C to 85°C
MAX
3.94
4.5 V
IOH = 8 mA
MIN
–40°C to 125°C
MAX
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.1
0.36
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1 (1)
±1 (1)
±1
µA
IOZ
VO = VCC or GND
VI (OE) = VIL or VIH
5.5 V
±0.25
±2.5
±2.5
µA
ICC
VI = VCC or GND,
5.5 V
4
40
40
µA
5.5 V
1.35
1.5
1.5
mA
10
10
10
pF
ΔICC
(1)
(2)
TEST CONDITIONS
(2)
IO = 0
One input at 3.4 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
5V
2.5
CO
VO = VCC or GND
5V
5
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
7.6 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
A
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
TA = 25°C
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
2.5 (1)
4.8 (1)
1
6.5
1
8.5
(1)
4.8 (1)
1
6.5
1
8.5
3.5 (1)
8 (1)
1
9.5
1
9
(1)
7 (1)
1
8.5 (1)
1
8
3.1 (1)
8 (1)
1
9.5
1
9
(1)
7 (1)
1
8.5
1
8
3.5
5.8
1
7.5
1
9.5
3.3
5.8
1
7.5
1
9.5
4.5
9
1
10.5
1
10
3.7
8
1
9.5
1
9
4.1
9
1
10.5
1
10
3.6
8
1
9.5
1
9
2.5
2.8
2.8
UNIT
ns
ns
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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7.7 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHCT367
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.4
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2
V
0.8
V
TYP
UNIT
Characteristics are for surface-mount packages only.
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
22
pF
7.9 Typical Characteristics
6
5
TPD (ns)
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 1. TPD vs Temperature, 50 pF Load
6
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8 Parameter Measurement Information
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74AHCT367 device is designed specifically to improve both the performance and density of
3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. This device is
organized as a dual 4-line and 2-line buffer/driver with active-low output-enable (1OE and 2OE) inputs. When OE
is low, the device passes noninverted data from the A inputs to the Y outputs. When OE is high, the outputs are
in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
1OE
2OE
1Y1
1A1
2Y1
2A1
To Three Other Channels
To One Other Channel
Figure 3. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
•
•
VCC is optimized at 5 V
Allows up voltage translation from 3.3 V to 5 V
– Inputs Accept VIH levels of 2 V
Slow edge rates minimize output ringing
Inputs are TTL-Voltage compatible
9.4 Device Functional Modes
Table 1. Function Table
(Each Buffer/Driver)
INPUTS
8
OE
A
OUTPUT
Y
H
X
Z
L
H
H
L
L
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74AHCT367 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V VIL and 2-V VIH.
This feature makes it Ideal for translating up from 3.3 V to 5 V. Figure 5 shows this type of translation.
10.2 Typical Application
Regulated 3.3 V
5V
OE
A1
VCC
Y1
µC or
System Logic
A4
Y4
µC
System Logic
LEDs
GND
Figure 4. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
Voltage
10.2.3 Application Curves
Time
Figure 5. Typical Application Curve
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
10
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 6 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN74AHCT367
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHCT367D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT367
SN74AHCT367DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB367
SN74AHCT367DGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB367
SN74AHCT367DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT367
SN74AHCT367PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB367
SN74AHCT367PWG4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB367
SN74AHCT367PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB367
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AHCT367DGVR
Package Package Pins
Type Drawing
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AHCT367DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AHCT367PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHCT367DGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74AHCT367DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AHCT367PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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