Texas Instruments | SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset (Rev. M) | Datasheet | Texas Instruments SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset (Rev. M) Datasheet

Texas Instruments SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset (Rev. M) Datasheet
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SN74LVC112A
SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014
SN74LVC112A Dual Negative-Edge-Triggered J-K Flip-Flop
With Clear And Preset
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
1
•
•
•
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.8 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 3000-V Human-Body Model
– 200-V Machine Model
– 1500-V Charged-Device Model
Servers
PCs
Notebooks
Network switches
Toys
I/O Expanders
Electronic Points of Sale
3 Description
This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-V to 3.6-V VCC operation.
Device Information(1)
PART NUMBER
SN74LVC112A
PACKAGE
BODY SIZE (NOM)
SSOP (16)
6.50 mm x 5.30 mm
TSSOP (16)
5.00 mm x 4.40 mm
TVSOP (16)
3.60 mm x 4.40 mm
SOP (16)
10.20 mm x 5.30
mm
SOIC (16)
9.00 mm x 3.90 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
Q
PRE
K
Q
CLR
J
CLK
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC112A
SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
7
7
7
7
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Timing Requirements, –40°C to 85°C.......................
Timing Requirements, –40°C to 125°C.....................
Switching Characteristics, –40°C to 85°C.................
Switching Characteristics, –40°C to 125°C...............
Operating Characteristics........................................
Typical Characteristics ............................................
8
9
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision L (August 2004) to Revision M
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................... 5
•
Added –40°C to 125°C temperature range to Electrical Specifications table. ...................................................................... 6
•
Added Timing Requirements table for –40°C to 125°C temperature range. .......................................................................... 6
•
Added Switching Characteristics table for –40°C to 125°C temperature range. ................................................................... 7
2
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6 Pin Configuration and Functions
D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
VCC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
Pin Functions
PIN
TYPE
DESCRIPTION
NO.
NAME
1
1CLK
I
1 Clock
2
1K
I
1K Input
3
1J
I
1J Input
4
1PRE
I
1 Preset
5
1Q
O
1Q Output. Pull low to set 1Q high and 1Q low upon power-up.
6
1Q
O
1Q Output
7
2Q
O
2Q Output
8
GND
—
Ground Pin
9
2Q
O
2Q Output
10
2PRE
I
2 Preset
11
2J
I
2J Input. Pull low to set 2Q high and 2Q low upon power-up.
12
2K
I
2K Input
13
2CLK
I
2 Clock
14
2CLR
I
2 Clear
15
1CLR
I
1 Clear. Pull low to set 2Q low and 2Q high upon power-up.
16
VCC
—
Power Pin. Pull low to set 1Q low and 1Q high upon power-up.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range
(2)
MIN
MAX
–0.5
6.5
UNIT
V
–0.5
6.5
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through VCC or GND
Tstg
(1)
(2)
(3)
Storage temperature range
V
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
3000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage
VIH
High-level input voltage
Operating
Data retention only
MIN
MAX
1.65
3.6
UNIT
V
1.5
VCC = 1.65 V to 1.95 V
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
V
0.35 × VCC
VIL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 2.7 V to 3.6 V
0.8
VCC = 1.65 V
IOH
High-level output current
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
mA
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LVC112A
THERMAL METRIC (1)
D
DB
DGV
NS
PW
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
90.6
107.1
129.0
90.7
122.6
RθJC(to
Junction-to-case (top) thermal resistance
50.9
59.6
52.1
48.3
51.4
RθJB
Junction-to-board thermal resistance
44.8
54.4
62.0
49.4
64.4
ψJT
Junction-to-top characterization parameter
14.7
20.5
6.5
14.6
6.7
ψJB
Junction-to-board characterization parameter
44.5
53.8
61.3
49.1
63.8
p)
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
VCC
II
Ci
(1)
MAX
MIN
–40°C to 125°C
MAX
MIN
VCC – 0.2
VCC – 0.2
VCC – 0.2
IOH = –4 mA
1.65 V
1.2
1.2
1.2
IOH = –8 mA
2.3 V
1.7
1.7
1.7
2.7 V
2.2
2.2
2.2
MAX
UNIT
V
3V
2.4
2.4
2.4
IOH = –24 mA
3V
2.2
2.2
2.2
IOL = 100 μA
1.65 V
to
3.6 V
0.2
0.2
0.2
IOL = 4 mA
1.65 V
0.45
0.45
0.45
IOL = 8 mA
2.3 V
0.7
0.7
0.7
IOL = 12 mA
2.7 V
0.4
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
0.55
3.6 V
±5
±5
±5
μA
3.6 V
10
10
10
μA
One input at VCC – 0.6 V,
Other inputs at VCC or GND
2.7 V
to
3.6 V
500
500
500
μA
VI = VCC or GND
3.3 V
VI = VCC or
GND,
ΔICC
–40°C to 85°C
1.65 V
to
3.6 V
VI = 5.5 V or GND
ICC
MIN TYP
(1)
IOH = –100 μA
IOH = –12 mA
VOL
TA = 25°C
IO = 0
4.5
V
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
7.6 Timing Requirements, –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time
th
Hold time, data after CLK↓
MAX
VCC = 2.5 V
± 0.2 V
MIN
120
Data before CLK↓
PRE or CLR inactive
MAX
VCC = 2.7 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
4.2
3.3
3.3
3.3
5.8
3.2
3.1
2.3
5
2.8
2.4
1.1
6.2
4.4
2.5
0.7
UNIT
MAX
MHz
ns
ns
ns
7.7 Timing Requirements, –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V
MIN
fclock
Clock frequency
tw
Pulse duration, CLK high or low
tsu
Setup time
th
Hold time, data after CLK↓
6
MAX
VCC = 2.5 V
± 0.2 V
MIN
120
MAX
VCC = 2.7 V
MIN
150
MAX
VCC = 3.3 V
± 0.3 V
MIN
150
150
4.1
3.3
3.3
3.3
Data before CLK↓
6
3.2
3.1
2.3
PRE or CLR inactive
5
2.8
2.4
1.1
6.2
4.7
2.5
0.7
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UNIT
MAX
MHz
ns
ns
ns
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7.8 Switching Characteristics, –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
PARAMETER
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
VCC = 2.5 V
± 0.2 V
MAX
MIN
150
CLR or PRE
CLK
VCC = 2.7 V
MAX
150
Q or Q
MIN
VCC = 3.3 V ± 0.3 V
MAX
MIN
150
TYP
MAX
150
UNIT
MHz
5.9
4.1
5.5
1
3.4
4.8
5.6
4
7.1
1
3.5
5.9
ns
7.9 Switching Characteristics, –40°C to 125°C
over operating free-air temperature range (unless otherwise noted)
FROM
(INPUT)
PARAMETER
VCC = 1.8 V
± 0.15 V
TO
(OUTPUT)
MIN
fmax
tpd
MAX
120
CLR or PRE
CLK
VCC = 2.5 V
± 0.2 V
MIN
VCC = 2.7 V
MAX
150
Q or Q
MIN
VCC = 3.3 V ± 0.3 V
MAX
MIN
150
TYP
MAX
150
UNIT
MHz
6.2
4
6
1
3.4
5.3
6.2
4.1
7.6
1
3.5
6.4
ns
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
(1)
TEST CONDITIONS
Power dissipation capacitance
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
See (1)
See (1)
24
f = 10 MHz
UNIT
pF
This information was not available at the time of publication.
7.11 Typical Characteristics
4.5
6
4
5
3.5
4
TPD (ns)
TPD (ns)
3
2.5
2
1.5
3
2
1
1
0.5
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 1. TPD vs Temperature
1
2
VCC
3
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D002
Figure 2. TPD vs VCC at 25°C
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and t PHZ are the same as t dis.
F. t PZL and t PZH are the same as t en.
G. t PLH and t PHL are the same as t pd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
This dual negative-edge-triggered J-K flip-flop is designed for 1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time
requirements is transferred to the outputs on the negative-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the J and K inputs can be changed without affecting the levels at the outputs. The SN74LVC112A can
perform as a toggle flip-flop by tying J and K high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
9.2 Functional Block Diagram
Q
Q
CLR
PRE
K
J
CLK
Figure 4. Logic Diagram, Each Flip-Flop (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
(1)
OUTPUTS
PRE
CLR
CLK
J
K
Q
Q
L
H
X
X
X
H
L
H
L
X
X
X
L
H
L
L
X
X
X
H (1)
H (1)
H
H
↓
L
L
Q0
Q0
H
H
↓
H
L
H
L
H
H
↓
L
H
L
H
H
H
↓
H
H
H
H
H
X
X
Toggle
Q0
Q0
The output levels in this configuration may not meet the minimum
levels for VOH. Furthermore, this configuration is nonstable; that is, it
does not persist when either PRE or CLR returns to its inactive
(high) level.
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10 Application and Implementation
10.1 Application Information
SN74LVC112A is a high-drive CMOS device that can be used for a multitude of bus interface type applications
where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V, making it Ideal for
driving multiple outputs and good for high-speed applications up to 150 MHz. The inputs are 5.5-V tolerant
allowing it to translate down to VCC.
10.2 Typical Application
Regulated 3.3 V
PRE
VCC
CLR
CLK
J
Q
µC
System Logic
LEDs
µC or
System Logic
K
Q
GND
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curves
2.5
2.25
2
1.75
VCC
1.5
1.25
1
0.75
0.5
VCC 1.8 V
VCC 2.5 V
VCC 3.3 V
0.25
0
0
5
10
15
20
25
30
Frequency (MHz)
35
40
45
50
D003
Figure 6. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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SN74LVC112A
SCAS289M – JANUARY 1993 – REVISED DECEMBER 2014
www.ti.com
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver..
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
Submit Documentation Feedback
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVC112A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC112AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC112A
SN74LVC112ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
SN74LVC112ADGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
SN74LVC112ADGVRG4
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
SN74LVC112ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC112A
SN74LVC112ADT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC112A
SN74LVC112ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC112A
SN74LVC112APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
SN74LVC112APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
SN74LVC112APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC112A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74LVC112ADGVR
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
8.0
12.0
Q1
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
W
Pin1
(mm) Quadrant
SN74LVC112ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LVC112ANSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LVC112APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC112APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC112ADGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74LVC112ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LVC112ANSR
SO
NS
16
2000
367.0
367.0
38.0
SN74LVC112APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LVC112APWT
TSSOP
PW
16
250
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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