Texas Instruments | SN74AHC1G86 Single 2-Input Exclusive-OR Gate (Rev. N) | Datasheet | Texas Instruments SN74AHC1G86 Single 2-Input Exclusive-OR Gate (Rev. N) Datasheet

Texas Instruments SN74AHC1G86 Single 2-Input Exclusive-OR Gate (Rev. N) Datasheet
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SN74AHC1G86
SCLS323N – MARCH 1996 – REVISED DECEMBER 2014
SN74AHC1G86 Single 2-Input Exclusive-OR Gate
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
•
1
•
•
Operating Range of 2 V to 5.5 V
Max tpd of 8 ns at 5 V
Low Power Consumption, 10-µA Max ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the
Circuit Tolerant for Slower Input Rise and Fall
Time
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Cameras
Programmable Logic Controllers
Telecom Infrastructure
Wireless Headsets
Motor Drives and Controls
TVs
Set-top-boxes
Audio
3 Description
The SN74AHC1G86 is a single 2-input exclusive-OR
gate. The device performs the Boolean function Y = A
× B or Y = AB + AB in positive logic.
Device Information(1)
PART NUMBER
SN74AHC1G86
PACKAGE
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm x 1.60 mm
SC-70 (5)
2.00 mm x 1.30 mm
SOT-553 (5)
1.65 mm x 1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86 gate in positive logic; negation may be shown at any twoports.
LOGIC-IDENTITY ELEMENT
=
The output is active (low) if
all inputs stand at the same
logic level (that is, A = B).
EVEN-PARITY ELEMENT
2k
The output is active (low) if
an even number of inputs
(that is, 0 or 2) are active.
ODD-PARITY ELEMENT
2k + 1
The output is active (high) if
an odd number of inputs
(that is, only 1 of the 2) are
active.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AHC1G86
SCLS323N – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
8
1
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 4
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........ 5
Switching Characteristics, VCC = 5 V ± 0.5 V............ 5
Operating Characteristics.......................................... 6
Typical Characteristics .............................................. 6
Parameter Measurement Information .................. 7
9
Detailed Description .............................................. 8
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
8
8
8
8
10 Application and Implementation.......................... 9
10.1 Application Information............................................ 9
10.2 Typical Application ................................................. 9
11 Power Supply Recommendations ..................... 10
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 11
13.1 Trademarks ........................................................... 11
13.2 Electrostatic Discharge Caution ............................ 11
13.3 Glossary ................................................................ 11
14 Mechanical, Packaging, and Orderable
Information ........................................................... 11
5 Revision History
Changes from Revision M (June 2005) to Revision N
Page
•
Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. .......................................... 4
2
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6 Pin Configuration and Functions
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
A
1
B
2
GND
3
A
1
B
2
GND
3
5
V CC
5
4
DRL PACKAGE
(TOP VIEW)
V CC
Y
A
1
B
2
GND
3
5
V CC
4
Y
Y
4
See mechanical drawings for dimensions.
Pin Functions
PIN
NO.
NAME
TYPE
DESCRIPTION
1
A
I
Input A
2
B
I
Input B
3
GND
—
Ground Pin
4
Y
O
Output Y
5
VCC
—
Power Pin
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SCLS323N – MARCH 1996 – REVISED DECEMBER 2014
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
Continuous channel current through VCC or GND
Tstg
(1)
(2)
Storage temperature range
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1)
2000
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
VIH
Supply voltage
High-level input voltage
MIN
MAX
2
5.5
VCC = 2 V
1.5
VCC = 3 V
2.1
VCC = 5.5 V
UNIT
V
V
3.85
VCC = 2 V
0.5
VCC = 3 V
0.9
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 5.5 V
1.65
VCC = 2 V
IOH
IOL
High-level output current
Low-level output current
∆t/∆v Input transition rise or fall rate
TA
(1)
4
VCC = 3.3 V ± 0.3 V
–4
VCC = 5 V ± 0.5 V
–8
VCC = 2 V
50
VCC = 3.3 V ± 0.3 V
4
VCC = 5 V ± 0.5 V
8
VCC = 3.3 V ± 0.3 V
100
VCC = 5 V ± 0.5 V
Operating free-air temperature
V
20
–40
125
V
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
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7.4 Thermal Information
SN74AHC1G86
THERMAL METRIC (1)
DBV
DCK
DRL
UNIT
5 PINS
RθJA
Junction-to-ambient thermal resistance
231.3
287.6
328.7
RθJC(top)
Junction-to-case (top) thermal resistance
119.9
97.7
105.1
RθJB
Junction-to-board thermal resistance
60.6
65.
150.3
ψJT
Junction-to-top characterization parameter
17.8
2.0
6.9
ψJB
Junction-to-board characterization parameter
60.1
64.2
148.4
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = 25°C
VCC
IOH = –50 µA
VOH
–40°C to 85°C
MAX
MIN
–40°C to 125°C
MIN
TYP
MAX
MIN
2V
1.9
2
1.9
1.9
3V
2.9
3
2.9
2.9
4.5
4.5 V
4.4
4.4
4.4
IOH = –4 mA
3V
2.58
2.48
2.48
IOH = –8 mA
4.5 V
3.94
3.8
3.8
MAX
UNIT
V
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
3V
0.36
0.44
0.44
IOL = 8 mA
4.5 V
0.36
0.44
0.44
II
VI = 5.5 V or GND
0 V to
5.5 V
±0.1
±1
±1
µA
ICC
VI = VCC or GND,
1
10
10
µA
Ci
VI = VCC or GND
10
10
10
pF
IOL = 50 µA
VOL
IOL = 4 mA
IO = 0
5.5 V
5V
4
V
7.6 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
LOAD
(OUTPUT) CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
7
11
1
13
1
14
7
11
1
13
1
14
9.5
14.5
1
16.5
1
17.5
9.5
14.5
1
16.5
1
17.5
UNIT
ns
ns
7.7 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
FROM
(INPUT)
TO
LOAD
(OUTPUT) CAPACITANCE
A or B
Y
CL = 15 pF
A or B
Y
CL = 50 pF
TA = 25°C
MIN
–40°C to 85°C
–40°C to 125°C
TYP
MAX
MIN
MAX
MIN
MAX
4.8
6.8
1
8
1
8.6
4.8
6.8
1
8
1
8.6
6.3
8.8
1
10
1
11
6.3
8.8
1
10
1
11
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UNIT
ns
ns
5
SN74AHC1G86
SCLS323N – MARCH 1996 – REVISED DECEMBER 2014
www.ti.com
7.8 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
TYP
f = 1 MHz
UNIT
18
pF
7.9 Typical Characteristics
6
8
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 1. TPD vs Temperature
6
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2
3
VCC
4
5
6
D002
Figure 2. TPD vs VCC at 25°C
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8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
50% VCC
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
Figure 3. Load Circuit and Voltage Waveforms
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SN74AHC1G86
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9 Detailed Description
9.1 Overview
The SN74AHC1G86 is a single 2-input exclusive-OR gate. The device performs the Boolean function Y = A
× B or Y = AB + AB in positive logic.
A common application is as a true or complementary element. If one of the inputs is low, the other input is
reproduced in true form at the output. If one of the inputs is high, the signal on the other input is reproduced
inverted at the output.
9.2 Functional Block Diagram
An exclusive-OR gate has many applications, some of which can be represented better by alternative
logic symbols.
EXCLUSIVE OR
=1
These are five equivalent exclusive-OR symbols valid for an SN74AHC1G86 gate in positive logic; negation may be shown at any twoports.
LOGIC-IDENTITY ELEMENT
EVEN-PARITY ELEMENT
=
2k
2k + 1
The output is active (low) if
an even number of inputs
(that is, 0 or 2) are active.
The output is active (low) if
all inputs stand at the same
logic level (that is, A = B).
ODD-PARITY ELEMENT
The output is active (high) if
an odd number of inputs
(that is, only 1 of the 2) are
active.
Figure 4. Exclusive-OR Logic
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 2 V to 5.5 V
Allows down-voltage translation
– Inputs accept voltages to 5.5 V
The low drive and slow edge rates will minimize overshoot and undershoot on the outputs
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
8
A
B
OUTPUT
Y
L
L
L
L
H
H
H
L
H
H
H
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
SN74AHCT1G125 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making it Ideal for down translation.
10.2 Typical Application
5-V accessory
3.3-V or 5-V regulated
0.1 µF
5-V
System
Logic
µC or
System
Logic
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– For rise time and fall time specifications, see Δt/ΔV in the Recommended Operating Conditions table.
– For specified High and low levels, see VIH and VIL in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
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Typical Application (continued)
10.2.3 Application Curves
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and
1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
10
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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11
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC1G86DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(A863, A86G, A86J,
A86S)
SN74AHC1G86DBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
A86G
SN74AHC1G86DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
A86G
SN74AHC1G86DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(A863, A86G, A86J,
A86S)
SN74AHC1G86DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(AH3, AHG, AHJ, AH
S)
SN74AHC1G86DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AH3
SN74AHC1G86DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AH3
SN74AHC1G86DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(AH3, AHG, AHJ, AH
S)
SN74AHC1G86DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AH3
SN74AHC1G86DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
AHS
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
4-Apr-2019
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AHC1G86 :
• Automotive: SN74AHC1G86-Q1
• Enhanced Product: SN74AHC1G86-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
178.0
9.2
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
178.0
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
178.0
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
SN74AHC1G86DBVRG4 SOT-23
DBV
5
W
Pin1
(mm) Quadrant
3.3
3.23
1.55
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
3000
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHC1G86DBVT
SOT-23
DBV
5
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74AHC1G86DBVT
SOT-23
DBV
5
250
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
SN74AHC1G86DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHC1G86DBVT
SOT-23
DBV
5
250
180.0
8.4
3.23
3.17
1.37
4.0
8.0
Q3
SN74AHC1G86DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G86DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G86DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G86DCKRG4
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G86DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G86DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74AHC1G86DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G86DCKTG4
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AHC1G86DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Jan-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G86DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AHC1G86DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AHC1G86DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G86DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G86DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AHC1G86DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AHC1G86DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G86DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G86DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G86DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AHC1G86DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G86DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G86DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G86DCKTG4
SC70
DCK
5
250
180.0
180.0
18.0
SN74AHC1G86DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
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AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Copyright © 2019, Texas Instruments Incorporated
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