Texas Instruments | SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs (Rev. G) | Datasheet | Texas Instruments SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs (Rev. G) Datasheet

Texas Instruments SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation and 3-State Outputs (Rev. G) Datasheet
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SN74AVC4T245
SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
SN74AVC4T245 Dual-Bit Bus Transceiver with Configurable Voltage Translation
and 3-State Outputs
1 Features
3 Description
•
This 4-bit noninverting bus transceiver uses two
separate configurable power-supply rails. The A port
is designed to track VCCA. VCCA accepts any supply
voltage from 1.2 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from
1.2 V to 3.6 V. The SN74AVC4T245 is optimized to
operate with VCCA/VCCB set at 1.4 V to 3.6 V. It is
operational with VCCA/VCCB as low as 1.2 V. This
allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V,
2.5-V, and 3.3-V voltage nodes.
Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
Fully Configurable Dual-Rail Design Allows Each
Port to Operate Over the Full 1.2-V to 3.6-V
Power-Supply Range
I/Os Are 4.6-V Tolerant
Ioff Supports Partial Power-Down-Mode Operation
Maximum Data Rates
– 380 Mbps (1.8-V to 3.3-V Translation)
– 200 Mbps (< 1.8-V to 3.3-V Translation)
– 200 Mbps (Translate to 2.5 V or 1.8 V)
– 150 Mbps (Translate to 1.5 V)
– 100 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A)
– 150-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1
•
•
•
•
•
•
The SN74AVC4T245 device is designed so that the
control pins (1DIR, 2DIR, 1OE, and 2OE) are
supplied by VCCA.
2 Applications
•
•
•
•
The SN74AVC4T245 device is designed for
asynchronous communication between two data
buses. The logic levels of the direction-control (DIR)
input and the output-enable (OE) input activate either
the B-port outputs or the A-port outputs or place both
output ports into the high-impedance mode. The
device transmits data from the A bus to the B bus
when the B-port outputs are activated, and from the B
bus to the A bus when the A-port outputs are
activated. The input circuitry on both A and B ports is
always active and must have a logic HIGH or LOW
level applied to prevent excess ICC and ICCZ.
Personal Electronics
Industrial
Enterprise
Telecom
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
The VCC isolation feature ensures that if either VCC
input is at GND, then both ports are in the highimpedance state.
Logic Diagram (Positive Logic)
for 1/2 of SN74AVC4T245
DIR
OE
A1
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
Device Information(1)
B1
PART NUMBER
A2
SN74AVC4T245
B2
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm x 3.91 mm
TVSOP (16)
3.60 mm x 4.40 mm
TSSOP (16)
5.00 mm x 4.40 mm
VQFN (16)
4.00 mm x 3.50 mm
UQFN (16)
2.60 mm x 1.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AVC4T245
SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
7
1
1
1
2
3
4
Absolute Maximum Ratings ..................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics .......................................... 6
Operating Characteristics.......................................... 7
Switching Characteristics: VCCA = 1.2 V ................... 7
Switching Characteristics: VCCA = 1.5 V ± 0.1 V....... 8
Switching Characteristics: VCCA = 1.8 V ± 0.15 V..... 8
Switching Characteristics: VCCA = 2.5 V ± 0.2 V..... 9
Switching Characteristics: VCCA = 3.3 V ± 0.3 V..... 9
Typical Characteristics .......................................... 10
Parameter Measurement Information ................ 11
8
Detailed Description ............................................ 12
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
12
12
13
13
Application and Implementation ........................ 14
9.1 Application Information............................................ 14
9.2 Typical Application ................................................. 14
10 Power Supply Recommendations ..................... 16
11 Layout................................................................... 16
11.1 Layout Guidelines ................................................. 16
11.2 Layout Example .................................................... 16
12 Device and Documentation Support ................. 17
12.1 Trademarks ........................................................... 17
12.2 Electrostatic Discharge Caution ............................ 17
12.3 Glossary ................................................................ 17
13 Mechanical, Packaging, and Orderable
Information ........................................................... 17
13.1 Package Materials Information ............................. 18
4 Revision History
Changes from Revision F (October 2014) to Revision G
Page
•
Changed Pin Functions table. ............................................................................................................................................... 3
•
Changed Typical Application schematic. ............................................................................................................................. 14
Changes from Revision E (December 2011) to Revision F
•
Added Applications, Pin Configuration and Functions section, Handling Rating table, Thermal Information table,
Feature Description section, Typical Characteristics section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section ............................................................... 1
Changes from Revision D (September 2007) to Revision E
•
2
Page
Page
Fixed tPZL VCCB = 3.3 V parameter typographical error from 36.6 to 3.6. ............................................................................... 7
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SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
5 Pin Configuration and Functions
1
16
1B2
1OE
VCCB
2B1
15
2OE
16
2
VCCB
1
1DIR
VCCA
VCCA
RSV PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
1B1
D, DGV, OR PW PACKAGE
(TOP VIEW)
16 15 14 13
4
13
1B1
1DIR
2
15
1OE
12
2B2
14
2OE
1OE
VCCB
1
3
2
11
GND
13
1B1
VCCA
3
10
GND
1DIR
4
9
2A2
1A2
5
12
1B2
2DIR
2A1
6
11
2B1
1A1
4
2A2
7
10
2B2
5
GND
8
9
GND
1A2
2A1
12
11
7
10
2B2
8
9
GND
6
1B2
2B1
GND
2A2
GND
or
FLOAT
5
6
7
8
2A1
1A1
1A2
14
1A1
3
2OE
2DIR
2DIR
Pin Functions
PIN
NAME
1A1
NO.
TYPE
DESCRIPTION
D, DGV,
PW, RGY
RSV
4
6
I/O
Input/output 1A1. Referenced to VCCA.
1A2
5
7
I/O
Input/output 1A2. Referenced to VCCA.
1B1
13
15
I/O
Input/output 1B1. Referenced to VCCB.
1B2
12
14
I/O
Input/output 1B2. Referenced to VCCB.
1DIR
2
4
I
Direction-control input for ‘1’ ports
1OE
15
1
I
3-state output-mode enables. Pull OE high to place ‘1’ outputs in 3-state
mode. Referenced to VCCA.
2A1
6
8
I/O
Input/output 2A1. Referenced to VCCA.
2A2
7
9
I/O
Input/output 2A2. Referenced to VCCA.
2B1
11
13
I/O
Input/output 2B1. Referenced to VCCB.
2B2
10
12
I/O
Input/output 2B2. Referenced to VCCB.
2DIR
3
5
I
Direction-control input for ‘2’ ports
2OE
14
16
I
3-state output-mode enables. Pull OE high to place ‘2’ outputs in 3-state
mode. Referenced to VCCA.
GND
8, 9
10, 11
—
Ground
VCCA
1
3
—
A-port power supply voltage. 1.2 V ≤ VCCA ≤ 3.6 V
VCCB
16
2
—
B-port power supply voltage. 1.2 V ≤ VCCB ≤ 3.6 V
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6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
UNIT
VCCA
VCCB
Supply voltage range
VI
Input voltage range (2)
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCCA, VCCB, or GND
(1)
(2)
(3)
V
V
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
Electrostatic discharge
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
8
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
1
Machine model (C101)
(1)
(2)
4
kV
150
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
VCCI
VCCO
MIN
MAX
UNIT
VCCA
Supply voltage
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
High-level
input voltage
VIH
Low-level
input voltage
VIL
Data inputs (4)
Data inputs (4)
1.2 V to 1.95 V
VCCI × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
V
1.2 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
High-level
input voltage
VIH
Low-level
input voltage
VIL
VI
DIR
(referenced to VCCA) (5)
DIR
(referenced to VCCA) (5)
Output voltage
IOH
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
V
1.2 V to 1.95 V
VCCA × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
0
3.6
Active state
0
VCCO
3-state
0
3.6
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(4)
(5)
VCCA × 0.65
High-level output current
IOL
(1)
(2)
(3)
0.8
1.2 V to 1.95 V
Input voltage
VO
V
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.1 V to 1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
–40
V
V
V
mA
mA
5
ns/V
85
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V
6.4 Thermal Information
SN74AVC4T245
THERMAL METRIC
(1)
D
DGV
PW
RGY
RSV
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
85.5
126.0
112.0
37.5
146.9
RθJC(top)
Junction-to-case (top) thermal resistance
46.9
50.8
46.8
54.5
53.6
RθJB
Junction-to-board thermal resistance
43.0
57.7
57.1
15.6
75.6
ψJT
Junction-to-top characterization parameter
13.4
5.7
5.7
0.5
13.5
ψJB
Junction-to-board characterization parameter
42.7
57.2
56.5
15.8
75.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
—
3.5
—
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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6.5 Electrical Characteristics (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VCCA
MIN
TYP
MAX
1.05
1.65 V
1.65 V
1.2
IOH = –9 mA
2.3 V
2.3 V
1.75
IOH = –12 mA
3V
3V
2.3
0.95
1.2 V to 3.6 V 1.2 V to 3.6 V
V
0.2
1.2 V
1.2 V
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
0.7
IOL = 6 mA
IOL = 8 mA
VI = VIL
II
Control
inputs
Ioff
A or B port VI or VO = 0 to 3.6 V
IOZ
A or B port
VI = VCCA or GND
1.2 V to 3.6 V 1.2 V to 3.6 V
VO = VCCO or GND,
VI = VCCI or GND, OE = VIH
0.25
±0.025
±0.25
±1
0V
0 V to 3.6 V
±0.1
±1
±5
0 V to 3.6 V
0V
±0.1
±1
±5
3.6 V
3.6 V
±0.5
±2.5
±5
1.2 V to 3.6 V 1.2 V to 3.6 V
VI = VCCI or GND, IO = 0
VI = VCCI or GND, IO = 0
ICCA + ICCB
VI = VCCI or GND, IO = 0
Ci
Control
inputs
0 V to 3.6 V
–2
0 V to 3.6 V
0V
8
Cio
A or B port VO = 3.3 V or GND
μA
μA
μA
μA
8
0V
0 V to 3.6 V
8
0 V to 3.6 V
0V
–2
1.2 V to 3.6 V 1.2 V to 3.6 V
VI = 3.3 V or GND
V
8
0V
1.2 V to 3.6 V 1.2 V to 3.6 V
ICCB
UNIT
VCCO – 0.2
1.4 V
IOL = 3 mA
6
MIN
1.4 V
VI = VIH
IOL = 100 μA
(1)
(2)
MAX
1.2 V
IOH = –8 mA
ICCA
–40°C to 85°C
1.2 V
IOH = –6 mA
VOL
TA = 25°C
1.2 V to 3.6 V 1.2 V to 3.6 V
IOH = –3 mA
VOH
VCCB
μA
16
μA
3.3 V
3.3 V
3.5
4.5
pF
3.3 V
3.3 V
6
7
pF
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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6.6 Operating Characteristics
TA = 25°C
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
1
1
1
1.5
2
1
1
1
1
1
12
12.5
13
14
15
Outputs
disabled
1
1
1
1
1
Outputs
enabled
12
12.5
13
14
15
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
TEST
CONDITIONS
PARAMETER
A to B
CpdA
(1)
B to A
A to B
CpdB
(1)
B to A
(1)
Outputs
enabled
Outputs
disabled
Outputs
enabled
Outputs
disabled
Outputs
enabled
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
Outputs
disabled
UNIT
pF
pF
Power dissipation capacitance per transceiver
6.7 Switching Characteristics: VCCA = 1.2 V
over recommended operating free-air temperature range, VCCA = 1.2 V (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
TYP
TYP
TYP
TYP
3.4
2.9
2.7
2.6
2.8
3.4
2.9
2.7
2.6
2.8
3.6
3.1
2.8
2.6
2.6
3.6
3.1
2.8
2.6
2.6
5.6
4.7
4.3
3.9
3.7
5.6
4.7
4.3
3.9
3.7
5
4.3
3.9
3.6
3.6
5
4.3
3.9
3.6
3.6
6.2
5.2
5.2
4.3
4.8
6.2
5.2
5.2
4.3
4.8
5.9
5.1
5
4.7
5.5
5.9
5.1
5
4.7
5.5
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UNIT
ns
ns
ns
ns
ns
ns
7
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SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
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6.8 Switching Characteristics: VCCA = 1.5 V ± 0.1 V
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3.2
0.3
6.3
0.3
5.2
0.4
4.2
0.4
4.2
3.2
0.3
6.3
0.3
5.2
0.4
4.2
0.4
4.2
3.3
0.7
6.3
0.5
6
0.4
5.7
0.3
5.6
3.3
0.7
6.3
0.5
6
0.4
5.7
0.3
5.6
4.9
1.4
9.6
1.1
9.5
0.7
9.4
0.4
9.4
4.9
1.4
9.6
1.1
9.5
0.7
9.4
0.4
9.4
4.5
1.4
9.6
1.1
7.7
0.9
5.8
0.9
5.6
4.5
1.4
9.6
1.1
7.7
0.9
5.8
0.9
5.6
5.6
1.8
10.2
1.5
10.2
1.3
10.2
1.6
10.2
5.6
1.8
10.2
1.5
10.2
1.3
10.2
1.6
10.2
5.2
1.9
10.3
1.9
9.1
1.4
7.4
1.2
7.6
5.2
1.9
10.3
1.9
9.1
1.4
7.4
1.2
7.6
UNIT
ns
ns
ns
ns
ns
ns
6.9 Switching Characteristics: VCCA = 1.8 V ± 0.15 V
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
8
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.9
0.1
6
0.1
4.9
0.1
3.9
0.3
3.9
2.9
0.1
6
0.1
4.9
0.1
3.9
0.3
3.9
3
0.6
5.3
0.5
4.9
0.3
4.6
0.3
4.5
3
0.6
5.3
0.5
4.9
0.3
4.6
0.3
4.5
4.4
1
7.4
1
7.3
0.6
7.3
0.4
7.2
4.4
1
7.4
1
7.3
0.6
7.3
0.4
7.2
4.1
1.2
9.2
1
7.4
0.8
5.3
0.8
4.6
4.1
1.2
9.2
1
7.4
0.8
5.3
0.8
4.6
5.4
1.6
8.6
1.8
8.7
1.3
8.7
1.6
8.7
5.4
1.6
8.6
1.8
8.7
1.3
8.7
1.6
8.7
5
1.7
9.9
1.6
8.7
1.2
6.9
1
6.9
5
1.7
9.9
1.6
8.7
1.2
6.9
1
6.9
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UNIT
ns
ns
ns
ns
ns
ns
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6.10 Switching Characteristics: VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
0.1
5.7
0.1
4.6
0.2
3.5
0.1
3.6
2.8
0.1
5.7
0.1
4.6
0.2
3.5
0.1
3.6
2.7
0.6
4.2
0.4
3.9
0.2
3.4
0.2
3.3
2.7
0.6
4.2
0.4
3.9
0.2
3.4
0.2
3.3
4
0.7
6.5
0.7
5.2
0.6
4.8
0.4
4.8
4
0.7
6.5
0.7
5.2
0.6
4.8
0.4
4.8
3.8
0.9
8.8
0.8
7
0.6
4.8
0.6
4
3.8
0.9
8.8
0.8
7
0.6
4.8
0.6
4
4.7
1
8.4
1
8.4
1
6.2
1
6.6
4.7
1
8.4
1
8.4
1
6.2
1
6.6
4.5
1.5
9.4
1.3
8.2
1.1
6.2
0.9
5.2
4.5
1.5
9.4
1.3
8.2
1.1
6.2
0.9
5.2
UNIT
ns
ns
ns
ns
ns
ns
6.11 Switching Characteristics: VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.9
0.1
5.6
0.1
4.5
0.1
3.3
0.1
2.9
2.9
0.1
5.6
0.1
4.5
0.1
3.3
0.1
2.9
2.6
0.6
4.2
0.4
3.4
0.2
3
0.1
2.8
2.6
0.6
4.2
0.4
3.4
0.2
3
0.1
2.8
3.8
0.6
8.7
0.6
5.2
0.6
3.8
0.4
3.8
3.8
0.6
8.7
0.6
5.2
0.6
3.8
0.4
3.8
3.7
0.8
8.7
0.6
6.8
0.5
4.7
0.5
3.8
3.7
0.8
8.7
0.6
6.8
0.5
4.7
0.5
3.8
4.8
0.7
9.3
0.7
8.3
0.7
5.6
0.7
6.6
4.8
0.7
9.3
0.7
8.3
0.7
5.6
0.7
6.6
5.3
1.4
9.3
1.2
8.1
1
6.4
0.8
6.2
5.3
1.4
9.3
1.2
8.1
1
6.4
0.8
6.2
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UNIT
ns
ns
ns
ns
ns
ns
9
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SCES576G – JUNE 2004 – REVISED NOVEMBER 2014
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3.6
3.6
3.2
3.2
2.8
2.8
2.4
2.4
VOH Voltage (V)
VOL Voltage (V)
6.12 Typical Characteristics
2.0
1.6
1.6
1.2
1.2
0.8
0.8
-40 °C
25 °C
85 °C
0.4
-40 °C
25 °C
85 °C
0.4
0
0
0
20
40
60
80
IOL Current (mA)
Figure 1. Low-Level Output Voltage (VOL)
vs Low-Level Current (IOL)
10
2.0
100
0
20
40
60
80
100
IOH Current (mA)
Figure 2. High-Level Output Voltage (VOH)
vs High-Level Current (IOH)
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7 Parameter Measurement Information
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLZ and t PHZ are the same as tdis.
F. t PZL and t PZH are the same as ten.
G. tPLH and t PHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 3. Load and Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74AVC4T245 is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins
and control pins (1DIR, 2DIR,1OE, and 2OE) are supported by VCCA, and Bx pins are supported by VCCB. The A
port is able to accept I/O voltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from
1.2 V to 3.6 V. A high on DIR allows data transmission from Ax to Bx and a low on DIR allows data transmission
from Bx to Ax when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance
state.
8.2 Functional Block Diagram
DIR
OE
A1
B1
A2
B2
Figure 4. Logic Diagram (Positive Logic) for 1/2 of SN74AVC4T245
12
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8.3 Feature Description
8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2-V to 3.6-V
Power-Supply Range
Both VCCA and VCCB can be supplied at any voltage between 1.2 V and 3.6 V; thus, making the device suitable
for translating between any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).
8.3.2 Supports High Speed Translation
The SN74AVC4T245 device can support high data rate applications. The translated signal data rate can be up to
380 Mbps when the signal is translated from 1.8 V to 3.3 V.
8.3.3 Ioff Supports Partial-Power-Down Mode Operation
Ioff will prevent backflow current by disabling I/O output circuits when device is in partial-power-down mode.
8.4 Device Functional Modes
Table 1. Function Table
(Each 2-Bit Section) (1)
CONTROL INPUTS
OE
(1)
OUTPUT CIRCUITS
B PORT
OPERATION
DIR
A PORT
L
L
Enabled
Hi-Z
B data to A bus
L
H
Hi-Z
Enabled
A data to B bus
H
X
Hi-Z
Hi-Z
Isolation
Input circuits of the data I/Os are always active.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AVC4T245 device can be used in level-translation applications for interfacing devices or systems
operating at different interface voltages with one another. The SN74AVC4T245 device is ideal for use in
applications where a push-pull driver is connected to the data I/Os. The max data rate can be up to 380 Mbps
when device translates a signal from 1.8 V to 3.3 V.
9.2 Typical Application
1.2 V
3.3 V
0.1 μC
0.1 μC
VCCA
1 µF
VCCB
1OE
2OE
1DIR
2DIR
1.2 V
Controller
Data
GND
3.3 V
System
SN74AVC4T245
1A1
1B1
1A2
1B2
2A1
2B1
2A2
2B2
Data
GND
GND
Figure 5. Typical Application Diagram
14
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Typical Application (continued)
9.2.1 Design Requirements
For the design example shown in Typical Application, use the parameters listed in Table 2.
Table 2. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage range
1.2 V to 3.6 V
Output voltage range
1.2 V to 3.6 V
9.2.2 Detailed Design Procedure
To begin the design process, determine the following:
• Input voltage range
– Use the supply voltage of the device that is driving the SN74AVC4T245 device to determine the input
voltage range. For a valid logic high, the value must exceed the VIH of the input port. For a valid logic low,
the value must be less than the VIL of the input port.
• Output voltage range
– Use the supply voltage of the device that the SN74AVC4T245 device is driving to determine the output
voltage range.
9.2.3 Application Curves
Input (1.2 V)
Output (3.3 V)
Figure 6. Translation Up (1.2 V to 3.3 V) at 2.5 MHz
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10 Power Supply Recommendations
The SN74AVC4T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA accepts
any supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port and
B port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation between
any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.3-V voltage nodes.
The output-enable (OE) input circuit is designed so that it is supplied by VCCA and when the OE input is high, all
outputs are placed in the high-impedance state. To ensure the high-impedance state of the outputs during power
up or power down, the OE input pin must be tied to VCCA through a pullup resistor and must not be enabled until
VCCA and VCCB are fully ramped and stable. The minimum value of the pullup resistor to VCCA is determined by
the current-sinking capability of the driver.
11 Layout
11.1 Layout Guidelines
To
•
•
•
ensure reliability of the device, following common printed-circuit board layout guidelines is recommended.
Bypass capacitors should be used on power supplies.
Short trace lengths should be used to avoid excessive loading.
Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of
signals, depending on the system requirements.
11.2 Layout Example
LEGEND
VIA to Power Plane
Polygonal Copper Pour
VIA to GND Plane (Inner Layer)
VCCB
VCCA
Bypass Capacitor
Bypass Capacitor
VCCA
1
VCCA
VCCB
16
2
1DIR
1OE
15
3
2DIR
2OE
14
From
Controller
4
1A1
1B1
13
To
System
From
Controller
5
1A2
1B2
12
To
System
To
Controller
6
2A1
2B1
11
From
System
To
Controller
7
2A2
2B2
10
From
System
8
GND
GND
9
Keep OE high until VCCA and
VCCB are powered up
SN74AVC4T245
16
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12 Device and Documentation Support
12.1 Trademarks
All trademarks are the property of their respective owners.
12.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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13.1 Package Materials Information
13.1.1 Tape and Reel Information
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
B0 W
Reel
Diameter
Cavity
A0
B0
K0
W
P1
A0
Dimension designed to accommodate the component width
Dimension designed to accommodate the component length
Dimension designed to accommodate the component thickness
Overall width of the carrier tape
Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1
Q2
Q1
Q2
Q3
Q4
Q3
Q4
User Direction of Feed
Pocket Quadrants
Device
Package
Type
Package
Drawing
Pins
SPQ
Reel
Diameter
(mm)
Reel
Width W1
(mm)
A0
(mm)
SN74AVC4T245DGVR
TVSOP
DGV
16
2000
330.0
12.4
SN74AVC4T245DR
SOIC
D
16
2500
330.0
16.4
SN74AVC4T245PWR
TSSOP
PW
16
2000
330.0
SN74AVC4T245RGYR
VQFN
RGY
16
3000
SN74AVC4T245RGYR
VQFN
RGY
16
SN74AVC4T245RSVR
UQFN
RSV
16
18
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
6.8
4.0
1.6
8.0
12.0
Q1
6.5
10.3
2.1
8.0
16.0
Q1
12.4
6.9
5.6
1.6
8.0
12.0
Q1
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
3000
180.0
12.4
2.1
2.9
0.75
4.0
12.0
Q1
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TAPE AND REEL BOX DIMENSIONS
Width (mm)
W
L
H
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AVC4T245DGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74AVC4T245DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AVC4T245PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74AVC4T245RGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
SN74AVC4T245RGYR
VQFN
RGY
16
3000
355.0
350.0
50.0
SN74AVC4T245RSVR
UQFN
RSV
16
3000
203.0
203.0
35.0
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PACKAGE OPTION ADDENDUM
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21-Dec-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74AVC4T245DGVRE4
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
74AVC4T245RGYRG4
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
WT245
74AVC4T245RSVR-NT
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZWU
74AVC4T245RSVRG4
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZWU
HPA00719RSVR
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZWU
SN74AVC4T245D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AVC4T245
SN74AVC4T245DGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AVC4T245
SN74AVC4T245DRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AVC4T245
SN74AVC4T245DT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AVC4T245
SN74AVC4T245PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWE4
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWRE4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245PWTE4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
21-Dec-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AVC4T245PWTG4
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
WT245
SN74AVC4T245RGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
WT245
SN74AVC4T245RSVR
ACTIVE
UQFN
RSV
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ZWU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
21-Dec-2018
OTHER QUALIFIED VERSIONS OF SN74AVC4T245 :
• Automotive: SN74AVC4T245-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
74AVC4T245RSVR-NT
Package Package Pins
Type Drawing
UQFN
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
RSV
16
3000
180.0
B0
(mm)
K0
(mm)
P1
(mm)
9.5
2.1
2.9
0.75
4.0
W
Pin1
(mm) Quadrant
8.0
Q1
74AVC4T245RSVR-NT
UQFN
RSV
16
3000
180.0
8.4
2.0
2.8
0.7
4.0
8.0
Q1
SN74AVC4T245DGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74AVC4T245DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AVC4T245PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AVC4T245PWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AVC4T245RGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
SN74AVC4T245RSVR
UQFN
RSV
16
3000
178.0
13.5
2.1
2.9
0.75
4.0
12.0
Q1
SN74AVC4T245RSVR
UQFN
RSV
16
3000
180.0
12.4
2.1
2.9
0.75
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
74AVC4T245RSVR-NT
UQFN
RSV
16
3000
189.0
185.0
36.0
74AVC4T245RSVR-NT
UQFN
RSV
16
3000
203.0
203.0
35.0
SN74AVC4T245DGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74AVC4T245DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AVC4T245PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74AVC4T245PWT
TSSOP
PW
16
250
367.0
367.0
35.0
SN74AVC4T245RGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
SN74AVC4T245RSVR
UQFN
RSV
16
3000
189.0
185.0
36.0
SN74AVC4T245RSVR
UQFN
RSV
16
3000
203.0
203.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
RSV0016A
UQFN - 0.55 mm max height
SCALE 5.000
ULTRA THIN QUAD FLATPACK - NO LEAD
1.85
1.75
B
A
PIN 1 INDEX AREA
2.65
2.55
C
0.55
0.45
SEATING PLANE
0.05 C
0.05
0.00
2X 1.2
SYMM
5
(0.13) TYP
8
15X
4
0.45
0.35
9
SYMM
2X 1.2
12X 0.4
1
12
16
0.55
0.45
16X
0.25
0.15
0.07
0.05
C A B
13
PIN 1 ID
(45 X 0.1)
4220314/B 05/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
SYMM
(0.7)
16
SEE SOLDER MASK
DETAIL
13
12
1
16X (0.2)
SYMM
12X (0.4)
(R0.05) TYP
(2.4)
9
4
15X (0.6)
8
5
(1.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 25X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
OPENING
SOLDER MASK DEFINED
SOLDER MASK DETAILS
4220314/B 05/2019
NOTES: (continued)
3. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
RSV0016A
UQFN - 0.55 mm max height
ULTRA THIN QUAD FLATPACK - NO LEAD
(0.7)
13
16
16X (0.2)
12
1
SYMM
12X (0.4)
(2.4)
(R0.05) TYP
4
9
15X (0.6)
5
8
SYMM
(1.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 25X
4220314/B 05/2019
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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