Texas Instruments | SN74LV08A Quadruple 2-Input Positive-AND Gates (Rev. M) | Datasheet | Texas Instruments SN74LV08A Quadruple 2-Input Positive-AND Gates (Rev. M) Datasheet

Texas Instruments SN74LV08A Quadruple 2-Input Positive-AND Gates (Rev. M) Datasheet
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SN74LV08A
SCLS387M – SEPTEMBER 1997 – REVISED OCTOBER 2014
SN74LV08A Quadruple 2-Input Positive-AND Gates
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 7 ns at 5 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
Servers
Telecom Infrastructure
PCs and Notebooks
TV Set-Top Boxes
3 Description
This quadruple 2-input positive-AND gate is designed
for 2-V to 5.5-V VCC operation. The SN74LV08A
device
performs
the
Boolean
function
Y = A • B or Y = A + B in positive logic.
Device Information(1)
PART NUMBER
SN74LV08A
PACKAGE
BODY SIZE (NOM)
TVSOP (14)
3.60 mm × 4.40 mm
SOIC (14)
8.65 mm × 3.91 mm
VQFN (14)
3.50 mm× 3.50 mm
SSOP (14)
6.20 mm × 5.30 mm
TSSOP (14)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
A
B
A
B
A
B
A
B
Y
Y
Y
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV08A
SCLS387M – SEPTEMBER 1997 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
6
6
7
7
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics........................................
Typical Characteristics ............................................
8
9
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
9
9
9
9
10 Application and Implementation........................ 10
10.1 Application Information.......................................... 10
10.2 Typical Application ............................................... 10
11 Power Supply Recommendations ..................... 11
12 Layout................................................................... 11
12.1 Layout Guidelines ................................................. 11
12.2 Layout Example .................................................... 11
13 Device and Documentation Support ................. 12
13.1 Trademarks ........................................................... 12
13.2 Electrostatic Discharge Caution ............................ 12
13.3 Glossary ................................................................ 12
14 Mechanical, Packaging, and Orderable
Information ........................................................... 12
5 Revision History
Changes from Revision L (October 2010) to Revision M
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Deleted SN54LV08A device from data sheet......................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 5
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 7
•
Added Detailed Description section........................................................................................................................................ 9
•
Added Application and Implementation section.................................................................................................................... 10
•
Added Power Supply Recommendations and Layout sections............................................................................................ 11
2
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6 Pin Configuration and Functions
13
3
12
4
11
5
10
6
9
7
8
VCC
4B
4A
4Y
3B
3A
3Y
1B
1Y
2A
2B
2Y
VCC
14
2
1
14
2
13 4B
3
12 4A
4Y
4
11
5
10 3B
9 3A
6
7
8
3Y
1
GND
1A
1B
1Y
2A
2B
2Y
GND
1A
SN74LV08A . . . RGY PACKAGE
(TOP VIEW)
SN74LV08A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
SN74LV08A
NAME
I/O
DESCRIPTION
D, DB, DGV,
NS, PW, RGY
1A
1
I
1A Input
1B
1Y
2
I
1B Input
3
O
1Y Output
2A
4
I
2A Input
2B
5
I
2B Input
2Y
6
O
2Y Output
3Y
8
O
3Y Output
3A
9
I
3A Input
3B
10
I
3B Input
4Y
11
O
4Y Output
4A
12
I
4A Input
4B
13
I
4B Input
GND
7
—
Ground Pin
VCC
14
—
Power Pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
VI
Input voltage range
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range (2) (3)
−0.5 VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN74LV08A
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
V
1.5
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
VCC = 2 V
VIL
UNIT
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
V
VCC × 0.3 5
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
V
–50
µA
VCC = 2 V
IOH
VCC = 2.3 V to 2.7 V
High-level output current
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
Δt/Δv
50
VCC = 2.3 V to 2.7 V
Low-level output current
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
µA
2
VCC = 3 V to 3.6 V
Input transition rise and fall rate
mA
–12
VCC = 2 V
IOL
V
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LV08A
THERMAL METRIC (1)
D
DB
DGV
N
NS
PW
RGY
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
14 PINS
RθJA
Junction-to-ambient thermal
resistance
90.6
107.1
129.0
57.4
90.7
122.6
57.5
RθJC(top)
Junction-to-case (top) thermal
resistance
50.9
59.6
52.1
44.9
48.3
51.4
70.8
RθJB
Junction-to-board thermal
resistance
44.8
54.4
62.0
37.2
49.4
64.4
33.6
ψJT
Junction-to-top characterization
parameter
14.7
20.5
6.5
30.1
14.6
6.7
3.4
ψJB
Junction-to-board characterization
parameter
44.5
53.8
61.3
37.1
49.1
63.8
33.7
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
–
–
–
–
–
–
13.9
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN74LV08A
–40°C to 85°C
VCC
MIN
VOH
IOH = –50 µA
2 V to 5.5 V
IOH = –2 mA
2.3 V
IOH = –6 mA
IOH = –12 mA
VOL
MAX
VCC – 0.1
MIN
TYP
UNIT
MAX
VCC – 0.1
2
2
3V
2.48
2.48
4.5 V
3.8
V
3.8
IOL = 50 µA
2 V to 5.5 V
0.1
IOL = 2 mA
2.3 V
0.4
0.4
IOL = 6 mA
3V
0.44
0.44
4.5 V
IOL = 12 mA
II
VI = 5.5 V or GND
ICC
VI = VCC or GND,
Ioff
VI or VO = 0 to 5.5 V
Ci
TYP
SN74LV08A
–40°C to 125°C
IO = 0
V
0.55
0.55
0 to 5.5 V
±1
±1
µA
5.5 V
20
20
µA
5
µA
0
VI = VCC or GND
0.1
5
3.3 V
3.3
3.3
5V
3.3
3.3
pF
7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN74LV08A
–40°C to 125°C
SN74LV08A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
7.9 (1)
13.8 (1)
1
16
1
17
CL = 50 pF
10.5
17.3
1
20
1
21
UNIT
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN74LV08A
–40°C to 125°C
SN74LV08A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
5.6 (1)
8.8 (1)
1
10.5
1
11.5
CL = 50 pF
7.5
12.3
1
14
1
15
UNIT
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
(1)
6
FROM
(INPUT)
TO
(OUTPUT)
A or B
Y
LOAD
CAPACITANCE
TA = 25°C
MIN
SN74LV08A
–40°C to 125°C
SN74LV08A
TYP
MAX
MIN
MAX
MIN
MAX
CL = 15 pF
4.1 (1)
5.9 (1)
1
7
1
8
CL = 50 pF
5.5
7.9
1
9
1
10
UNIT
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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7.9 Noise Characteristics (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV08A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.2
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.1
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3.1
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
TYP
UNIT
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
CL = 50 pF,
VCC
f = 10 MHz
3.3 V
8
5V
10
pF
7.11 Typical Characteristics
6
9
TPD in ns
TPD in ns
8
5
7
4
TPD (ns)
TPD (ns)
6
5
4
3
2
3
2
1
1
0
0
1
2
3
4
VCC (V)
5
6
0
-100
D001
Figure 1. TPD vs VCC
-50
0
50
Temperature (qC)
100
150
D002
Figure 2. TPD vs Temperature
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8 Parameter Measurement Information
VCC
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
50% VCC
50% VCC
VOH
50% VCC
VOL
tPLZ
≈VCC
50% VCC
VOL + 0.3 V
50% VCC
VOH − 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
≈0 V
A.
F.
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
Output
Waveform 1
S1 at VCC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
50% VCC
tPZL
tPHL
tPLH
In-Phase
Output
0V
VCC
Output
Control
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
This quadruple 2-input positive-AND gate is designed for 2-V to 5.5-V VCC operation. The SN74LA08A device
performs the Boolean function Y = A • B or Y = A + B in positive logic.
This device is fully specified for partial-power-down application using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
9.2 Functional Block Diagram
A
Y
B
Figure 4. Logic Diagram, Each Gate (Positive Logic)
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates From 2 V to 5.5 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the input or output when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
(Each Gate)
INPUTS
A
B
OUTPUT
Y
H
H
H
L
X
L
X
L
L
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LV08A is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages up to 5.5 V at any valid VCC, thus making it ideal for down
translation.
10.2 Typical Application
5V
5V
VCC
1A
C or System
Logic
1Y
SN74LV08A
4A
C/System
Logic/LEDs
4Y
GND
Figure 5. Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– For specified high and low levels, see VIH and VIL in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10
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Typical Application (continued)
10.2.3 Application Curves
Figure 6. Application Curves
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1 μF capacitor is recommended. If there are multiple VCC terminals then 0.01 μF or 0.022 μF
capacitors are recommended for each power terminal. It is ok to parallel multiple bypass capacitors to reject
different frequencies of noise. 0.1 μF and 1.0 μF capacitors are commonly used in parallel. The bypass capacitor
should be installed as close to the power terminal as possible for the best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such input pins should not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states.
Specified in Figure 7 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that should be
applied to any particular unused input depends on the function of the device. Generally they will be tied to GND
or VCC, whichever makes more sense or is more convenient. It is acceptable to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when
asserted. This will not disable the input section of the I/Os so they also cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
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13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
12
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV08AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ADBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ADE4
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ADGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ADR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ADRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ANSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV08A
SN74LV08APW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWRE4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWRG3
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWT
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08APWTG4
ACTIVE
TSSOP
PW
14
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV08A
SN74LV08ARGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV08A
SN74LV08ARGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV08A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV08A :
• Automotive: SN74LV08A-Q1
• Enhanced Product: SN74LV08A-EP
NOTE: Qualified Version Definitions:
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV08ADGVR
Package Package Pins
Type Drawing
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGV
14
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LV08ADR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74LV08APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV08APWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV08APWRG3
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV08APWRG4
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV08APWT
TSSOP
PW
14
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV08ARGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV08ADGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74LV08ADR
SOIC
D
14
2500
367.0
367.0
38.0
SN74LV08APWR
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74LV08APWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LV08APWRG3
TSSOP
PW
14
2000
364.0
364.0
27.0
SN74LV08APWRG4
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74LV08APWT
TSSOP
PW
14
250
367.0
367.0
35.0
SN74LV08ARGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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