Texas Instruments | SNx4LV245A Octal Bus Transceivers With 3-State Outputs (Rev. O) | Datasheet | Texas Instruments SNx4LV245A Octal Bus Transceivers With 3-State Outputs (Rev. O) Datasheet

Texas Instruments SNx4LV245A Octal Bus Transceivers With 3-State Outputs (Rev. O) Datasheet
Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
SNx4LV245A Octal Bus Transceivers With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 6.5 ns at 5 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Servers
LED Displays
Network Switches
Telecom Infrastructure
Motor Drivers
I/O Expanders
3 Description
These octal bus transceivers are designed for 2-V to
5.5-V VCC operation.
Device Information
PART NUMBER
SNx4LV245A
PACKAGE
BODY SIZE (NOM)
SSOP (20)
7.20 mm × 5.30 mm
TVSOP (20)
5.00 mm × 4.40 mm
TSSOP (20)
6.50 mm × 4.40 mm
VQFN (20)
4.50 mm × 3.50 mm
SOIC (20)
12.80 mm × 7.50 mm
4 Simplified Schematic
DIR
OE
A1
B1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
5
5
6
6
7
7
8
8
8
8
9
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, VCC = 2.5 V ± 0.2 V ........
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ................................................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
9
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision N (August 2012) to Revision O
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 5
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions table. ......................................... 6
•
Added –40°C to 125°C for SN74LV245A in Electrical Characteristics table.......................................................................... 7
•
Added –40°C to 125°C for SN74LV245A in all three Switching Characteristics tables. ........................................................ 7
•
Added Typical Characteristics. ............................................................................................................................................... 9
•
Added Detailed Description section...................................................................................................................................... 11
•
Added Application and Implementation section.................................................................................................................... 12
•
Added Power Supply Recommendations and Layout sections............................................................................................ 13
2
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
6 Pin Configuration and Functions
2
19
3
18
4
5
17
16
6
15
7
14
8
13
9
12
10
11
A1
A2
A3
A4
A5
A6
A7
A8
1
20
A2
A1
DIR
VCC
OE
VCC
VCC
OE
B1
B2
B3
B4
B5
B6
B7
B8
2
19 OE
3
18 B1
4
17 B2
16 B3
5
15 B4
14 B5
6
7
8
13 B6
12 B7
9
10
SN54LV245A . . . FK PACKAGE
(TOP VIEW)
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
B1
B2
B3
B4
B5
11
B8
20
DIR
1
GND
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN74LV245A . . . RGY PACKAGE
(TOP VIEW)
A8
GND
B8
B7
B6
SN54LV245A . . . J OR W PACKAGE
SN74LV245A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
DIR
I
Direction Pin
2
A1
I/O
A1 I/O
3
A2
I/O
A2 I/O
4
A3
I/O
A3 I/O
5
A4
I/O
A4 I/O
6
A5
I/O
A5 I/O
7
A6
I/O
A6 I/O
8
A7
I/O
A7 I/O
9
A8
I/O
A8 I/O
10
GND
—
Ground Pin
11
B8
I/O
B8 I/O
12
B7
I/O
B7 I/O
13
B6
I/O
B6 I/O
14
B5
I/O
B5 I/O
15
B4
I/O
B4 I/O
16
B3
I/O
B3 I/O
17
B2
I/O
B2 I/O
18
B1
I/O
B1 I/O
19
OE
I
20
VCC
—
Output Enable
Power Pin
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
Submit Documentation Feedback
3
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
GQN PACKAGE
(TOP VIEW)
1
4
2
3
www.ti.com
Pin Assignments
4
1
2
3
4
A
A
A1
DIR
VCC
OE
B
B
A3
B2
A2
B1
C
C
A5
A4
B4
B3
D
D
A7
B6
A6
B5
E
E
GND
A8
B8
B7
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
Supply voltage range
Except I/O ports
(2)
VI
Input voltage range
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
I/O ports (2) (3)
(2) (3)
MIN
MAX
–0.5
7
–0.5
7
–0.5
7
–0.5
7
–0.5
VCC + 0.5
UNIT
V
V
V
VO
Output voltage range applied in the high or low state
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
Continuous current through VCC or GND
(1)
(2)
(3)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5-V maximum.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
Submit Documentation Feedback
5
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LV245A (2)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
VI
Output voltage
High-level output current
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
Δt/Δv
Input transition rise or fall rate
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
VCC = 4.5 V to 5.5 V
VCC × 0.3
VCC × 0.3
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
–50
–50
VCC = 2.3 V to 2.7 V
–2
–2
VCC = 3 V to 3.6 V
–8
–8
–16
–16
50
50
VCC = 2.3 V to 2.7 V
2
2
VCC = 3 V to 3.6 V
8
8
VCC = 4.5 V to 5.5 V
16
16
VCC = 2.3 V to 2.7 V
200
200
VCC = 3 V to 3.6 V
100
100
20
20
(1)
(2)
Operating free-air temperature
V
VCC × 0.7
VCC = 4.5 V to 5.5 V
TA
UNIT
V
0.5
VCC = 2 V
Low-level output current
5.5
VCC × 0.7
VCC = 4.5 V to 5.5 V
IOL
2
VCC = 2.3 V to 2.7 V
VCC = 2 V
IOH
MAX
1.5
Input voltage
VO
MIN
1.5
VCC = 2 V
VIL
SN74LV245A
–55
125
–40
125
V
V
V
µA
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
Product Preview
7.4 Thermal Information
SN74LV245A
THERMAL METRIC
(1)
DB
DGV
DW
NS
PW
RGY
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
94.6
114.8
77.5
76.6
101.5
34.1
RθJC(top)
Junction-to-case (top) thermal resistance
56.3
30.1
43.7
43.0
35.6
38.4
RθJB
Junction-to-board thermal resistance
49.8
56.3
45.1
44.1
52.5
12.0
ψJT
Junction-to-top characterization parameter
18.3
0.9
16.9
16.7
2.2
0.8
ψJB
Junction-to-board characterization
parameter
49.4
55.6
44.7
43.7
52.0
12.0
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
—
—
—
—
—
7.1
(1)
6
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP
VOH
VOL
–40°C to 85°C
SN74LV245A
SN54LV245A (1)
VCC
MAX
MIN
TYP
–40°C to 125°C
SN74LV245A
MAX
MIN
TYP
UNIT
MAX
IOH = –50 µA
2 V to
5.5 V
IOH = –2 mA
2.3 V
2
2
2
IOH = –8 mA
3V
2.48
2.48
2.48
IOH = –16 mA
4.5 V
3.8
3.8
3.8
IOL = 50 µA
2 V to
5.5 V
IOL = 2 mA
2.3 V
0.4
0.4
0.4
IOL = 8 mA
3V
0.44
0.44
0.44
IOL = 16 mA
4.5 V
0.55
0.55
0.55
±1
±1
±1
µA
II
Control inputs
VI = 5.5 V or GND
0 to
5.5 V
IOZ
A or B port
VCC – 0.1
VCC – 0.1
VCC – 0.1
0.1
V
0.1
0.1
V
VO = VCC or GND
5.5 V
±5
±5
±5
µA
ICC
VI = VCC or GND, IO = 0
5.5 V
20
20
20
µA
Ioff
VI or VO = 0 to 5.5 V
0
5
5
5
µA
Ci
Control inputs
VI = VCC or GND
Cio
A or B port
VO = VCC or GND
(1)
3.3 V
3
3
5V
3
3
3.3 V
5.5
5.5
5V
5.5
5.5
pF
pF
Product Preview
7.6 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
LOAD
CAPACITANCE
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B or A
8.3 (2)
13 (2)
1 (2)
15 (2)
1
15
1
17
(2)
(2)
(2)
(2)
CL = 15 pF
MIN
–40°C to 125°C
SN74LV245A
SN74LV245A
TYP
ten
OE
A or B
1
22
1
24
tdis
OE
A or B
11.8 (2)
18.1 (2)
1 (2)
20 (2)
1
20
1
22
tpd
A or B
B or A
11.2
15.9
1
18
1
18
1
21
ten
OE
A or B
14.1
22.7
1
26
1
26
1
28
tdis
OE
A or B
17.6
23.1
1
25
1
25
1
27
CL = 50 pF
tsk(o)
(1)
(2)
SN54LV245A (1)
TA = 25°C
11.8
19.9
1
22
2
UNIT
ns
ns
2
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
Submit Documentation Feedback
7
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
7.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
A or B
SN54LV245A (1)
TA = 25°C
LOAD
CAPACITANCE
MIN
TYP
MAX
MIN
MAX
MIN
B or A
5.9 (2)
8.4 (2)
1 (2)
10 (2)
(2)
(2)
(2)
15.5 (2)
CL = 15 pF
8.2
(1)
(2)
MIN
MAX
1
10
1
11
1
15.5
1
16.5
OE
A or B
tdis
OE
A or B
9.6 (2)
16.5 (2)
1 (2)
19.5 (2)
1
19.5
1
20.5
tpd
A or B
B or A
7.9
11.9
1
13.5
1
13.5
1
14.5
ten
OE
A or B
9.9
16.7
1
19
1
19
1
20
tdis
OE
A or B
13.9
19.8
1
22
1
22
1
23
tsk(o)
1
UNIT
MAX
ten
CL = 50 pF
13.2
–40°C to 125°C
SN74LV245A
SN74LV245A
1.5
ns
ns
1.5
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.8 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
tpd
LOAD
CAPACITANCE
TO
(OUTPUT)
A or B
B or A
4.3 (2)
(2)
MIN
CL = 15 pF
TYP
5.7
MAX
–40°C to 125°C
SN74LV245A
SN74LV245A
UNIT
MIN
MAX
MIN
MAX
MIN
5.5 (2)
1 (2)
6.5 (2)
1
6.5
1
7
(2)
(2)
10.6 (2)
1
10
1
10.5
12.8 (2)
1 (2)
14.7 (2)
1
14.2
1
14.7
OE
A or B
tdis
OE
A or B
7.8 (2)
tpd
A or B
B or A
5.6
7.5
1
8.5
1
8.5
1
9
ten
OE
A or B
7
10.6
1
12
1
12
1
12.5
tdis
OE
A or B
10.9
14.7
1
16
1
16
1
16.5
CL = 50 pF
8.5
1
MAX
ten
tsk(o)
(1)
(2)
SN54LV245A (1)
TA = 25°C
FROM
(INPUT)
1
ns
ns
1
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
7.9 Noise Characteristics (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
SN74LV245A
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.5
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.4
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
2.9
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
8
Power dissipation capacitance
Submit Documentation Feedback
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
20
5V
25
UNIT
pF
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
7.11 Typical Characteristics
10
14
TPD in ns
TPD in ns
12
8
6
TPD (ns)
TPD (ns)
10
4
8
6
4
2
2
0
-100
0
-50
0
50
Temperature qC)
100
150
0
1
D001
Figure 1. TPD vs Temperature at 3.3V
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
2
3
VCC
4
5
6
D001
Figure 2. TPD vs VCC
Submit Documentation Feedback
9
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
8 Parameter Measurement Information
VCC
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
CL
(see Note A)
S1
Open
TEST
GND
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
Input
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPHL
tPLH
In-Phase
Output
50% VCC
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
9 Detailed Description
9.1 Overview
The SNx4LV245A devices are designed for asynchronous communication between data buses. The device
transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are
effectively isolated.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
9.2 Functional Block Diagram
DIR
OE
A1
B1
To Seven Other Channels
Figure 4. Logic Diagram (Positive Logic)
9.3 Feature Description
•
•
Allows down voltage translation from 5 V to 3.3 V
– Inputs accept voltage levels up to 5.5 V
Slow edge rates minimize output ringing
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
OE
DIR
OPERATION
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
Submit Documentation Feedback
11
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
10 Application and Implementation
10.1 Application Information
The SNx4LV245A is a low-drive CMOS device that can be used for a multitude of bus-interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs can accept voltages to 5.5 V at any valid VCC making the device ideal for down
translation.
10.2 Typical Application
Regulated 5 V
Regulated 5 V
OE
VCC
OE
DIR
A1
5-V LEDs, relays,
or other
system boards
DIR
B1
3.3-V µC
or other
system boards
B8
A8
VCC
GND
µC
5-V LEDs, relays
or other
system boards
A1
B1
A8
B8
GND
µC
5-V LEDs, relays
or other
system boards
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention, because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive, but the high drive will also create faster edges into light loads; therefore, routing and load
conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
– Rise time and fall time specifications, see (Δt/ΔV) in Recommended Operating Conditions table.
– Specified high and low levels, see (VIH and VIL) in Recommended Operating Conditions table.
– Inputs are overvoltage tolerant, allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions:
– Load currents should not exceed 35 mA per output and 70 mA total for the part.
– Outputs should not be pulled above VCC.
12
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
SN54LV245A, SN74LV245A
www.ti.com
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
Typical Application (continued)
10.2.3 Application Curves
AC245
HC245
LV245
LV
Figure 6. Switching Characteristics Comparison
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended and if there are multiple VCC terminals then 0.01 μF or 0.022 μF is recommended
for each power terminal. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise.
A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the
power terminal as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 7 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs
section of the part when asserted. This will not disable the input section of the I/Os so they cannot float when
disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 7. Layout Diagram
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
Submit Documentation Feedback
13
SN54LV245A, SN74LV245A
SCLS382O – SEPTEMBER 1997 – REVISED SEPTEMBER 2014
www.ti.com
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV245A
Click here
Click here
Click here
Click here
Click here
SN74LV245A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54LV245A SN74LV245A
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV245ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ADWE4
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV245A
SN74LV245ANSRG4
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV245A
SN74LV245APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245APWRG3
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV245A
SN74LV245ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV245A
SN74LV245AZQNR
LIFEBUY
BGA
MICROSTAR
JUNIOR
ZQN
20
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LV245A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2020
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
8.2
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LV245ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LV245ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV245ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV245ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV245APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LV245APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV245APWRG3
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LV245ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
ZQN
20
1000
330.0
12.4
3.3
4.3
1.6
8.0
12.0
Q1
SN74LV245AZQNR
BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV245ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LV245ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LV245ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV245ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV245APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LV245APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV245APWRG3
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LV245ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
SN74LV245AZQNR
BGA MICROSTAR
JUNIOR
ZQN
20
1000
350.0
350.0
43.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2020, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising