Texas Instruments | SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs (Rev. B) | Datasheet | Texas Instruments SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs (Rev. B) Datasheet

Texas Instruments SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs (Rev. B) Datasheet
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SN74LVC16374A
SCAS728B – OCTOBER 2003 – REVISED SEPTEMBER 2014
SN74LVC16374A 16-Bit Edge-Triggered D-Type Flip-Flop With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
1
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input and Output Voltages
With 3.3-V VCC)
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Servers
PCs and Notebooks
Network Switches
Electronic Points of Sale
3 Description
This 16-bit edge-triggered D-type flip-flop is designed
for 1.65-V to 3.6-V VCC operation.
Device Information(1)
PART NUMBER
SN74LVC16374A
PACKAGE
BODY SIZE (NOM)
SSOP (48)
15.80 mm × 7.50 mm
TSSOP (48)
12.50 mm × 6.10 mm
TVSOP (48)
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
2OE
1CLK
2CLK
C1
1D1
1D
To Seven Other Channels
C1
1Q1
2D1
1D
2Q1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC16374A
SCAS728B – OCTOBER 2003 – REVISED SEPTEMBER 2014
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
6
6
7
7
8
8
8
9
9
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
9
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1 Trademarks ........................................................... 14
13.2 Electrostatic Discharge Caution ............................ 14
13.3 Glossary ................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
Changes from Revision A (October 2005) to Revision B
Page
•
Updated document to new TI data sheet standards. ............................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Changed Ioff bullet in Features................................................................................................................................................ 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table...................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 6
•
Changed MAX operating temperature to 125°C in Recommended Operating Conditions. .................................................. 7
•
Added Thermal Information table. .......................................................................................................................................... 7
•
Added Typical Characteristics section.................................................................................................................................... 9
•
Added Detailed Description section...................................................................................................................................... 11
•
Added Application and Implementation section.................................................................................................................... 12
•
Added Power Supply Recommendations and Layout sections............................................................................................ 13
2
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6 Pin Configuration and Functions
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1CLK
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2CLK
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
1OE
I
Output Enable 1
2
1Q1
O
1Q1 Output
3
1Q2
O
1Q2 Output
4
GND
—
Ground Pin
5
1Q3
O
1Q3 Output
6
1Q4
O
1Q4 Output
7
VCC
—
Power Pin
8
1Q5
O
1Q5 Output
9
1Q6
O
1Q6 Output
10
GND
—
Ground Pin
11
1Q7
O
1Q7 Output
12
1Q8
O
1Q8 Output
13
2Q1
O
2Q1 Output
14
2Q2
O
2Q2 Output
15
GND
—
Ground Pin
16
2Q3
O
2Q3 Output
17
2Q4
O
2Q4 Output
18
VCC
—
Power Pin
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Pin Functions (continued)
PIN
NO.
4
NAME
I/O
DESCRIPTION
19
2Q5
O
2Q5 Output
20
2Q6
O
2Q6 Output
21
GND
—
Ground Pin
22
2Q7
O
2Q7 Output
23
2Q8
O
2Q8 Output
24
2OE
O
Output Enable 2
25
2CLK
I
Clock 2
26
2D8
I
2D8 Input
27
2D7
I
2D7 Input
28
GND
—
29
2D6
I
2D6 Input
30
2D5
I
2D5 Input
31
VCC
—
Power Pin
32
2D4
I
2D4 Input
33
2D3
I
2D3 Input
34
GND
—
35
2D2
I
2D2 Input
36
2D1
I
2D1 Input
37
1D8
I
1D8 Input
38
1D7
I
1D7 Input
39
GND
—
40
1D6
I
1D6 Input
41
1D5
I
1D5 Input
42
VCC
—
Power Pin
43
1D4
I
1D4 Input
44
1D3
I
1D3 Input
45
GND
—
46
1D2
I
1D2 Input
47
1D1
I
1D1 Input
48
1CLK
I
Clock 1
Ground Pin
Ground Pin
Ground Pin
Ground Pin
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GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
Table 1. Pin Assignments (1)
(56-Ball GQL or ZQL Package)
(1)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
1CLK
B
1Q2
1Q1
GND
GND
1D1
1D2
C
1Q4
1Q3
VCC
VCC
1D3
1D4
D
1Q6
1Q5
GND
GND
1D5
1D6
E
1Q8
1Q7
1D7
1D8
F
2Q1
2Q2
2D2
2D1
G
2Q3
2Q4
GND
GND
2D4
2D3
H
2Q5
2Q6
VCC
VCC
2D6
2D5
J
2Q7
2Q8
GND
GND
2D8
2D7
K
2OE
NC
NC
NC
NC
2CLK
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
Table 2. Pin Assignments (1)
(54-Ball GRD or ZRD Package)
(1)
1
2
3
4
5
6
A
1Q1
NC
1OE
1CLK
NC
1D1
B
1Q3
1Q2
NC
NC
1D2
1D3
C
1Q5
1Q4
VCC
VCC
1D4
1D5
D
1Q7
1Q6
GND
GND
1D6
1D7
E
2Q1
1Q8
GND
GND
1D8
2D1
F
2Q3
2Q2
GND
GND
2D2
2D3
G
2Q5
2Q4
VCC
VCC
2D4
2D5
H
2Q7
2Q6
NC
NC
2D6
2D7
J
2Q8
NC
2OE
2CLK
NC
2D8
NC – No internal connection
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through each VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
6
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Data retention only
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.8
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
IOH
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–40
mA
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs (SCBA004).
7.4 Thermal Information
SN74LVC16374A
THERMAL METRIC (1)
DL
DGV
DGG
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
68.4
78.4
64.3
RθJC(top)
Junction-to-case (top) thermal resistance
34.7
30.7
17.6
RθJB
Junction-to-board thermal resistance
41.0
41.8
31.5
ψJT
Junction-to-top characterization parameter
12.3
3.8
1.1
ψJB
Junction-to-board characterization parameter
40.4
41.3
31.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V to 3.6 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
UNIT
V
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 μA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
IOL = 24 mA
V
±5
μA
Ioff
VI or VO = 5.5 V
0
±10
μA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
μA
II
VI = 0 to 5.5 V
VI = VCC or GND
ICC
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
ΔICC
(1)
(2)
MAX
VCC – 0.2
IOH = –4 mA
IOH = –12 mA
VOL
MIN TYP (1)
VCC
3.6 V
20
3.6 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
μA
20
2.7 V to 3.6 V
μA
500
Ci
VI = VCC or GND
3.3 V
5
pF
Co
VO = VCC or GND
3.3 V
6.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
MAX
MIN
MAX
150
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
150
MAX
MIN
150
UNIT
MAX
fclock
Clock frequency
tw
Pulse duration, CLK high or low
3.3
3.3
3.3
3.3
150
MHz
ns
tsu
Setup time, data before CLK↑
2.4
1.6
1.9
1.9
ns
th
Hold time, data after CLK↑
0.8
1
1.1
1.9
ns
7.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
VCC = 2.5 V
± 0.2 V
MIN MAX
MIN
150
150
MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN MAX
MIN MAX
150
150
UNIT
MHz
tpd
CLK
Q
1
6.5
1
4.3
1
4.9
1.5
4.5
ns
ten
OE
Q
1
6.7
1
4.7
1
5.3
1.5
4.6
ns
tdis
OE
Q
1
10.7
1
5
1
6.1
1.5
5.5
ns
1
ns
tsk(o)
8
VCC = 1.8 V
± 0.15 V
1
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7.8 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance
per flip-flop
Cpd
Outputs enabled
Outputs disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
47
52
58
21
23
24
f = 10 MHz
UNIT
pF
7.9 Typical Characteristics
3.5
5
3
4
TPD (ns)
TPD (ns)
2.5
2
1.5
3
2
1
1
0.5
TPD in ns
0
-100
TPD in ns
0
-50
0
50
Temperature (qC)
100
150
0
D001
Figure 1. TPD vs Temperature CLK to Q
1
2
VCC (V)
3
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D002
Figure 2. TPD vs VCC CLK to Q
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
VCC
VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
th
VI
VM
Input
VM
VI
VM
Data Input
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
VM
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VM
VM
0V
tPZL
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VI
Output
Control
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t PLZ and t PHZ are the same as t dis.
F. t PZL and t PZH are the same as t en.
G. t PLH and t PHL are the same as t pd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
This 16-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC16374A device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pull-up components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pull-up
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
9.2 Functional Block Diagram
1OE
2OE
1CLK
2CLK
C1
C1
1D1
1Q1
1D
1D
2D1
2Q1
To Seven Other Channels
To Seven Other Channels
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 3. Function Table
(Each Flip-Flop)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
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Product Folder Links: SN74LVC16374A
11
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
The SN74LVC16374A is a high-drive CMOS device that can be used for a multitude of bus interface type
applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V;
therefore, making it ideal for driving multiple outputs and good for high speed applications up to 150 MHz. The
inputs are 5.5-V tolerant allowing the device to translate down to VCC.
10.2 Typical Application
Regulated 3.3 V
OE
VCC
CLK
1D
1Q
µC
System Logic
µC or
8D
LEDs
8Q
System Logic
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads, so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended input conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified High and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend output conditions
– Load currents should not exceed 50 mA per output and 100 mA total for the part.
– Outputs should not be pulled above VCC.
12
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SN74LVC16374A
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SCAS728B – OCTOBER 2003 – REVISED SEPTEMBER 2014
Typical Application (continued)
10.2.3 Application Curves
300
250
ICC (V)
200
150
100
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
50
0
0
10
20
30
40
Frequency (MHz)
50
60
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF bypass capacitor is recommended. If there are multiple VCC pins, 0.01 μF or 0.022 μF is
recommended for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed
as close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified in Figure 6 are the rules that must be observed under all circumstances. All unused inputs of
digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that
should be applied to any particular unused input depends on the function of the device. Generally they will be
tied to GND or VCC; whichever makes more sense or is more convenient. It is generally acceptable to float
outputs unless the part is a transceiver.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
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13
SN74LVC16374A
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www.ti.com
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC16374ADGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16374A
SN74LVC16374ADGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LD374A
SN74LVC16374ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16374A
SN74LVC16374ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC16374A
SN74LVC16374AZQLR
NRND
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LD374A
SN74LVC16374AZRDR
NRND
BGA
MICROSTAR
JUNIOR
ZRD
54
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LD374A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
13.0
1.8
12.0
24.0
Q1
SN74LVC16374ADGGR
TSSOP
DGG
48
2000
330.0
24.4
SN74LVC16374ADGVR
TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
SN74LVC16374ADLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
SN74LVC16374AZQLR
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
SN74LVC16374AZRDR
BGA MI
CROSTA
R JUNI
OR
ZRD
54
1000
330.0
16.4
5.8
8.3
1.55
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC16374ADGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74LVC16374ADGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74LVC16374ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
SN74LVC16374AZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
350.0
350.0
43.0
SN74LVC16374AZRDR
BGA MICROSTAR
JUNIOR
ZRD
54
1000
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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