Texas Instruments | SNx4AHCT595 8-Bit Shift Registers With 3-State Output Registers (Rev. N) | Datasheet | Texas Instruments SNx4AHCT595 8-Bit Shift Registers With 3-State Output Registers (Rev. N) Datasheet

Texas Instruments SNx4AHCT595 8-Bit Shift Registers With 3-State Output Registers (Rev. N) Datasheet
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SN54AHCT595, SN74AHCT595
SCLS374N – MAY 1997 – REVISED JULY 2014
SNx4AHCT595 8-Bit Shift Registers With 3-State Output Registers
1 Features
3 Description
•
•
•
•
The SNx4AHCT595 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Both the shift register clock (SRCLK)
and storage register clock (RCLK) are positive-edge
triggered.
1
•
Inputs are TTL-Voltage Compatible
8-Bit Serial-In, Parallel-Out Shift
Shift Register Has Direct Clear
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
SNxAHCT595
2 Applications
•
•
•
•
•
Network Switches
Power Infrastructures
PCs ans Notebooks
LED Displays
Servers
PACKAGE
BODY SIZE (NOM)
PDIP (20)
24.33 mm 6.35 mm
SOP (20)
12.60 mm x 5.30 mm
SSOP (20)
7.50 mm x 5.30 mm
TVSOP (20)
5.00 mm x 4.40 mm
SOIC (20)
12.80 mm x 7.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
QA
QB
QC
9
QD
QE
QF
QG
QH
QH′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54AHCT595, SN74AHCT595
SCLS374N – MAY 1997 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
4
4
4
5
5
5
6
7
7
7
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Switching Characteristics ..........................................
Noise Characteristics ................................................
Operating Characteristics..........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 8
9
Detailed Description .............................................. 9
9.1
9.2
9.3
9.4
Overview ................................................................... 9
Functional Block Diagram ......................................... 9
Feature Description................................................. 10
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ................................................ 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (July 2014) to Revision N
•
Page
Changed Pin Functions table. ................................................................................................................................................ 3
Changes from Revision L (February 2004) to Revision M
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Changed MAX operating temperature from 85°C to 125°C in Recommended Operating Conditions table. ........................ 4
•
Added Typical Characteristics. ............................................................................................................................................... 7
•
Added Detailed Description section........................................................................................................................................ 9
•
Added Application and Implementation section.................................................................................................................... 11
2
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SCLS374N – MAY 1997 – REVISED JULY 2014
6 Pin Configuration and Functions
SN54AHCT595 . . . J OR W PACKAGE
SN74AHCT595 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
15
3
14
4
13
5
12
6
11
7
10
8
9
QD
QE
NC
QF
QG
NC
VCC
QA
QC
QB
VCC
QA
SER
OE
RCLK
SRCLK
SRCLR
QH′
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
SER
OE
NC
RCLK
SRCLK
SRCLR
16
2
QH
1
GND
NC
Q H′
QB
QC
QD
QE
QF
QG
QH
GND
SN54AHCT595 . . . FK PACKAGE
(TOP VIEW)
NC − No internal connection
Pin Functions
PIN
SN74AHCT595
NAME
D, DB, DGV,
N, NS, PW
SN54AHCT595
J, W
FK
I/O
DESCRIPTION
Ground Pin
GND
8
8
10
—
OE
13
13
17
I
Output Enable
QA
15
15
19
O
QA Output
QB
1
1
2
O
QB Output
QC
2
2
3
O
QC Output
QD
3
3
4
O
QD Output
QE
4
4
5
O
QE Output
QF
5
5
7
O
QF Output
QG
6
6
8
O
QG Output
QH
7
7
9
O
QH Output
QH'
9
9
12
O
QH' Output
RCLK
12
12
14
I
RCLK Input
SER
14
14
18
I
SER Input
SRCLK
11
11
14
I
SRCLK Input
SRCLR
10
10
13
I
SRCLR Input
1
NC
—
6
11
—
No Connection
—
Power Pin
16
VCC
16
16
20
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SCLS374N – MAY 1997 – REVISED JULY 2014
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHCT595 (2)
SN74AHCT595
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
0
5.5
VO
Output voltage
0
VCC
IOH
High-level output current
–8
–8
IOL
Low-level output current
8
8
mA
∆t/∆v
Input transition rise and fall time
20
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
(2)
4
2
2
0.8
–55
125
V
V
0.8
V
0
5.5
V
0
VCC
V
–40
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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7.4 Thermal Information
SN74AHCT595
THERMAL METRIC (1)
D
DB
N
NS
PW
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
80.2
97.5
47.5
79.1
105.7
RθJC(top)
Junction-to-case (top) thermal resistance
39.1
47.7
34.9
35.4
40.4
RθJB
Junction-to-board thermal resistance
27.7
48.1
27.5
39.9
50.7
ψJT
Junction-to-top characterization parameter
9.9
9.8
19.8
5.4
3.7
ψJB
Junction-to-board characterization parameter
37.4
47.6
27.4
39.5
50.1
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
VCC
IOH = –50 mA
4.5 V
IOH = –8 mA
IOL = 50 µA
MIN
TYP
4.4
4.5
MAX
MIN
3.94
MAX
MIN
4.4
4.4
3.8
3.8
MAX
UNIT
V
0.1
0.1
0.1
0.36
0.44
0.44
0 to 5.5
V
±0.1
±1 (2)
±1
µA
4.5 V
IOL = 8 mA
SN54AHCT595 (1) SN74AHCT595
TA = 25°C
V
II
VI = 5.5 V or GND
IOZ
VO = VCC or GND
QA – QH
5.5 V
±0.25
±2.5
±2.5
µA
ICC
VI = VCC or GND
IO = 0
5.5 V
4
40
40
µA
One input at 3.4V,
Other inputs at VCC or GND
5.5 V
2
2.2
2.2
mA
10
pF
ΔICC (3)
(1)
(2)
(3)
TEST CONDITIONS
Ci
VI = VCC or GND
5V
3
Co
VO = VCC or GND
5V
5.5
10
pF
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
7.6 Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
TA = 25°C
PARAMETER
tw
Pulse duration
MIN
Setup time
(1)
(2)
Hold time
MIN
MAX
SN74AHCT595
MIN
5
5.5
5.5
RCLK high or low
5
5.5
5.5
SRCLR low
5
5
5
3
3
3
5
5
5
5
5
5
3.4
3.8
3.8
2
2
2
SRCLK↑ before RCLK↑
(2)
SRCLR low before RCLK↑
SRCLR high (inactive) before SRCLK↑
th
MAX
SRCLK high or low
SER before SRCLK↑
tsu
SN54AHCT595 (1)
SER after SRCLK↑
MAX
UNIT
ns
ns
ns
Product Preview
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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SRCLK
SER
RCLK
SRCLR
OE
QA
QB
QC
QD
QE
QF
QG
QH
QH’
NOTE:
implies that the output is in 3-State mode.
Figure 1. Timing Diagram
7.7 Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 3)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPLH
tPHL
tPLH
tPHL
tPHL
tPZH
tPZL
tPHZ
tPLZ
(1)
(2)
6
LOAD
CAPACITANCE
SN54AHCT595 (1)
TA = 25°C
MIN
TYP
CL = 15 pF
135 (2)
170 (2)
115 (2)
115
CL = 50 pF
95
140
85
85
RCLK
QA – QH
CL = 15 pF
SRCLK
QH’
CL = 15 pF
SRCLR
QH’
CL = 15 pF
OE
QA – QH
CL = 15 pF
RCLK
QA – QH
CL = 50 pF
SRCLK
QH’
CL = 50 pF
SRCLR
QH’
CL = 50 pF
OE
QA – QH
CL = 50 pF
OE
QA – QH
CL = 50 pF
MAX
MIN
MAX
SN74AHCT595
MIN
MAX
MHz
4.3 (2)
7.4 (2)
1 (2)
8.5 (2)
1
8.5
(2)
(2)
(2)
8.5 (2)
1
8.5
4.3
7.4
1
4.5 (2)
8.2 (2)
1 (2)
9.4 (2)
1
9.4
4.5 (2)
8.2 (2)
1 (2)
9.4 (2)
1
9.4
4.5 (2)
8 (2)
1 (2)
9.1 (2)
1
9.1
(2)
(2)
(2)
10 (2)
1
10
4.3
8.6
1
UNIT
5.4 (2)
8.6 (2)
1 (2)
10 (2)
1
10
5.6
9.4
1
10.5
1
10.5
5.6
9.4
1
10.5
1
10.5
6.4
10.2
1
11.4
1
11.4
6.4
10.2
1
11.4
1
11.4
6.4
10
1
11.1
1
11.1
5.7
10.6
1
12
1
12
6.8
10.6
1
12
1
12
3.5
10.3
1
11
1
11
3.4
10.3
1
11
1
11
ns
ns
ns
ns
ns
ns
ns
ns
ns
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On products compliant to MIL-PRF-38535, this parameter is not production tested.
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7.8 Noise Characteristics (1)
VCC = 5 V, CL = 50 pF, TA = 25°C
SN74AHCT595
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
1
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.6
V
VOH(V)
Quiet output, minimum dynamic VOH
3.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2
V
0.8
V
TYP
UNIT
112
pF
Characteristics are for surface-mount packages only.
7.9 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
f = 1 MHz
7.10 Typical Characteristics
7
6
TPD (ns)
5
4
3
2
1
TPD in ns
0
-100
-50
0
50
Temperature (qC)
100
150
D001
Figure 2. SN74AHCT595 TPD vs Temperature, 15 pF Load
RCLK to Q
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8 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH – 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, t f ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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9 Detailed Description
9.1 Overview
The SNx4AHCT595 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. The storage register has parallel 3-state outputs. Separate clocks are provided for the shift and storage
registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial outputs for
cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. Both the shift
register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are
connected together, the shift register always is one clock pulse ahead of the storage register.
9.2 Functional Block Diagram
OE
RCLK
SRCLR
SRCLK
SER
13
12
10
11
14
1D Q
C1
R
3D
C3 Q
15
2D Q
C2
R
3D
C3 Q
1
2D Q
C2
R
3D
C3 Q
2
2D Q
C2
R
3D
C3 Q
3
2D Q
C2
R
3D
C3 Q
4
2D Q
C2
R
3D
C3 Q
5
2D Q
C2
R
3D
C3 Q
6
2D Q
C2
R
3D
C3 Q
7
QA
QB
QC
9
QD
QE
QF
QG
QH
QH′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
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9.3 Feature Description
•
•
•
Inputs are TTL-voltage compatible
Slow edges for reduced noise
Low power
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
10
FUNCTION
SER
SRCLK
SRCLR
RCLK
OE
X
X
X
X
H
Outputs QA – QH are disabled.
X
X
X
X
L
Outputs QA – QH are enabled.
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
X
X
X
↑
X
Shift-register data is stored in the storage register.
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SCLS374N – MAY 1997 – REVISED JULY 2014
10 Application and Implementation
10.1 Application Information
The SNx4AHCT595 is a low-drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and
undershoot on the outputs. The input switching levels have been lowered to accommodate TTL inputs of 0.8-V
VIL and 2-V VIH. This feature makes it ideal for translating up from 3.3 V to 5 V. Figure 4 shows this type of
translation.
13
8
SRCLR
R3
270
LED3
RCLK
R4
270
GND
2
OC
OE
OF
OE
LED4
R5
270
LED5
R6
270
LED6
R7
270
LED7
R8
270
LED8
1
OG
3
4
5
6
7
9
OH*
SN74AHCT595
VCC
GND
GND
LED2
GND
270
OB
OH
1K
R9
SRCLK
OD
12
µC
R2
GND
15
GND
VCC
GND
VCC
10
LED1
16
SER
OA
11
270
GND
IC1
14
R1
GND
VCC
GND
10.2 Typical Application
Figure 4. Specific Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
• Recommended input conditions
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Specified high and low levels. See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
• Recommend output conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part
– Outputs should not be pulled above VCC
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT595 SN74AHCT595
Submit Documentation Feedback
11
SN54AHCT595, SN74AHCT595
SCLS374N – MAY 1997 – REVISED JULY 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
Output
Input
Figure 5. Typical Application Curve
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
Submit Documentation Feedback
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT595 SN74AHCT595
SN54AHCT595, SN74AHCT595
www.ti.com
SCLS374N – MAY 1997 – REVISED JULY 2014
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHCT595
Click here
Click here
Click here
Click here
Click here
SN74AHCT595
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1997–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHCT595 SN74AHCT595
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHCT595D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT595
SN74AHCT595DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB595
SN74AHCT595DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT595
SN74AHCT595DRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AHCT595
SN74AHCT595N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHCT595N
SN74AHCT595NE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
SN74AHCT595N
SN74AHCT595PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB595
SN74AHCT595PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HB595
SN74AHCT595PWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
HB595
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHCT595DR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AHCT595PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHCT595PWRG3
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHCT595DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AHCT595PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74AHCT595PWRG3
TSSOP
PW
16
2000
364.0
364.0
27.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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• DALLAS, TEXAS 75265
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