Texas Instruments | SN74AUP1G04 Low-Power Single Inverter Gate (Rev. K) | Datasheet | Texas Instruments SN74AUP1G04 Low-Power Single Inverter Gate (Rev. K) Datasheet

Texas Instruments SN74AUP1G04 Low-Power Single Inverter Gate (Rev. K) Datasheet
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SN74AUP1G04
SCES571K – JUNE 2004 – REVISED JUNE 2014
SN74AUP1G04 Low-Power Single Inverter Gate
1 Features
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2 Applications
2
Available in the Ultra Small 0.64 mm Package
(DPW) with 0.5-mm Pitch
Low Static-Power Consumption
(ICC = 0.9 μA Max)
Low Dynamic-Power Consumption
(Cpd = 4.1 pF Typ at 3.3 V)
Low Input Capacitance (Ci = 1.5 pF Typ)
Low Noise − Overshoot and Undershoot
<10% of VCC
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Input Hysteresis Allows Slow Input Transition and
Better Switching Noise Immunity at the Input
(Vhys = 250 mV Typ at 3.3 V)
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode Signal
Operation
tpd = 3.9 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
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ATCA Solutions
Active Noise Cancellation (ANC)
Barcode Scanner
Blood Pressure Monitor
CPAP Machine
Cable Solutions
DLP 3D Machine Vision, Hyperspectral Imaging,
Optical Networking, and Spectroscopy
E-Book
Embedded PC
Field Transmitter: Temperature or Pressure
Sensor
Fingerprint Biometrics
HVAC: Heating, Ventilating, and Air Conditioning
Network-Attached Storage (NAS)
Server Motherboard and PSU
Software Defined Radio (SDR)
TV: High-Definition (HDTV), LCD, and Digital
Video Communications System
Wireless Data Access Card, Headset, Keyboard,
Mouse, and LAN Card
X-ray: Baggage Scanner, Medical, and Dental
3 Description
The SN74AUP1G04 device is a single inverter gate
performs the Boolean function Y = A.
Device Information(1)
PART NUMBER
PACKAGE
SN74AUP1G04
BODY SIZE (NOM)
SOT-23 (5)
2.90 mm × 1.60 mm
SOT (5)
2.00 mm × 1.25 mm
SOT (5)
1.60 mm × 1.20 mm
USON (6)
1.45 mm × 1.00 mm
X2SON (4)
0.80 mm × 0.80 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74AUP1G04
SCES571K – JUNE 2004 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
4
4
5
5
6
6
7
7
7
7
8
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics, CL = 5 pF ........................
Switching Characteristics, CL = 10 pF ......................
Switching Characteristics, CL = 15 pF ......................
Switching Characteristics, CL = 30 pF ......................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information .................. 9
8.1 Propagation Delays, Setup and Hold Times, and
8.2
9
Pulse Width................................................................ 9
Enable and Disable Times ..................................... 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 14
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 15
13.1 Trademarks ........................................................... 15
13.2 Electrostatic Discharge Caution ............................ 15
13.3 Glossary ................................................................ 15
14 Mechanical, Packaging, and Orderable
Information ........................................................... 15
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision J (May 2014) to Revision K
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Updated Ioff in Features. ........................................................................................................................................................ 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics. ............................................................................................................................................... 8
2
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6 Pin Configuration and Functions
N.C.
A
2
GND
3
N.C.
1
A
2
GND
3
VCC
5
1
4
VCC
N.C.
1
A
2
GND
3
5
VCC
4
Y
Y
6
VCC
A
2
5
N.C.
GND
3
4
Y
YFP PACKAGE
(TOP VIEW)
DSF PACKAGE
(TOP VIEW)
DRY PACKAGE
(TOP VIEW)
1
5
Y
4
N.C.
DRL PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DBV PACKAGE
(TOP VIEW)
N.C.
1
6
A
2
5
N.C.
GND
3
4
Y
VCC
A
GND
A1
1
4
A2
B1
2
3
B2
VCC
Y
DPW PACKAGE
(TOP VIEW)
N.C. – No internal connection.
DNU – Do not use
GND
See mechancial drawings for dimensions.
N.C. 1
5
3
A
2
4
VCC
Y
Pin Functions
PIN
NAME
DBV, DCK,
DRL
DSF, DRY
NC
1
A
2
GND
Y
VCC
I/O
DESCRIPTION
1
—
No Connection
2
I
B1
3
—
Ground Pin
B2
4
O
Output Y
A2
5
—
Power Pin
YFP
DPW
1, 5
—
2
A1
3
3
4
4
5
6
Input A
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
UNIT
V
(2)
VI
Input voltage range
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
0.8
3.6
Supply voltage
VCC = 0.8 V
VIH
0.65 × VCC
VCC = 2.3 V to 2.7 V
V
1.6
VCC = 3 V to 3.6 V
2
VCC = 0.8 V
VIL
Low-level input voltage
VI
Input voltage
VO
Output voltage
0
VCC = 1.1 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
High-level output current
0.9
0
3.6
0
Low-level output current
VCC
V
–20
μA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
V
VCC = 0.8 V
VCC = 3 V
IOL
V
0.7
VCC = 3 V to 3.6 V
IOH
V
VCC
VCC = 1.1 V to 1.95 V
High-level input voltage
UNIT
μA
mA
4
VCC = 0.8 V to 3.6 V
200
ns/V
85
°C
–40
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
THERMAL METRIC (1)
DBV
DCK
DPW
DRL
DRY
DSF
5 PINS
5 PINS
5 PINS
5 PINS
6 PINS
6 PINS
RθJA
Junction-to-ambient thermal
resistance
298.6
314.4
291.8
349.7
554.9
407.1
RθJC(top)
Junction-to-case (top) thermal
resistance
240.2
128.7
224.2
120.5
385.4
232.0
RθJB
Junction-to-board thermal
resistance
134.6
100.6
245.8
171.4
388.2
306.9
ψJT
Junction-to-top characterization
parameter
114.5
7.1
31.4
10.8
159.0
40.3
ψJB
Junction-to-board characterization
parameter
133.9
99.8
245.6
169.4
384.1
306.0
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
195.4
n/a
n/a
n/a
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
TA = 25°C
MIN
TA = –40°C to 85°C
TYP
MAX
MIN
IOH = –20 μA
0.8 V to 3.6 V
VCC – 0.1
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –2.3 mA
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
VOL
VCC
IOL = 20 μA
0.8 V to 3.6 V
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
IOL = 2.3 mA
2.6
IOL = 2.7 mA
2.55
0.1
1.1 V
0.3 × VCC
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
3V
IOL = 4 mA
V
0.1
2.3 V
IOL = 3.1 mA
UNIT
MAX
V
0 V to 3.6 V
0.1
0.5
μA
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
μA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
μA
ICC
VI = GND or IO = 0
(VCC to 3.6 V)
0.8 V to 3.6 V
0.5
0.9
μA
ΔICC
VI = VCC – 0.6 V, IO = 0
40
50
μA
II
A input
VI = GND to 3.6 V
CI
VI = VCC or GND
Co
VO = VCC or GND
3.3 V
0V
1.5
3.6 V
1.5
3.6 V
2.5
pF
pF
7.6 Switching Characteristics, CL = 5 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
6
A
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
UNIT
MAX
MIN
MAX
15.6
1.2 V ± 0.1 V
3.3
5.9
10.8
2.1
13.5
1.5 V ± 0.1 V
2.5
4.2
7
1.6
8.8
1.8 V ± 0.15 V
2.2
3.4
5.9
1.4
7
2.5 V ± 0.2 V
1.7
2.5
4
1.3
4.9
3.3 V ± 0.3 V
1.4
2.1
3.2
1.2
3.9
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7.7 Switching Characteristics, CL = 10 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
UNIT
MAX
17.7
1.2 V ± 0.1 V
3.9
6.9
12.2
3.1
15
1.5 V ± 0.1 V
3
5
8.1
2.5
9.9
1.8 V ± 0.15 V
2.6
4
6.9
2.1
7.9
2.5 V ± 0.2 V
2.1
3
4.6
1.7
5.6
3.3 V ± 0.3 V
1.8
2.5
3.8
1.5
4.5
ns
7.8 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
UNIT
MAX
MIN
MAX
19.5
1.2 V ± 0.1 V
4.7
7.8
13
3.8
15.9
1.5 V ± 0.1 V
3.7
5.6
8.6
3.1
10.6
1.8 V ± 0.15 V
3.2
4.6
7.4
2.6
8.5
2.5 V ± 0.2 V
2.5
3.5
5.1
2.1
6.1
3.3 V ± 0.3 V
2.2
2.9
4.2
1.9
5
ns
7.9 Switching Characteristics, CL = 30 pF
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC
MIN
0.8 V
tpd
A
Y
TA = –40°C
to 85°C
TA = 25°C
TYP
MAX
MIN
UNIT
MAX
25.4
1.2 V ± 0.1 V
6.8
10.4
16
6.1
19
1.5 V ± 0.1 V
5.3
7.6
10.8
4.8
12.9
1.8 V ± 0.15 V
4.6
6.3
9.2
4.1
10.5
2.5 V ± 0.2 V
3.6
4.8
6.5
3.3
7.6
3.3 V ± 0.3 V
3.2
4
5.4
2.9
6.2
ns
7.10 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
VCC
TYP
0.8 V
3.9
1.2 V ± 0.1 V
3.9
1.5 V ± 0.1 V
3.9
1.8 V ± 0.15 V
3.9
2.5 V ± 0.2 V
3.9
3.3 V ± 0.3 V
4.1
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UNIT
pF
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7.11 Typical Characteristics
18
4.5
16
4
14
3.5
12
3
TPD (ns)
TPD (ns)
TPD in ns
10
8
2.5
2
6
1.5
4
1
2
0.5
TPD in ns
0
0
1
2
VCC (V)
Figure 1. TPD vs VCC
8
3
4
0
-50
0
D001
50
Temperature (qC)
100
150
D002
Figure 2. TPD vs Temperature at 1.8 V
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8 Parameter Measurement Information
8.1 Propagation Delays, Setup and Hold Times, and Pulse Width
From Output
Under Test
CL
(see Note A)
1 MW
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
VM
Output
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
E.
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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8.2
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Enable and Disable Times
2 ´ VCC
5 kW
From Output
Under Test
S1
GND
CL
(see Note A)
5 kW
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 ´ VCC
GND
LOAD CIRCUIT
CL
VM
VI
VD
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 ´ VCC
(see Note B)
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + VD
VOL
tPHZ
VCC/2
VOH - VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
The SN74AUP1G04 device is a single inverter gate performs the Boolean function Y = A.
The AUP family of devices has quiescent power consumption less than 1 µA and comes in the ultra small DPW
package. The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square
footprint saves significant board space over other package options while still retaining the traditional
manufacturing friendly lead pitch of 0.5 mm.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. The Ioff feature also allows
for live insertion.
9.2 Functional Block Diagram
A
Y
9.3 Feature Description
•
•
•
•
•
Wide operating VCC range of 0.8 V to 3.6 V
3.6-V I/O tolerant to support down translation
Input hysteresis allows slow input transition and better switching noise immunity at the input
Ioff feature allows voltages on the inputs and outputs when VCC is 0 V
Low noise due to slower edge rates
9.4 Device Functional Modes
Table 1. Function Table
INPUT
A
INPUT
B
H
L
L
H
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11
SN74AUP1G04
SCES571K – JUNE 2004 – REVISED JUNE 2014
www.ti.com
10 Application and Implementation
10.1 Application Information
The AUP family is TI's premier solution to the industry’s low-power needs in battery-powered portable
applications. This family ensures a very low static and dynamic power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity. It
has a small amount of hysteresis built in allowing for slower or noisy input signals. The lowered drive produces
slower edges and prevents overshoot and undershoot on the outputs.
10.2 Typical Application
3.3 V Bus Driver
VCC
1 V regulated
0.1 µF
1 V Micro Processor
Driver
µC
Figure 5. Typical Application Schematic
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits.
10.2.2 Detailed Design Procedure
1. Recommended Input conditions
– Rise time and fall time specs. See (Δt/ΔV) in Recommended Operating Conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions
– Inputs are overvoltage tolerant allowing them to go as high as 3.6 V at any valid VCC
2. Recommend output conditions
– Load currents should not exceed 20 mA on the output and 50 mA total for the part
– Outputs should not be pulled above VCC
12
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SN74AUP1G04
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SCES571K – JUNE 2004 – REVISED JUNE 2014
Typical Application (continued)
10.2.3 Application Curves
Switching Characteristics
at 25 MHz†
3.5
Voltage − V
3
2.5
Input
2
1.5
1
Output
0.5
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 6. AUP – The Lowest-Power Family
Figure 7. Excellent Signal Integrity
The AUP family of single gate logic makes excellent translators for the new lower voltage microprocessors that
typically are powered from 0.8 V to 1.2 V. They can drop the voltage of peripheral drivers and accessories that
are still powered by 3.3 V to the new uC power levels.
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13
SN74AUP1G04
SCES571K – JUNE 2004 – REVISED JUNE 2014
www.ti.com
11 Power Supply Recommendations
The power supply can be any voltage between the Min and Max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 8 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Unused Input
Output
Input
Figure 8. Layout Diagram
14
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SN74AUP1G04
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SCES571K – JUNE 2004 – REVISED JUNE 2014
13 Device and Documentation Support
13.1 Trademarks
The Ioff feature also allows for live insertion. is a trademark of others.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: SN74AUP1G04
15
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AUP1G04DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(H04F, H04R)
SN74AUP1G04DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(H04F, H04R)
SN74AUP1G04DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HC5, HCF, HCK, HC
R)
SN74AUP1G04DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HC5, HCF, HCK, HC
R)
SN74AUP1G04DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HC5, HCF, HCK, HC
R)
SN74AUP1G04DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HC5, HCF, HCR)
SN74AUP1G04DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
(HC5, HCF, HCR)
SN74AUP1G04DPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
C4
SN74AUP1G04DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
(HC7, HCR)
SN74AUP1G04DRY2
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC
SN74AUP1G04DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
HC
SN74AUP1G04DSF2
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HC
SN74AUP1G04DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
HC
SN74AUP1G04YFPR
ACTIVE
DSBGA
YFP
4
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
HC
N
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Nov-2018
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74AUP1G04DBVR
SOT-23
DBV
5
3000
178.0
9.0
SN74AUP1G04DBVR
SOT-23
DBV
5
3000
180.0
SN74AUP1G04DBVT
SOT-23
DBV
5
250
180.0
SN74AUP1G04DBVT
SOT-23
DBV
5
250
SN74AUP1G04DCKR
SC70
DCK
5
SN74AUP1G04DCKR
SC70
DCK
SN74AUP1G04DCKT
SC70
DCK
SN74AUP1G04DCKT
SC70
SN74AUP1G04DPWR
SN74AUP1G04DRLR
SN74AUP1G04DRLR
W
Pin1
(mm) Quadrant
3.23
3.17
1.37
4.0
8.0
Q3
8.4
3.23
3.17
1.37
4.0
8.0
Q3
8.4
3.23
3.17
1.37
4.0
8.0
Q3
178.0
8.4
3.3
3.2
1.4
4.0
8.0
Q3
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q3
SOT-5X3
DRL
5
4000
180.0
9.5
1.78
1.78
0.69
4.0
8.0
Q3
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
SN74AUP1G04DRY2
SON
DRY
6
5000
180.0
9.5
1.6
1.15
0.75
4.0
8.0
Q3
SN74AUP1G04DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
SN74AUP1G04DSF2
SON
DSF
6
5000
180.0
8.4
1.16
1.16
0.63
4.0
8.0
Q3
SN74AUP1G04DSF2
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q3
SN74AUP1G04DSFR
SON
DSF
6
5000
180.0
8.4
1.16
1.16
0.63
4.0
8.0
Q2
SN74AUP1G04YFPR
DSBGA
YFP
4
3000
178.0
9.2
0.89
0.89
0.58
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Nov-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G04DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74AUP1G04DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74AUP1G04DBVT
SOT-23
DBV
5
250
202.0
201.0
28.0
SN74AUP1G04DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74AUP1G04DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74AUP1G04DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74AUP1G04DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AUP1G04DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74AUP1G04DPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
SN74AUP1G04DRLR
SOT-5X3
DRL
5
4000
184.0
184.0
19.0
SN74AUP1G04DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
SN74AUP1G04DRY2
SON
DRY
6
5000
184.0
184.0
19.0
SN74AUP1G04DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74AUP1G04DSF2
SON
DSF
6
5000
202.0
201.0
28.0
SN74AUP1G04DSF2
SON
DSF
6
5000
184.0
184.0
19.0
SN74AUP1G04DSFR
SON
DSF
6
5000
202.0
201.0
28.0
SN74AUP1G04YFPR
DSBGA
YFP
4
3000
220.0
220.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YFP0004
DSBGA - 0.5 mm max height
SCALE 10.000
DIE SIZE BALL GRID ARRAY
B
E
A
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.13
BALL TYP
0.05 C
0.4
TYP
B
D: Max = 0.79 mm, Min = 0.73 mm
SYMM
0.4
TYP
E: Max = 0.79 mm, Min = 0.73 mm
A
4X
0.015
0.25
0.21
C A B
1
2
SYMM
4223507/A 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YFP0004
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
4X ( 0.23)
2
1
A
SYMM
(0.4) TYP
B
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:50X
( 0.23)
METAL
SOLDER MASK
OPENING
0.05 MAX
EXPOSED
METAL
0.05 MIN
METAL UNDER
SOLDER MASK
EXPOSED
METAL
( 0.23)
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223507/A 01/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YFP0004
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.4) TYP
(R0.05) TYP
4X ( 0.25)
1
2
A
SYMM
(0.4) TYP
B
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:50X
4223507/A 01/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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