Texas Instruments | SN74LVC162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. B) | Datasheet | Texas Instruments SN74LVC162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. B) Datasheet

Texas Instruments SN74LVC162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. B) Datasheet
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SN74LVC162244A
SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
SN74LVC162244A 16-Bit Buffer/Driver with 3-State Outputs
1 Features
2 Applications
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Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.4 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
Supports Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Output Ports Have Equivalent 26 Ω Series
Resistors, So No External Resistors Are Required
Ioff Supports Live Insertion, Partial Power Down
Mode, and Back Drive Protection
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
Motor drive
Network switch
Power Infrastructure
Test and Measurement
3 Description
This 16-bit buffer or driver is designed for 1.65-V to
3.6-V VCC operation. The device can be used as four
4-bit buffers, two 8-bit buffers, or one 16-bit buffer.
Device Information(1)
PART NUMBER
SN74LVC162244A
PACKAGE
BODY SIZE (NOM)
SSOP (48)
15.88 × 7.49 mm
TSSOP (48)
12.50 × 6.10 mm
TVSOP (48)
9.70 × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC162244A
SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
6
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
6
6
7
7
8
8
8
9
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information ................ 10
Detailed Description ............................................ 11
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
11
12
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 14
12.1 Layout Guidelines ................................................. 14
12.2 Layout Example .................................................... 14
13 Device and Documentation Support ................. 14
13.1 Trademarks ........................................................... 14
13.2 Electrostatic Discharge Caution ............................ 14
13.3 Glossary ................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (October 2005) to Revision B
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Changed MAX ambient temperature to 125°C. ..................................................................................................................... 7
•
Added Device and Documentation Support section............................................................................................................. 14
•
Added ESD warning. ............................................................................................................................................................ 14
•
Added Mechanical, Packaging, and Orderable Information section..................................................................................... 14
2
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SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
6 Pin Configuration and Functions
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
1OE
1
I
Output Enable 1 (input)
1Y1
2
O
1Y1 Output
1Y2
3
O
1Y2 Output
GND
4
–
Ground pin
1Y3
5
O
1Y3 Output
1Y4
6
O
1Y4 Output
VCC
7
–
Power pin
2Y1
8
O
2Y1 Output
2Y2
9
O
2Y2 Output
GND
10
–
Ground pin
2Y3
11
O
2Y3 Output
2Y4
12
O
2Y4 Output
3Y1
13
O
3Y1 Output
3Y2
14
O
3Y2 Output
GND
15
–
Ground pin
3Y3
16
O
3Y3 Output
3Y4
17
O
3Y4 Output
VCC
18
–
Power pin
4Y1
19
O
4Y1 Output
4Y2
20
O
4Y2 Output
GND
21
–
Ground pin
4Y3
22
O
4Y3 Output
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
4Y4
23
O
4Y4 Output
4OE
24
I
Output Enable 4 (input)
3OE
25
I
Output Enable 3 (input)
4A4
26
I
4A4 Input
4A3
27
I
4A3 Input
GND
28
–
Ground pin
4A2
29
I
4A2 Input
4A1
30
I
4A1 Input
VCC
31
–
Power pin
3A4
32
I
3A4 Input
3A3
33
I
3A3 Input
GND
34
–
Ground pin
3A2
35
I
3A2 Input
3A1
36
I
3A1 Input
2A4
37
I
2A4 Input
2A3
38
I
2A3 Input
GND
39
–
Ground pin
2A2
40
I
2A2 Input
2A1
41
I
2A1 Input
VCC
42
–
Power pin
1A4
43
I
1A4 Input
1A3
44
I
1A3 Input
GND
45
–
Ground pin
1A2
46
I
1A2 Input
1A1
47
I
1A1 Input
2OE
48
I
Output Enable 2 (Input)
4
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SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
Table 1. 3Pin Assignments (1)
(56-Ball GQL or ZQL Package)
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
VCC
VCC
1A3
1A4
D
2Y2
2Y1
GND
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
VCC
4A2
4A1
J
4Y3
4Y4
GND
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
(1)
NC - No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
2
3
4
5
6
1
A
B
C
D
E
F
G
H
J
Table 2. Pin Assignments (1)
(54-Ball GRD or ZRD Package)
(1)
1
2
3
4
5
6
A
1Y1
NC
1OE
2OE
NC
1A1
B
1Y3
1Y2
NC
NC
1A2
1A3
C
2Y1
1Y4
VCC
VCC
1A4
2A1
D
2Y3
2Y2
GND
GND
2A2
2A3
E
3Y1
2Y4
GND
GND
2A4
3A1
F
3Y3
3Y2
GND
GND
3A2
3A3
G
4Y1
3Y4
VCC
VCC
3A4
4A1
H
4Y3
4Y2
NC
NC
4A2
4A3
J
4Y4
NC
4OE
3OE
NC
4A4
NC - No internal connection
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
MIN
Tstg
Storage temperature range
V(ESD)
(1)
(2)
6
Electrostatic discharge
MAX
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
UNIT
°C
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
Data retention only
MIN
MAX
1.65
3.6
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
IOH
High-level output current
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
5.5
High or low state
0
VCC
High-impedance state
0
5.5
VCC = 1.65 V
–2
VCC = 2.3 V
–4
VCC = 2.7 V
–8
V
V
mA
–12
VCC = 1.65 V
2
VCC = 2.3 V
4
VCC = 2.7 V
8
VCC = 3 V
(1)
V
0.8
0
VCC = 3 V
IOL
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
12
–40
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
THERMAL METRIC (1)
DGG
DGV
DL
48 PINS
48 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
64.3
78.4
68.4
RθJC(top)
Junction-to-case (top) thermal resistance
17.6
30.7
34.7
RθJB
Junction-to-board thermal resistance
31.5
41.8
41.0
ψJT
Junction-to-top characterization parameter
1.1
3.8
12.3
ψJB
Junction-to-board characterization parameter
31.2
41.3
40.4
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
1.65 V to 3.6 V
IOH = –2 mA
VOH
II
VCC – 0.2
1.2
2.3 V
1.7
2.7 V
2.2
IOH = –6 mA
3V
2.4
IOH = –8 mA
2.7 V
2
IOH = –12 mA
3V
2
IOL = 100 µA
1.65 V to 3.6 V
0.2
1.65 V
0.45
2.3 V
0.7
IOH = –4 mA
IOL = 4 mA
V
2.7 V
0.4
IOL = 6 mA
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
V
3.6 V
±5
µA
VI or VO = 5.5 V
0
±10
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
µA
ΔICC
VI = 0 to 5.5 V
UNIT
Ioff
ICC
(1)
(2)
TYP (1) MAX
1.65 V
IOL = 2 mA
VOL
MIN
VI = VCC or GND
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
One input at VCC – 0.6 V,
20
3.6 V
Other inputs at VCC or GND
20
2.7 V to 3.6 V
500
µA
µA
Ci
VI = VCC or GND
3.3 V
5.5
pF
Co
VO = VCC or GND
3.3 V
6
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
PARAMETER
VCC = 1.8 V
± 0.15 V
MIN
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.5
6
1
4.3
1
5.6
1.1
4.4
ns
1.5
7.3
1
5
1
6.9
1
5.5
ns
1.5
8.9
1
5.5
1
6.8
1.8
6.3
ns
7.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
8
Power dissipation capacitance
per buffer/driver
Outputs enabled
Outputs disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
31
33
35
2
3
4
f = 10 MHz
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UNIT
pF
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7.8 Typical Characteristics
4
4
TPD
3.5
3.5
3
3
2.5
2.5
TPD (ns)
TPD (ns)
TPD
2
2
1.5
1.5
1
1
0.5
0.5
0
0
1
2
3
VCC (V)
4
0
-100
-50
D001
Figure 1. TPD Across VCC at 25°C
0
50
Temperature (°C)
100
150
D005
Figure 2. TPD Across Temperature at 3.3 V
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
10
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9 Detailed Description
9.1 Overview
This 16-bit buffer/driver is designed for 1.65-V to 3.6-V VCC operation. The SN74LVC162244A is designed
specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and busoriented receivers and transmitters. The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit
buffer. It provides true outputs and symmetrical active-low output-enable (OE) inputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment. The outputs, which are designed to sink up to 12 mA, include equivalent
26-Ω resistors to reduce overshoot and undershoot. Inputs can be driven from either 3.3-V or 5-V devices. This
feature allows the use of this device as a translator in a mixed 3.3-V/5-V system environment. This device is fully
specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered down. To ensure the high-impedance state
during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the
resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG, DGV, and DL packages.
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
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11
SN74LVC162244A
SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
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9.4 Device Functional Modes
Table 3. Function Table
(Each 4-Bit Buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
10 Application and Implementation
10.1 Application Information
The SN74LVC162244A is a 16 bit buffer driver. This device can be used as four 4-bit, two 8-bit, or one 16-bit
buffer. It allows data transmission from the A bus to the Y bus with 4 separate enable pins that control 4 bits
each. The output-enable (OE) input can be used to disable sections of the device so the buses are effectively
isolated. The device has 5.5 V tolerant inputs at any valid VCC which allows it to be used in multi-power systems
and can be used for down translation.
10.2 Typical Application
Regulated 3.6 V
uC or
System Logic
OE
Vcc
A1
Y1
A4
uC
System Logic
LEDs
Y4
GND
Figure 4. Typical Application Schematic
12
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SN74LVC162244A
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SCAS758B – DECEMBER 2003 – REVISED JUNE 2014
Typical Application (continued)
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
10.2.3 Application Curves
300
250
ICC - mA
200
150
100
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
50
0
0
10
20
30
40
Frequency - MHz
50
60
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
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12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC whichever make more sense or is more convenient. It is generally OK to float outputs unless the
part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when
asserted. This will not disable the input section of the IOs, so they also cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
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Product Folder Links: SN74LVC162244A
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVC162244ADGGRG4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC162244A
SN74LVC162244ADGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC162244A
SN74LVC162244ADGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LD2244A
SN74LVC162244ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC162244A
SN74LVC162244ADLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC162244A
SN74LVC162244ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC162244A
SN74LVC162244AZQLR
NRND
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
LD2244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
13.0
1.8
12.0
24.0
Q1
SN74LVC162244ADGGR TSSOP
DGG
48
2000
330.0
24.4
SN74LVC162244ADGVR TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
SN74LVC162244ADLR
SSOP
SN74LVC162244AZQLR BGA MI
CROSTA
R JUNI
OR
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC162244ADGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74LVC162244ADGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74LVC162244ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
ZQL
56
1000
350.0
350.0
43.0
SN74LVC162244AZQLR BGA MICROSTAR
JUNIOR
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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