Texas Instruments | SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. L) | Datasheet | Texas Instruments SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. L) Datasheet

Texas Instruments SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs (Rev. L) Datasheet
Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
SN74LVCH162244A 16-Bit Buffer/Driver with 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
Member of the Texas Instruments
Widebus™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.4 ns at 3.3 V
Output Ports Have Equivalent 26-Ω Series
Resistors, so No External Resistors are Required
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Supports Mixed-Mode Signal Operation on
All Ports
(5-V Input/Output Voltage With 3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need for
External Pullup or Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Servers
PCs and Notebooks
Network Switches
Wireless and Telecom Infrastructures
TV Set-top Boxes
Electronic Points of Sale
3 Description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer.
The SN74LVCH162244A device is designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and transmitters.
Device Information(1)
PART NUMBER
PACKAGE
SSOP (48)
SN74LVCH162244A TSSOP (48)
TVSOP (48)
BODY SIZE (NOM)
15.88 mm × 7.49 mm
12.50 mm × 6.10 mm
9.70 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
5
5
6
6
7
8
8
8
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics ..........................................
Switching Characteristics .........................................
Operating Characteristics..........................................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
11
11
10 Application and Implementation........................ 12
10.1 Application Information.......................................... 12
10.2 Typical Application ............................................... 12
11 Power Supply Recommendations ..................... 13
12 Layout................................................................... 13
12.1 Layout Guidelines ................................................. 13
12.2 Layout Example .................................................... 13
13 Device and Documentation Support ................. 14
13.1 Trademarks ........................................................... 14
13.2 Electrostatic Discharge Caution ............................ 14
13.3 Glossary ................................................................ 14
14 Mechanical, Packaging, and Orderable
Information ........................................................... 14
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (March 2005) to Revision L
Page
•
Updated document to new TI data sheet standards. ............................................................................................................ 1
•
Changed Updated Ioff Features bullet..................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. .............................................................................................................................................. 5
•
Changed MAX ambient temperature from 85°C to 125°C. ................................................................................................... 6
•
Added Thermal Information table. .......................................................................................................................................... 6
•
Added Typical Characteristics. .............................................................................................................................................. 8
2
Submit Documentation Feedback
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
6 Pin Configuration and Functions
DL, DGG, OR DGV PACKAGE
(TOP VIEW)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
Pin Functions
PIN
I/O
DESCRIPTION
1OE
I
Output Enable 1
2
1Y1
O
1Y1 Output
3
1Y2
O
1Y2 Output
4
GND
—
Ground pin
5
1Y3
O
1Y3 Output
6
1Y4
O
1Y4 Output
7
VCC
—
Power Pin
8
2Y1
O
2Y1 Output
9
2Y2
O
2Y2 Output
10
GND
—
Ground Pin
11
2Y3
O
2Y3 Output
12
2Y4
O
2Y4 Output
13
3Y1
O
3Y1 Output
14
3Y2
O
3Y2 Output
15
GND
—
Ground Pin
16
3Y3
O
3Y3 Output
17
3Y4
O
3Y4 Output
18
VCC
—
Power Pin
19
4Y1
O
4Y1 Output
20
4Y2
O
4Y2 Output
NO.
NAME
1
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
3
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
Pin Functions (continued)
PIN
I/O
DESCRIPTION
GND
—
Ground Pin
4Y3
O
4Y3 Output
23
4Y4
O
4Y4 Output
24
4OE
I
Output Enable 4
25
3OE
I
Output Enable 3
26
4A4
I
4A4 Input
27
4A3
I
4A3 Input
28
GND
—
29
4A2
I
4A2 Input
30
4A1
I
4A1 Input
31
VCC
—
Power Pin
32
3A4
I
3A4 Input
33
3A3
I
3A3 Input
34
GND
—
35
3A2
I
3A2 Input
36
3A1
I
3A1 Input
37
2A4
I
2A4 Input
38
2A3
I
2A3 Input
39
GND
—
40
2A2
I
2A2 Input
41
2A1
I
2A1 Input
42
VCC
—
Power Pin
43
1A4
I
1A4 Input
44
1A3
I
1A3 Input
45
GND
—
46
1A2
I
1A2 Input
47
1A1
I
1A1 Input
48
2OE
I
Output Enable 2
NO.
NAME
21
22
4
Submit Documentation Feedback
Ground Pin
Ground Pin
Ground Pin
Ground Pin
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
(3)
Continuous current through each VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
5
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
Operating
VCC
Supply voltage
VIH
High-level input voltage
Data retention only
MIN
MAX
1.65
3.6
1.5
VCC = 1.65 V to 1.95 V
Low-level input voltage
VI
Input voltage
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
Output voltage
IOH
High-level output current
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 1.65 V
–2
VCC = 2.3 V
–4
VCC = 2.7 V
–8
V
V
mA
–12
VCC = 1.65 V
2
VCC = 2.3 V
4
VCC = 2.7 V
8
VCC = 3 V
(1)
V
0.8
0
VCC = 3 V
IOL
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
VCC = 1.65 V to 1.95 V
VIL
UNIT
mA
12
–40
10
ns/V
125
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVCH162244A
THERMAL METRIC (1)
DGG
DGV
DL
48 PINS
48 PINS
48 PINS
RθJA
Junction-to-ambient thermal resistance
64.3
78.4
68.4
RθJC(top)
Junction-to-case (top) thermal resistance
17.6
30.7
34.7
RθJB
Junction-to-board thermal resistance
31.5
41.8
41.0
ψJT
Junction-to-top characterization parameter
1.1
3.8
12.3
ψJB
Junction-to-board characterization parameter
31.2
41.3
40.4
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
(1)
6
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
Submit Documentation Feedback
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
1.65 V to 3.6 V
IOH = –2 mA
VOH
II
II(hold)
VCC – 0.2
1.2
1.7
2.7 V
2.2
IOH = –6 mA
3V
2.4
IOH = –8 mA
2.7 V
2
IOH = –12 mA
3V
2
IOL = 100 μA
1.65 V to 3.6 V
0.2
1.65 V
0.45
2.3 V
0.7
IOH = –4 mA
IOL = 4 mA
UNIT
V
2.7 V
0.4
IOL = 6 mA
3V
0.55
IOL = 8 mA
2.7 V
0.6
IOL = 12 mA
3V
0.8
VI = 0 to 5.5 V
3.6 V
VI = 0.58 V
1.65 V
(2)
±5
VI = 1.07 V
1.65 V
(2)
VI = 0.7 V
2.3 V
45
VI = 1.7 V
2.3 V
–45
VI = 0.8 V
3V
75
3V
–75
V
μA
μA
VI = 0 to 3.6 V (3)
3.6 V
±500
Ioff
VI or VO = 5.5 V
0
±10
μA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
μA
ICC
ΔICC
(4)
MAX
2.3 V
VI = 2 V
(1)
(2)
(3)
MIN TYP (1)
1.65 V
IOL = 2 mA
VOL
VCC
VI = VCC or GND
IO = 0
3.6 V ≤ VI ≤ 5.5 V (4)
One input at VCC – 0.6 V, Other inputs at VCC or GND
20
3.6 V
20
2.7 V to 3.6 V
500
μA
μA
Ci
VI = VCC or GND
3.3 V
5.5
pF
Co
VO = VCC or GND
3.3 V
6
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This information was not available at the time of publication.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
This applies in the disabled state only.
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
7
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Y
1
10.2
1
6.4
1
5.6
1.1
4.4
ns
Y
1
14.8
1
8.2
1
6.9
1
5.5
ns
Y
1
12.3
1
7.1
1
6.8
1.8
6.3
ns
7.7 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Power dissipation capacitance
per buffer/driver
Cpd
(1)
Outputs enabled
f = 10 MHz
Outputs
disabled
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
See (1)
See (1)
35
See (1)
See (1)
4
0
50
Temperature (qC)
100
UNIT
pF
This information was not available at the time of publication.
7.8 Typical Characteristics
4
4
TPD in ns
3.5
3.5
3
3
2.5
2.5
TPD - ns
TPD - ns
TPD in ns
2
1.5
1.5
1
1
0.5
0.5
0
0
1
2
3
VCC - V
Submit Documentation Feedback
4
0
-100
-50
D001
Figure 1. TPD Across VCC at 25°C
8
2
150
D002
Figure 2. TPD Across Temperature at 3.3 V
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
9
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
9 Detailed Description
9.1 Overview
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and
symmetrical active-low output-enable (OE) inputs.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Inputs can
be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in a mixed
3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. Active bus-hold circuitry
holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold
circuitry is not recommended.
9.2 Functional Block Diagram
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
10
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
Submit Documentation Feedback
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
9.3 Feature Description
•
•
•
Wide operating range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
(Each 4-Bit Buffer)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
11
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
10 Application and Implementation
10.1 Application Information
The SN74LVCH16244A device is a 16-bit buffer driver. This device can be used as four 4-bit, two 8-bit, or one
16-bit buffer.
It allows data transmission from the A bus to the Y bus with 4 separate enable pins that control 4 bits each. The
output-enable (OE) input can be used to disable sections of the device so that the buses are effectively isolated.
The SN74LVCH16244A device has 5.5 V tolerant inputs at any valid VCC which allows it to be used in multipower systems and can be used for down translation. Active bus-hold circuitry holds unused or undriven inputs at
a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
10.2 Typical Application
Regulated 3.3 V
OE
Vcc
OE
A1
Y1
uC
System Logic
uC or
A8
LEDs
Y8
System Logic
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
12
Submit Documentation Feedback
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
SN74LVCH162244A
www.ti.com
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
Typical Application (continued)
10.2.3 Application Curves
300
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
250
ICC - mA
200
150
100
50
0
0
10
20
30
40
Frequency - MHz
50
60
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Input
Unused Input
Output
Unused Input
Output
Input
Figure 6. Layout Diagram
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
Submit Documentation Feedback
13
SN74LVCH162244A
SCAS545L – OCTOBER 1995 – REVISED JUNE 2014
www.ti.com
13 Device and Documentation Support
13.1 Trademarks
Widebus is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
14
Submit Documentation Feedback
Copyright © 1995–2014, Texas Instruments Incorporated
Product Folder Links: SN74LVCH162244A
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
74LVCH162244ADLRG4
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH162244A
SN74LVCH162244ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH162244A
SN74LVCH162244ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH162244A
SN74LVCH162244AGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVCH162244A
SN74LVCH162244AVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LN2244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVCH162244ADLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
SN74LVCH162244AGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
SN74LVCH162244AVR
TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVCH162244ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
SN74LVCH162244AGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74LVCH162244AVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its
semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers
should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated
circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and
services.
Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is
accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced
documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements
different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the
associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers
remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have
full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products
used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising