Texas Instruments | SN74LVC1G04 Single Inverter Gate (Rev. AD) | Datasheet | Texas Instruments SN74LVC1G04 Single Inverter Gate (Rev. AD) Datasheet

Texas Instruments SN74LVC1G04 Single Inverter Gate (Rev. AD) Datasheet
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SN74LVC1G04
SCES214AD–APRIL1999–REVISED OCTOBER 2014
SN74LVC1G04 Single Inverter Gate
1 Features
•
1
•
•
•
•
•
•
•
•
3 Description
2
Available in the Ultra-Small 0.64-mm
Package (DPW) with 0.5-mm Pitch
Supports 5-V VCC Operation
Inputs Accept Voltages up to 5.5 V Allowing Down
Translation to VCC
Max tpd of 3.3 ns at 3.3-V
Low Power Consumption, 10-μA Max ICC
±24-mA Output Drive at 3.3-V
Ioff Supports Live-Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
2 Applications
•
•
•
•
•
•
•
•
•
•
•
•
AV Receiver
Audio Dock: Portable
Blu-ray Player and Home Theater
Embedded PC
MP3 Player/Recorder (Portable Audio)
Personal Digital Assistant (PDA)
Power: Telecom/Server AC/DC Supply: Single
Controller: Analog and Digital
Solid State Drive (SSD): Client and Enterprise
TV: LCD/Digital and High-Definition (HDTV)
Tablet: Enterprise
Video Analytics: Server
Wireless Headset, Keyboard, and Mouse
This single inverter gate
1.65-V to 5.5-V VCC operation.
is
designed
for
The SN74LVC1G04 device performs the Boolean
function Y = A.
The CMOS device has high output drive while
maintaining low static power dissipation over a broad
VCC operating range.
The SN74LVC1G04 device is available in a variety of
packages, including the ultra-small DPW package
with a body size of 0.8 mm × 0.8 mm.
Device Information(1)
DEVICE NAME
SN74LVC1G04
PACKAGE
BODY SIZE
SOT-23 (5)
2.9mm × 1.6mm
SC70 (5)
2.0mm × 1.25mm
SON (6)
1.45mm × 1.0mm
SON (6)
1.0mm × 1.0mm
X2SON (4)
0.8mm × 0.8mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
A
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC1G04
SCES214AD – APRIL 1999 – REVISED OCTOBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features .................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Simplified Schematic............................................. 1
Revision History..................................................... 2
Pin Configuration and Functions ......................... 3
Specifications......................................................... 4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Absolute Maximum Ratings ..................................... 4
Handling Ratings....................................................... 4
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Switching Characteristics, CL = 15 pF ...................... 6
Switching Characteristics, CL = 30 pF or 50 pF,
–40°C to 85°C ............................................................ 6
7.8 Switching Characteristics, CL = 15 pF, –40°C to
125°C ......................................................................... 6
7.9 Switching Characteristics, CL = 30 pF or 50 pF,
–40°C to 125°C .......................................................... 7
7.10 Operating Characteristics........................................ 7
7.11 Typical Characteristics ............................................ 7
8
9
Parameter Measurement Information .................. 8
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview ................................................................. 10
Functional Block Diagram ....................................... 10
Feature Description................................................. 10
Device Functional Modes........................................ 10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1 Trademarks ........................................................... 13
13.2 Electrostatic Discharge Caution............................ 13
13.3 Glossary ................................................................ 13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
5 Revision History
Changes from Revision AC (March 2014) to Revision AD
Page
•
Updated Features, Description, and Device Information table. ............................................................................................. 1
•
Added Pin Functions table. .................................................................................................................................................... 3
•
Added Thermal Information table. ......................................................................................................................................... 5
•
Added Detailed Description section. .................................................................................................................................... 10
•
Added Application and Implementation section. ................................................................................................................. 11
•
Added Power Supply Recommendations section. .............................................................................................................. 12
•
Added Layout section. ......................................................................................................................................................... 12
Changes from Revision AB (October 2013) to Revision AC
Page
•
Added Applications. ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added DPW Package. ........................................................................................................................................................... 3
•
Moved Tstg to Handling Ratings table. .................................................................................................................................... 4
Changes from Revision AA (September 2013) to Revision AB
Page
•
Updated Input Voltage Feature. ............................................................................................................................................. 1
•
Corrected typographical error in the Operating Characteristics table. ................................................................................... 7
Changes from Revision Z (November 2012) to Revision AA
Page
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Extended maximum temperature operating range from 85°C to 125°C................................................................................. 6
2
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SCES214AD – APRIL 1999 – REVISED OCTOBER 2014
6 Pin Configuration and Functions
DBV PACKAGE
(TOP VIEW)
1
NC
5
DCK PACKAGE
(TOP VIEW)
NC
VCC
A
A
2
GND
3
NC
VCC
A
2
3
3
4
NC
VCC
5
1
GND
2
GND
4
5
1
DRY PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
Y
4
1
6
VCC
A
2
5
NC
GND
3
4
Y
DSF PACKAGE
(TOP VIEW)
NC
A
GND
1
6
2
5
3
4
VCC
NC
Y
Y
YZP PACKAGE
(TOP VIEW)
Y
DNU
NC – No internal connection
DNU – Do not use
See mechanical drawings for dimensions.
A1
A2
A
B1
B2
GND
C1
C2
YZV PACKAGE
(TOP VIEW)
A
VCC
GND
A1
B1
A2
B2
DPW PACKAGE
(TOP VIEW)
VCC GND NC
A
Y
1
5
3
2
4
VCC
Y
Y
Pin Functions
PIN
DBV, DCK,
DRL
DSF, DRY
YZP
NC
1
1, 5
A
2
2
GND
3
NAME
DESCRIPTION
YZV
DPW
A1, B2
–
1
B1
A1
2
Input
3
C1
B1
3
Ground
No connect
Y
4
4
C2
B2
4
Output
VCC
5
6
A2
A2
5
Power terminal
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7 Specifications
7.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
(3)
UNIT
mA
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
PARAMETER
Tstg
V(ESD)
(1)
(2)
4
DEFINITION
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2
Charged device model (CDM), per JEDEC specification JESD22C101, all pins (2)
0
1
Storage temperature range
Electrostatic discharge
kV
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Oprating Conditions (1)
VCC
Operating
Supply voltage
MAX
5.5
Data retention only
V
0.65 × VCC
VCC = 2.3 V to 2.7 V
High-level input voltage
UNIT
1.5
VCC = 1.65 V to 1.95 V
VIH
MIN
1.65
1.7
VCC = 3 V to 3.6 V
V
2
VCC = 4.5 V to 5.5 V
0.7 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
VIL
Low-level input voltage
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 4.5 V to 5.5 V
0.3 × VCC
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
Low-level output current
Δt/Δv
–32
VCC = 1.65 V
4
VCC = 2.3 V
8
16
VCC = 3 V
Input transition rise or fall rate
(1)
mA
24
VCC = 4.5 V
32
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
VCC = 4.5 V
IOL
V
ns/V
5
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
SN74LVC1G04
THERMAL METRIC (1)
DBV
DCK
DRL
DRY
YZP
DPW
5 PINS
5 PINS
5 PINS
6 PINS
5 PINS
4 PINS
RθJA
Junction-to-ambient thermal resistance
229
278
243
439
130
340
RθJCtop
Junction-to-case (top) thermal resistance
164
93
78
277
54
215
RθJB
Junction-to-board thermal resistance
62
65
78
271
51
294
ψJT
Junction-to-top characterization parameter
44
2
10
84
1
41
ψJB
Junction-to-board characterization parameter
62
64
77
271
50
294
RθJCbot
Junction-to-case (bottom) thermal resistance
–
–
–
–
–
250
(1)
UNIT
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
1.65 V to 5.5 V
VCC – 0.1
1.2
1.2
IOH = –8 mA
2.3 V
1.9
1.9
2.4
2.4
2.3
2.3
3V
3.8
TYP
UNIT
MAX
V
IOH = –32 mA
4.5 V
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.1
IOL = 4 mA
1.65 V
0.45
0.45
IOL = 8 mA
2.3 V
0.3
0.3
3.8
0.4
0.4
0.55
0.55
0.55
0.55
3V
IOL = 24 mA
IOL = 32 mA
4.5 V
VI = 5.5 V or GND
Ioff
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
MIN
VCC – 0.1
IOL = 16 mA
A input
MAX
1.65 V
IOH = –24 mA
II
TYP (1)
MIN
IOH = –4 mA
IOH = –16 mA
VOL
RECOMMENDED
–40°C to 125°C
–40°C to 85°C
VCC
IO = 0
V
0 to 5.5 V
±5
±5
μA
0
±10
±10
μA
1.65 V to 5.5 V
10
10
μA
3 V to 5.5 V
500
500
μA
3.3 V
3.5
3.50
pF
VCC = 5 V
± 0.5 V
UNIT
All typical values are at VCC = 3.3 V, TA = 25°C.
7.6 Switching Characteristics, CL = 15 pF
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted)
(see Figure 3)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2
6.4
1
4.2
0.7
3.3
0.7
3.1
ns
7.7 Switching Characteristics, CL = 30 pF or 50 pF, –40°C to 85°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted)
(see Figure 4)
–40°C to 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3
7.5
1.4
5.2
1
4.2
1
3.7
ns
7.8 Switching Characteristics, CL = 15 pF, –40°C to 125°C
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted)
(see Figure 3)
–40°C to 125°C
6
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2
6.4
1
4.2
0.7
3.3
0.7
3.1
ns
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7.9 Switching Characteristics, CL = 30 pF or 50 pF, –40°C to 125°C
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted)
(see Figure 4)
–40°C to 125°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
3
7.5
1.4
5.2
1
4.2
1
3.7
ns
7.10 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
TYP
TYP
TYP
TYP
16
18
18
20
f = 10 MHz
UNIT
pF
7.11 Typical Characteristics
6
8
TPD
TPD
7
5
6
TPD - ns
TPD - ns
4
3
2
5
4
3
2
1
0
-100
1
-50
0
50
Temperature - °C
100
150
0
0
1
D001
Figure 1. TPD Across Temperature at 3.3-V VCC
Copyright © 1999–2014, Texas Instruments Incorporated
2
3
Vcc - V
4
5
D002
Figure 2. TPD Across VCC at 25°C
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8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
tPHL
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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Parameter Measurement Information (continued)
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LVC1G04 device contains inverter gate and performs the Boolean function Y = A. This device is fully
specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing
damaging current backflow through the device when it is powered down.
The DPW package technology is a major breakthrough in IC packaging. Its tiny 0.64 mm square footprint saves
significant board space over other package options while still retaining the traditional manufacturing friendly lead
pitch of 0.5 mm.
9.2 Functional Block Diagram
A
Y
9.3 Feature Description
•
•
•
•
Wide operating voltage range.
– Operates from 1.65 V to 5.5 V.
Allows down voltage translation.
Inputs accept voltages to 5.5 V.
Ioff feature allows voltages on the inputs and outputs, when VCC is 0 V.
9.4 Device Functional Modes
Function Table
INPUT
A
10
OUTPUT
Y
H
L
L
H
Copyright © 1999–2014, Texas Instruments Incorporated
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Product Folder Links: SN74LVC1G04
SN74LVC1G04
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SCES214AD – APRIL 1999 – REVISED OCTOBER 2014
10 Application and Implementation
10.1 Application Information
The SN74LVC1G04 is a high drive CMOS device that can be used for implementing inversion logic with a high
output drive, such as an LED application. It can produce 24 mA of drive current at 3.3 V making it Ideal for
driving multiple outputs and good for high speed applications up to 100 Mhz. The inputs are 5.5 V tolerant
allowing it to translate down to VCC.
10.2 Typical Application
Inverter Logic Function
Basic LED Driver
VCC
VCC
uC or Logic
uC or Logic
uC or Logic
LVC1G04
LVC1G04
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads so routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in the Recommended Operating
Conditions table at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed (IO max) per output and should not exceed total current (continuous
current through VCC or GND) for the part. These limits are located in the Absolute Maximum Ratings
table.
– Outputs should not be pulled above VCC.
Copyright © 1999–2014, Texas Instruments Incorporated
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Product Folder Links: SN74LVC1G04
11
SN74LVC1G04
www.ti.com
SCES214AD – APRIL 1999 – REVISED OCTOBER 2014
Typical Application (continued)
10.2.3 Application Curves
7
Icc
Icc
Icc
Icc
6
Icc - mA
5
1.8V
2.5V
3.3V
5V
4
3
2
1
0
0
20
40
Frequency - MHz
60
80
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the min and max supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, a 0.1-μF capacitor is recommended. if there are multiple VCC pins, then a 0.01-μF or 0.022-μF capacitor
is recommended for each power pin. It is ok to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as
close to the power pin as possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused; for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. The rules that must be observed under all circumstances are specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
The logic level that should be applied to any particular unused input depends on the function of the device.
Generally they will be tied to GND or VCC; whichever makes more sense or is more convenient.
12.2 Layout Example
VCC
Unused Input
Input
Output
Unused Input
Output
Input
12
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Product Folder Links: SN74LVC1G04
SN74LVC1G04
www.ti.com
SCES214AD – APRIL 1999 – REVISED OCTOBER 2014
13 Device and Documentation Support
13.1 Trademarks
All trademarks are the property of their respective owners.
13.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1999–2014, Texas Instruments Incorporated
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Product Folder Links: SN74LVC1G04
13
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC1G04DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C045, C04F, C04J,
C04K, C04R)
(C04H, C04P)
SN74LVC1G04DBVRE4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C04
C04P
SN74LVC1G04DBVT
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(C045, C04F, C04J,
C04K, C04R)
(C04H, C04P, C04S)
SN74LVC1G04DBVTE4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C04
C04P
SN74LVC1G04DBVTG4
ACTIVE
SOT-23
DBV
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C04
C04P
SN74LVC1G04DCK3
ACTIVE
SC70
DCK
5
3000
Pb-Free
(RoHS)
CU SNBI
Level-1-260C-UNLIM
-40 to 125
(CCF, CCZ)
SN74LVC1G04DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP, CCS)
SN74LVC1G04DCKRE4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP, CCS)
SN74LVC1G04DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP, CCS)
SN74LVC1G04DCKT
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP)
SN74LVC1G04DCKTE4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP)
SN74LVC1G04DCKTG4
ACTIVE
SC70
DCK
5
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
(CC5, CCF, CCK, CC
R)
(CCH, CCP)
SN74LVC1G04DPWR
ACTIVE
X2SON
DPW
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
K4
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
4-Apr-2019
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC1G04DRLR
ACTIVE
SOT-5X3
DRL
5
4000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
(CC7, CCR)
SN74LVC1G04DRY2
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CC
SN74LVC1G04DRYR
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CC
SN74LVC1G04DRYRG4
ACTIVE
SON
DRY
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
CC
SN74LVC1G04DSF2
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 85
CC
SN74LVC1G04DSFR
ACTIVE
SON
DSF
6
5000
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-1-260C-UNLIM
-40 to 125
CC
SN74LVC1G04YZPR
ACTIVE
DSBGA
YZP
5
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
(CC7, CCN)
SN74LVC1G04YZVR
ACTIVE
DSBGA
YZV
4
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CC
7
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G04 :
• Automotive: SN74LVC1G04-Q1
• Enhanced Product: SN74LVC1G04-EP
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
178.0
9.2
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
178.0
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
178.0
SN74LVC1G04DBVT
SOT-23
DBV
5
250
SN74LVC1G04DBVT
SOT-23
DBV
5
W
Pin1
(mm) Quadrant
3.3
3.23
1.55
4.0
8.0
Q3
9.0
3.23
3.17
1.37
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
250
178.0
9.0
3.3
3.2
1.4
4.0
8.0
Q3
SN74LVC1G04DBVT
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G04DBVTG4
SOT-23
DBV
5
250
178.0
9.0
3.23
3.17
1.37
4.0
8.0
Q3
SN74LVC1G04DCKR
SC70
DCK
5
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G04DCKR
SC70
DCK
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
SN74LVC1G04DCKR
SC70
DCK
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G04DCKT
SC70
DCK
5
250
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74LVC1G04DCKT
SC70
DCK
5
250
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
SN74LVC1G04DPWR
X2SON
DPW
5
3000
178.0
8.4
0.91
0.91
0.5
2.0
8.0
Q3
SN74LVC1G04DRLR
SOT-5X3
DRL
5
4000
180.0
8.4
1.98
1.78
0.69
4.0
8.0
Q3
SN74LVC1G04DRLR
SOT-5X3
DRL
5
4000
180.0
9.5
1.78
1.78
0.69
4.0
8.0
Q3
SN74LVC1G04DRY2
SON
DRY
6
5000
180.0
9.5
1.6
1.15
0.75
4.0
8.0
Q3
SN74LVC1G04DRY2
SON
DRY
6
5000
180.0
8.4
1.65
1.2
0.7
4.0
8.0
Q3
SN74LVC1G04DRYR
SON
DRY
6
5000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVC1G04DSF2
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q3
SN74LVC1G04DSFR
SON
DSF
6
5000
180.0
9.5
1.16
1.16
0.5
4.0
8.0
Q2
SN74LVC1G04YZPR
DSBGA
YZP
5
3000
178.0
9.2
1.02
1.52
0.63
4.0
8.0
Q1
SN74LVC1G04YZVR
DSBGA
YZV
4
3000
180.0
8.4
1.0
1.0
0.63
4.0
8.0
Q1
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G04DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LVC1G04DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G04DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G04DBVT
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G04DBVTG4
SOT-23
DBV
5
250
180.0
180.0
18.0
SN74LVC1G04DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G04DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74LVC1G04DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LVC1G04DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74LVC1G04DCKT
SC70
DCK
5
250
180.0
180.0
18.0
SN74LVC1G04DPWR
X2SON
DPW
5
3000
205.0
200.0
33.0
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Oct-2019
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC1G04DRLR
SOT-5X3
DRL
5
4000
202.0
201.0
28.0
SN74LVC1G04DRLR
SOT-5X3
DRL
5
4000
184.0
184.0
19.0
SN74LVC1G04DRY2
SON
DRY
6
5000
184.0
184.0
19.0
SN74LVC1G04DRY2
SON
DRY
6
5000
202.0
201.0
28.0
SN74LVC1G04DRYR
SON
DRY
6
5000
184.0
184.0
19.0
SN74LVC1G04DSF2
SON
DSF
6
5000
184.0
184.0
19.0
SN74LVC1G04DSFR
SON
DSF
6
5000
184.0
184.0
19.0
SN74LVC1G04YZPR
DSBGA
YZP
5
3000
220.0
220.0
35.0
SN74LVC1G04YZVR
DSBGA
YZV
4
3000
182.0
182.0
20.0
Pack Materials-Page 3
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DPW0005A
X2SON - 0.4 mm max height
SCALE 12.000
PLASTIC SMALL OUTLINE - NO LEAD
0.85
0.75
B
A
0.85
0.75
PIN 1 INDEX AREA
0.4 MAX
C
SEATING PLANE
NOTE 3
(0.1)
0.05
0.00
(0.25)
4X (0.05)
0.25 0.1
2
4
2X
0.48
3
NOTE 3
2X (0.26)
5
1
4X
0.27
0.17
(0.06)
3X
0.27
0.17
0.1 C A B
0.05 C
0.32
0.23
4223102/B 09/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The size and shape of this feature may vary.
www.ti.com
EXAMPLE BOARD LAYOUT
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
(0.78)
SYMM
4X (0.42)
( 0.1)
VIA
0.05 MIN
ALL AROUND
TYP
1
5
4X (0.22)
SYMM
4X (0.26)
(0.48)
3
2
4
(R0.05) TYP
( 0.25)
4X (0.06)
(0.21) TYP
EXPOSED METAL
CLEARANCE
SOLDER MASK
OPENING, TYP
METAL UNDER
SOLDER MASK
TYP
LAND PATTERN EXAMPLE
SOLDER MASK DEFINED
SCALE:60X
4223102/B 09/2017
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, refer to QFN/SON PCB application note
in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DPW0005A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4X (0.42)
4X (0.22)
4X (0.06)
5
1
( 0.24)
4X (0.26)
SYMM
(0.21)
TYP
SOLDER MASK
EDGE
3
2
(R0.05) TYP
(0.48)
4
SYMM
(0.78)
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD
92% PRINTED SOLDER COVERAGE BY AREA
SCALE:100X
4223102/B 09/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
YZP0005
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
C
SYMM
1
TYP
D: Max = 1.418 mm, Min =1.358 mm
B
0.5
TYP
E: Max = 0.918 mm, Min =0.858 mm
A
5X
0.015
0.25
0.21
C A B
1
2
SYMM
4219492/A 05/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.23)
2
1
A
(0.5) TYP
SYMM
B
C
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219492/A 05/2017
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0005
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
5X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
SYMM
B
C
METAL
TYP
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4219492/A 05/2017
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
D: Max = 0.918 mm, Min =0.858 mm
E: Max = 0.918 mm, Min =0.858 mm
PACKAGE OUTLINE
DSF0006A
X2SON - 0.4 mm max height
SCALE 10.000
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.05
0.95
0.4 MAX
C
SEATING PLANE
0.05 C
(0.11) TYP
SYMM
0.05
0.00
3
4
SYMM
2X
0.7
4X
0.35
6
1
6X
(0.1)
PIN 1 ID
6X
0.45
0.35
0.22
0.12
0.07
0.05
C B A
C
4220597/A 06/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MO-287, variation X2AAF.
www.ti.com
EXAMPLE BOARD LAYOUT
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6X (0.17)
6
SYMM
4X (0.35)
4
3
SYMM
(0.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:40X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
EXPOSED METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220597/A 06/2017
NOTES: (continued)
4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DSF0006A
X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
6X (0.6)
(R0.05) TYP
1
6
6X (0.17)
SYMM
4X (0.35)
4
3
SYMM
(0.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:40X
4220597/A 06/2017
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
DRY 6
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4207181/G
PACKAGE OUTLINE
DRY0006A
USON - 0.6 mm max height
SCALE 8.500
PLASTIC SMALL OUTLINE - NO LEAD
1.05
0.95
B
A
PIN 1 INDEX AREA
1.5
1.4
C
0.6 MAX
SEATING PLANE
0.05
0.00
0.08 C
3X 0.6
SYMM
(0.127) TYP
(0.05) TYP
3
4
4X
0.5
SYMM
2X
1
1
6
6X
0.4
0.3
PIN 1 ID
(OPTIONAL)
5X
0.25
0.15
0.1
0.05
0.35
0.25
C A B
C
4222894/A 01/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
6
1
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
LAND PATTERN EXAMPLE
1:1 RATIO WITH PKG SOLDER PADS
EXPOSED METAL SHOWN
SCALE:40X
0.05 MAX
ALL AROUND
EXPOSED
METAL
0.05 MIN
ALL AROUND
EXPOSED
METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4222894/A 01/2018
NOTES: (continued)
3. For more information, see QFN/SON PCB application report in literature No. SLUA271 (www.ti.com/lit/slua271).
www.ti.com
EXAMPLE STENCIL DESIGN
DRY0006A
USON - 0.6 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
SYMM
(0.35)
5X (0.3)
1
6
6X (0.2)
SYMM
4X (0.5)
4
3
(R0.05) TYP
(0.6)
SOLDER PASTE EXAMPLE
BASED ON 0.075 - 0.1 mm THICK STENCIL
SCALE:40X
4222894/A 01/2018
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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