Texas Instruments | Single Power Supply Single Buffer GATE w/ 3-State Output CMOS Logic Level Shifte (Rev. A) | Datasheet | Texas Instruments Single Power Supply Single Buffer GATE w/ 3-State Output CMOS Logic Level Shifte (Rev. A) Datasheet

Texas Instruments Single Power Supply Single Buffer GATE w/ 3-State Output CMOS Logic Level Shifte (Rev. A) Datasheet
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SN74LV1T126
SCLS744A – DECEMBER 2013 – REVISED FEBRUARY 2014
SN74LV1T126 Single Power Supply Single Buffer Gate with 3-State Output CMOS Logic
Level Shifter
1 Features
2 Applications
•
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1
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(1)
Single-Supply Voltage Translator at
5.0/3.3/2.5/1.8V VCC
Operating Range of 1.8V to 5.5V
Up Translation
– 1.2V(1) to 1.8V at 1.8V VCC
– 1.5V(1) to 2.5V at 2.5V VCC
– 1.8V(1) to 3.3V at 3.3V VCC
– 3.3V to 5.0V at 5.0V VCC
Down Translation
– 3.3V to 1.8V at 1.8V VCC
– 3.3V to 2.5V at 2.5V VCC
– 5.0V to 3.3V at 3.3V VCC
Logic Output is Referenced to VCC
Output Drive
– 8.0mA Output Drive at 5.0V
– 7.0mA Output Drive at 3.3V
– 3.0mA Output Drive at 1.8V
Characterized up to 50MHz at 3.3V Vcc
5.0V Tolerance on Input Pins
–40°C to 125°C Operating Temperature Range
Latch-Up Performance Exceeds 250mA
Per JESD 17
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Supports Standard Logic Pinouts
CMOS Output B Compatible with AUP1G and
LVC1G Families
Refer to the VIH/VIL and output drive for lower VCC condition
Industrial controllers
Telecom
Portable applications
Servers
PC and notebooks
Automotive
3 Description
SN74LV1T126 is a low voltage CMOS gate logic that
operates at a wider voltage range for industrial,
portable, telecom, and automotive applications. The
output level is referenced to the supply voltage and is
able to support 1.8V/2.5V/3.3V/5V CMOS levels.
The input is designed with a lower threshold circuit to
match 1.8V input logic at VCC = 3.3V and can be used
in 1.8V to 3.3V level up translation. In addition, the
5V tolerant input pins enable down translation (e.g.
3.3V to 2.5V output at VCC = 2.5V). The wide VCC
range of 1.8V to 5.5V allows generation of desired
output levels to connect to controllers or processors.
The SN74LV1T126 is designed with current-drive
capability of 8 mA to reduce line reflections,
overshoot, and undershoot caused by high-drive
outputs.
Device Information
ORDER NUMBER
PACKAGE
BODY SIZE
SN74LV1T126DBVR
SOT-23 (5)
2,90mm x 1,60mm
SN74LV1T126DCKR
SC70 (5)
2,00mm x 1,25mm
DCK or DBV PACKAGE
(TOP VIEW)
OE
1
A
2
GND
3
5
VCC
4
Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LV1T126
SCLS744A – DECEMBER 2013 – REVISED FEBRUARY 2014
www.ti.com
Table of Contents
1
2
3
4
Features .................................................................
Applications ..........................................................
Description ............................................................
Revision History ...................................................
1
1
1
2
4.1
4.2
4.3
4.4
4.5
3
5
6
6
7
Logic Diagram ..........................................................
Typical Design Examples .........................................
Absolute Maximum Ratings .....................................
Recommended Operating Conditions ......................
Electrical Characteristics ..........................................
4.6 Switching Characteristics ......................................... 8
4.7 Operating Characteristics ........................................ 8
5
Parameter Measurement Information ................. 9
6
Device and Documentation Support ................. 11
5.1 More Product Selection .......................................... 10
6.1 Trademarks ............................................................ 11
6.2 Electrostatic Discharge Caution ............................. 11
6.3 Glossary ................................................................. 11
7
Mechanical, Packaging, and Orderable
Information .......................................................... 11
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (December 2013) to Revision A
•
2
Page
Updated document formatting. .............................................................................................................................................. 1
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SCLS744A – DECEMBER 2013 – REVISED FEBRUARY 2014
Function Table
INPUT
(Lower Level Input)
(1)
OUTPUT
(VCC CMOS)
OE (1)
A
Y
H
H
H
H
L
L
L
X
Z
Not recommend to floating OE pin for signal oscillation
SUPPLY Vcc = 3.3V
INPUT
(Lower Level Input)
A
OUTPUT
(VCC CMOS)
B
Y
VIH(min) =1.35 V
VIL(max) =0.8 V
VOH(min) = 2.9 V
VOL(max)= 0.2 V
4.1 Logic Diagram
1
OE
2
4
A
Y
white space
Switching Characteristics at 50 MHz
3.5
Output
Input
3.0
2.5
Voltage - V
2.0
1.5
1.0
0.5
0.0
±0.5
0
5
10
15
20
Time - ns
C001
Figure 1. Excellent Signal Integrity (1.8V to 3.3V at 3.3V VCC)
white space
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SCLS744A – DECEMBER 2013 – REVISED FEBRUARY 2014
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Logic Diagram (continued)
Switching Characteristics at 50 MHz
3.5
Input
Output
3.0
2.5
Voltage - V
2.0
1.5
1.0
0.5
0.0
±0.5
0
5
10
15
20
Time - ns
C002
Figure 2. Excellent Signal Integrity (3.3V to 3.3V at 3.3V VCC)
white space
Switching Characteristics at 15 MHz
3.5
Input
Output
3.0
2.5
Voltage - V
2.0
1.5
1.0
0.5
0.0
±0.5
0.0
12.5
25.0
37.5
50.0
62.5
75.0
87.5
Time - nS
C001
Figure 3. Excellent Signal Integrity (3.3V to 1.8V at 1.8V VCC)
4
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4.2 Typical Design Examples
VIH = 2.0V
VIL = 0.8V
5.0V
3.3V
System
VIH = 0.99V
VIL = 0.55V
Vcc = 5.0V
LV1Txx Logic
5.0V, 3.3V
2.5V, 1.8V
1.5V, 1.2V
System
5.0V
System
Vcc = 1.8V
LV1Txx Logic
1.8V
System
Vcc = 3.3V
5.0V, 3.3V
2.5V, 1.8V
System
LV1Txx Logic
3.3V
System
VOH min = 2.4V
VIH min = 1.36V
VOL max = 0.4V
VIL min = 0.8V
Figure 4. Switching Thresholds for 1.8-V to 3.3-V Translation
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4.3 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage range
–0.5
7.0
V
VI
Input voltage range (2)
–0.5
7.0
V
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
Voltage range applied to any output in the high or low state (2)
–0.5
VCC + 0.5
V
VO
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
±25
mA
Continuous current through VCC or GND
±50
mA
DBV package
206
DCK package
252
θJA
Package thermal
impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
–65
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
4.4 Recommended Operating Conditions (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCC
Supply voltage
1.6
5.5
V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
IOH
High-level output
current
Low-level output
current
IOL
VCC = 1.8 V
–3.0
VCC = 2.5 V
–5.0
VCC = 3.3 V
–7.0
VCC = 5.0 V
–8.0
VCC = 1.8 V
3.0
VCC = 2.5 V
5.0
VCC = 3.3 V
7.0
VCC = 5.0 V
8.0
VCC = 1.8 V
20
VCC = 3.3 V or 2.5 V
20
Δt/Δv
Input transition rise or
fall rate
TA
Operating free-air temperature
VCC = 5.0 V
(1)
6
mA
mA
ns/V
20
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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4.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
High-level input
voltage
Low-level input
voltage
1.0
0.99
1.03
1.145
1.18
VCC = 2.75 V
1.22
1.25
VCC = 3.0 V to 3.3 V
1.37
1.39
VCC = 3.6 V
1.47
1.48
VCC = 4.5 V to 5.0 V
2.02
2.03
2.1
2.11
0.55
VCC = 2.25 V to 2.75 V
0.75
0.71
0.8
0.65
1.65 V
1.28
1.21
1.8 V
1.5
1.45
IOH = –3.0 mA
2.3 V
2.0
1.93
IOH = –3.0 mA
2.5 V
2.25
2.15
3.0 V
IOH = –5.5 mA
2.9
2.8
4.2
4.1
4.1
3.95
4.6
V
5.0 V
IOL = 20.0 µA
1.65 V to 5.5 V
0.1
0.1
IOL = 2.0 mA
1.65 V
0.2
0.25
IOH = 3.0 mA
2.3 V
0.15
0.2
0.11
0.15
4.5
0.21
0.252
0.15
0.2
3.0 V
IOL = 5.5 mA
IOL = 4.0 mA
4.5 V
IOL = 8.0 mA
ICC
2.49
V
IOH = –8.0 mA
IOL = 3.0 mA
A input
2.7
2.6
4.5 V
IOH = –8.0 mA
II
2.78
3.3 V
IOH = –4.0 mA
VI = 0 V or VCC
VI = 0 V or VCC; IO = 0;
Open on loading
V
0.8
VCC – 0.1
IOH = –5.5 mA
VOL
0.8
VCC – 0.1
IOH = –3.0 mA
UNIT
V
0.57
1.65 V to 5.5 V
IOH = –2.0 mA
MAX
VCC = 1.65 V to 2.0 V
VCC = 4.5 V to 5.5 V
VOH
MIN
0.95
VCC = 3.0 V to 3.6 V
IOH = –20 µA
TA = –40°C to 125°C
MAX
VCC = 2.0 V
VCC = 5.5 V
VIL
TYP
VCC = 1.65 V to 1.8 V
VCC = 2.25 V to 2.5 V
VIH
TA = 25°C
MIN
0.3
0.35
0 V, 1.8 V, 2.5 V, 3.3 V,
5.5 V
0.1
±1.0
5.0 V
1.0
10.0
3.3 V
1.0
10.0
2.5 V
1.0
10.0
V
μA
μA
1.8 V
1.0
10.0
One input at 0.3 V or 3.4 V
Other inputs at 0 or VCC, IO = 0
5.5 V
1.35
1.5
mA
One input at 0.3 V or 1.1 V
Other inputs at 0 or VCC, IO = 0
1.8 V
10.0
10.0
μA
Ci
VI = VCC or GND
3.3 V
2.0
10.0
pF
Co
VO = VCC or GND
3.3 V
2.5
ΔICC
10.0
2.0
2.5
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7
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4.6 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
FREQUENCY
(TYP)
VCC
5.0 V
DC to 50 MHz
3.3 V
tpd
Any In
Y
DC to 25 MHz
2.5 V
DC to 15 MHz
1.8 V
5.0 V
DC to 50 MHz
3.3 V
tPZH, tPZL
OE
Y
DC to 25 MHz
2.5 V
DC to 15 MHz
1.8 V
5.0 V
DC to 50 MHz
3.3 V
tPHZ, tPLZ
OE
Y
DC to 25MHz
2.5 V
DC to 15MHz
1.8 V
CL
TA = 25°C
MIN
TA = –65°C to 125°C
TYP
MAX
15 pF
2.7
30 pF
3.0
15 pF
30 pF
MIN
TYP
MAX
5.5
3.4
6.5
6.5
4.1
7.5
4.0
7.0
5.0
8.0
4.9
8.0
6.0
9.0
15 pF
5.8
8.5
6.8
9.5
30 pF
6.5
9.5
7.5
10.5
15 pF
10.5
13.0
11.8
14.0
30 pF
12.0
14.5
12.0
15.5
15 pF
3.0
5.0
3.5
6.0
30 pF
4.3
6.5
4.9
7.5
15 pF
4.0
6.5
4.5
7.5
30 pF
5.0
8.0
6.5
9.0
15 pF
5.5
8.0
6.1
9.0
30 pF
7.0
10.0
8.5
11.0
15 pF
9.0
12.0
9.85
13.0
30 pF
12.5
15.0
13.5
16.0
15 pF
4.2
6.5
4.5
7.0
30 pF
4.8
8.0
5.0
8.5
15 pF
4.5
7.0
5.0
8.0
30 pF
5.0
8.0
5.5
9.0
15 pF
5.0
11.0
6.0
9.0
30 pF
6.0
9.0
7.0
10.0
15 pF
8.0
10.0
8.5
11.0
30 pF
8.5
11.0
9.5
12.0
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4.7 Operating Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Cpd
8
Power dissipation capacitance
TEST CONDITIONS
f = 1 MHz and 10 MHz
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VCC
TYP
1.8 V ± 0.15 V
14
2.5 V ± 0.2 V
14
3.3 V ± 0.3 V
14
5.0 V ± 0.5 V
14
UNIT
pF
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5 Parameter Measurement Information
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
1.5 V
tPLZ
tPZL
≈VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZH
tPLH
50% VCC
3V
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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Parameter Measurement Information (continued)
5.1 More Product Selection
DEVICE
PACKAGE
DESCRIPTION
SN74LV1T00
DCK, DBV
2-Input Positive-NAND Gate
SN74LV1T02
DCK, DBV
2-Input Positive-NOR Gate
SN74LV1T04
DCK, DBV
Inverter Gate
SN74LV1T08
DCK, DBV
2-Input Positive-AND Gate
SN74LV1T126
DCK, DBV, DPW
Single Buffer Gate
SN74LV1T14
DCK, DBV
Single Schmitt-Trigger Inverter Gate
SN74LV1T32
DCK, DBV
2-Input Positive-OR Gate
SN74LV1T86
DCK, DBV
Single 2-Input Exclusive-Or Gate
SN74LV1T125
DCK, DBV
Single Buffer Gate with 3-state Output
SN74LV1T126
DCK, DBV
Single Buffer Gate with 3-state Output
SN74LV4T125
RGY, PW
Quadruple Bus Buffer Gate With 3-State Outputs
10
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6 Device and Documentation Support
6.1 Trademarks
All trademarks are the property of their respective owners.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
7 Mechanical, Packaging, and Orderable Information
The following packaging information and addendum reflect the most current data available for the designated
devices. This data is subject to change without notice and revision of this document.
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PACKAGE OPTION ADDENDUM
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4-Apr-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV1T126DBVR
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(NEN3, NENJ, NENS)
SN74LV1T126DBVRG4
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
NEN3
SN74LV1T126DCKR
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
(WN3, WNJ, WNS)
SN74LV1T126DCKRG4
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
WN3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
4-Apr-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
SN74LV1T126DBVR
SOT-23
DBV
5
3000
180.0
8.4
SN74LV1T126DBVR
SOT-23
DBV
5
3000
178.0
SN74LV1T126DBVR
SOT-23
DBV
5
3000
178.0
SN74LV1T126DBVRG4
SOT-23
DBV
5
3000
SN74LV1T126DCKR
SC70
DCK
5
SN74LV1T126DCKR
SC70
DCK
SN74LV1T126DCKR
SC70
DCK
SN74LV1T126DCKRG4
SC70
DCK
3.23
3.17
1.37
4.0
8.0
Q3
9.2
3.3
3.23
1.55
4.0
8.0
Q3
9.0
3.3
3.2
1.4
4.0
8.0
Q3
178.0
9.2
3.3
3.23
1.55
4.0
8.0
Q3
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
5
3000
180.0
8.4
2.47
2.3
1.25
4.0
8.0
Q3
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
5
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV1T126DBVR
SOT-23
DBV
5
3000
202.0
201.0
28.0
SN74LV1T126DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LV1T126DBVR
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LV1T126DBVRG4
SOT-23
DBV
5
3000
180.0
180.0
18.0
SN74LV1T126DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LV1T126DCKR
SC70
DCK
5
3000
202.0
201.0
28.0
SN74LV1T126DCKR
SC70
DCK
5
3000
180.0
180.0
18.0
SN74LV1T126DCKRG4
SC70
DCK
5
3000
180.0
180.0
18.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45
0.90
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/E 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/E 09/2019
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/E 09/2019
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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