Texas Instruments | SNx4LV165A Parallel-Load 8-Bit Shift Registers (Rev. O) | Datasheet | Texas Instruments SNx4LV165A Parallel-Load 8-Bit Shift Registers (Rev. O) Datasheet

Texas Instruments SNx4LV165A Parallel-Load 8-Bit Shift Registers (Rev. O) Datasheet
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SN54LV165A, SN74LV165A
SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016
SNx4LV165A Parallel-Load 8-Bit Shift Registers
1 Features
3 Description
•
•
•
The ’LV165A devices are parallel-load, 8-bit shift
registers designed for 2-V to 5.5-V VCC operation.
1
•
•
•
2-V to 5.5-V VCC Operation
Max tpd of 10.5 ns at 5 V
Support Mixed-Mode Voltage Operation on
All Ports
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
When the devices are clocked, data is shifted toward
the serial output QH. Parallel-in access to each stage
is provided by eight individual direct data inputs that
are enabled by a low level at the shift/load (SH/LD)
input. The ’LV165A devices feature a clock-inhibit
function and a complemented serial output, QH.
Clocking is accomplished by a low-to-high transition
of the clock (CLK) input while SH/LD is held high and
clock inhibit (CLK INH) is held low. The functions of
CLK and CLK INH are interchangeable. Since a low
CLK and a low-to-high transition of CLK INH
accomplishes clocking, CLK INH must be changed to
the high level only while CLK is high. Parallel loading
is inhibited when SH/LD is held high. The parallel
inputs to the register are enabled while SH/LD is held
low, independently of the levels of CLK, CLK INH, or
SER.
2 Applications
•
•
•
•
IP Routers
Enterprise Switches
Access Control and Security: Access Keypads
and Biometrics
Smart Meters: Power Line Communication
These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables
the outputs, preventing damaging current backflow
through the devices when they are powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
SNx4LV165AD
SOIC (16)
9.90 mm × 3.91 mm
SNx4LV165ADB
SSOP (16)
6.20 mm × 5.30 mm
SNx4LV165ANS
SO (16)
10.30 mm × 5.30 mm
SNx4LV165APW
TSSOP (16)
5.00 mm × 4.40 mm
SNx4LV165ADGV
TVSOP (16)
3.60 mm × 4.40 mm
SNx4LV165ARGY
VQFN (16)
4.00 mm × 3.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Logic Diagram (Positive Logic)
A
SH/LD
CLK INH
CLK
SER
1
B
C
12
11
D
13
E
F
3
14
G
H
5
4
6
15
2
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
9
7
QH
QH
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LV165A, SN74LV165A
SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
7
8
1
1
1
2
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings.............................................................. 4
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 6
Timing Requirements—VCC = 2.5 V ± 0.2 V............. 7
Timing Requirements—VCC = 3.3 V ± 0.3 V............. 7
Timing Requirements—VCC = 5 V ± 0.5 V................ 8
Switching Characteristics—VCC = 2.5 V ± 0.2 V..... 10
Switching Characteristics—VCC = 3.3 V ± 0.3 V... 11
Switching Characteristics—VCC = 5 V ± 0.5 V...... 12
Operating Characteristics...................................... 12
Typical Characteristics .......................................... 13
Parameter Measurement Information ................ 14
Detailed Description ............................................ 15
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
16
17
Application and Implementation ........................ 18
9.1 Application Information............................................ 18
9.2 Typical Application .................................................. 18
10 Power Supply Recommendations ..................... 20
11 Layout................................................................... 20
11.1 Layout Guidelines ................................................. 20
11.2 Layout Example .................................................... 20
12 Device and Documentation Support ................. 21
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Related Documentation.........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
21
21
21
13 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision N (July 2013) to Revision O
•
Page
Added Applications section, Device Information table, Table of Contents, Pin Configuration and Functions section,
Specifications section, ESD Ratings table, Thermal Information table, Typical Characteristics section, Detailed
Description section, Application and Implementation section, Power Supply Recommendations section, Layout
section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section ...... 1
Changes from Revision M (December 2010) to Revision N
•
2
Page
Extended maximum temperature operating range from 85°C to 125°C................................................................................. 5
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SCLS402O – APRIL 1998 – REVISED NOVEMBER 2016
5 Pin Configuration and Functions
SN74LV165A: D, DB, DGV, NS or PW Package
SN54LV165A: J or W Package
16-Pin SOIC, SSOP, TVSOP, SOP, TSSOP
Top View
3
14
4
13
5
12
6
11
7
10
8
9
VCC
CLK INH
D
C
B
A
SER
QH
CLK
E
F
G
H
QH
VCC
15
1
16
15 CLK INH
14 D
2
3
5
13 C
12 B
6
11
7
10 SER
4
8
9
QH
16
2
SH/LD
1
GND
SH/LD
CLK
E
F
G
H
QH
GND
SN74LV165A: RGY Package
16-Pin VQFN
Top View
A
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
A
11
I
Serial input A
B
12
I
Serial input B
C
13
I
Serial input C
CLK
2
I
Storage clock
CLK INH
15
I
Storage clock
D
14
I
Serial input D
E
3
I
Serial input E
F
4
I
Serial input F
G
5
I
Serial input G
GND
8
—
H
6
I
Serial input H
O
Output H
QH
7
9
Ground pin
SH/LD
1
I
Load Input
SER
10
I
Serial input
VCC
16
—
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
see
(1)
MIN
MAX
UNIT
Supply voltage
–0.5
7
V
(2)
–0.5
7
V
–0.5
7
V
–0.5
VCC +
0.5
V
Input voltage
Voltage range applied to any output in the high-impedance or power-off state (2)
Output voltage
(2) (3)
Input clamp current
VI < 0
–20
mA
Output clamp current
VO < 0
–50
mA
Continuous output current
VO = 0 to VCC
±25
mA
±50
mA
150
°C
150
°C
Continuous current through VCC or GND
Tjmax Maximum virtual junction temperature
Tstg
(1)
(2)
(3)
Storage temperature
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
4
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
2
5.5
Supply voltage
VCC = 2 V
VIH
High-level input voltage
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 V to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 V to 5.5 V
VCC × 0.7
V
0.5
VCC = 2.3 V to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC = 4.5 V to 5.5 V
High-level output current
VCC × 0.3
5.5
0
VCC
V
–50
µA
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 V to 5.5 V
6
VCC = 4.5 V to 5.5 V
12
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
(1)
Operating free-air temperature
mA
µA
2
VCC = 3 V to 3.6 V
Input transition rise or fall rate
Δt/Δv
50
VCC = 2.3 V to 2.7 V
Low-level output current
V
–12
VCC = 2 V
IOL
V
0
VCC = 2 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
SN54LV165A
–55
125
SN74LV165A
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the Implications of Slow or Floating
CMOS Inputs application report.
6.4 Thermal Information
SN74LV165A
THERMAL METRIC
(1)
D (SOIC)
DB (SSOP)
NS (SO)
PW
(TSSOP)
DGV (TVSOP)
RGY
(VQFN)
UNIT
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
16 PINS
RθJA
Junction-to-ambient
thermal resistance
86.2
102.8
89.4
113.3
125.9
48.8
°C/W
RθJC(top)
Junction-to-case (top)
thermal resistance
46.1
53.3
47.9
48.3
51
46.7
°C/W
RθJB
Junction-to-board thermal
resistance
43.8
53.5
49.8
58.4
57.7
24.9
°C/W
ψJT
Junction-to-top
characterization parameter
13.2
16.6
16.6
6.4
5.7
2
°C/W
ψJB
Junction-to-board
characterization parameter
43.5
52.9
49.5
57.8
57.2
24.9
°C/W
RθJC(bot)
Junction-to-case (bottom)
thermal resistance
N/A
N/A
N/A
N/A
N/A
11.7
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted). Recommended TA = –40°C to +125°C
PARAMETER
VCC
TA
MIN
–55°C to +125°C
IOH = –50 mA
IOH = –2 mA
2 V to 5.5 V
2.3 V
VOH
IOH = –6 mA
IOH = –12 mA
IOL = 50 mA
IOL = 2 mA
3V
4.5 V
2 V to 5.5 V
2.3 V
VOL
IOL = 6 mA
IOL = 12 mA
II
ICC
Ioff
Ci
6
VI = 5.5 V or GND
VI = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
VI = VCC or GND
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3V
4.5 V
0 V to 5.5 V
5.5 V
0
3.3 V
TYP
MAX
UNIT
VCC – 0.1
–40°C to +85°C
CC
– 0.1
–40°C to +125°C
VCC – 0.1
–55°C to +125°C
2
–40°C to +85°C
2
–40°C to +125°C
2
–55°C to +125°C
2.48
–40°C to +85°C
2.48
–40°C to +125°C
2.48
–55°C to +125°C
3.8
–40°C to +85°C
3.8
–40°C to +125°C
3.8
V
–55°C to +125°C
0.1
–40°C to +85°C
0.1
–40°C to +125°C
0.1
–55°C to +125°C
0.4
–40°C to +85°C
0.4
–40°C to +125°C
0.4
–55°C to +125°C
0.44
–40°C to +85°C
0.44
–40°C to +125°C
0.44
–55°C to +125°C
0.55
–40°C to +85°C
0.55
–40°C to +125°C
0.55
–55°C to +125°C
±1
–40°C to +85°C
±1
–40°C to +125°C
±1
–55°C to +125°C
20
–40°C to +85°C
20
–40°C to +125°C
20
–55°C to +125°C
5
–40°C to +85°C
5
–40°C to +125°C
5
–55°C to +125°C
1.7
–40°C to +85°C
1.7
–40°C to +125°C
1.7
V
µA
µA
µA
pF
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6.6 Timing Requirements—VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITION
CLK high or low
tw
Pulse duration
SH/LD low
TA
MIN
25°C
8.5
–55°C to +125°C
9
–40°C to +85°C
9
–40°C to +125°C
9
25°C
11
–55°C to +125°C
13
–40°C to +85°C
13
–40°C to +125°C
13
25°C
SH/LD high before CLK↑
SER before CLK↑
tsu
Setup time
CLK INH before CLK↑
8.5
–40°C to +85°C
8.5
–40°C to +125°C
8.5
25°C
8.5
–55°C to +125°C
9.5
–40°C to +85°C
9.5
–40°C to +125°C
9.5
25°C
7
–55°C to +125°C
7
–40°C to +85°C
7
25°C
Data before SH/LD↑
SER data after CLK↑
th
Hold time
Parallel data after SH/LD↑
SH/LD high after CLK↑
ns
ns
7
11.5
–55°C to +125°C
12
–40°C to +85°C
12
–40°C to +125°C
12
25°C
−1
–55°C to +125°C
0
–40°C to +85°C
0
–40°C to +125°C
0
25°C
UNIT
7
–55°C to +125°C
–40°C to +125°C
MAX
0
–55°C to +125°C
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
0
–55°C to +125°C
0
–40°C to +85°C
0
–40°C to +125°C
0
ns
6.7 Timing Requirements—VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITION
CLK high or low
tw
TA
6
–55°C to +125°C
7
–40°C to +85°C
7
–40°C to +125°C
Pulse duration
25°C
SH/LD low
MIN
25°C
7
9
–40°C to +85°C
9
–40°C to +125°C
9
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UNIT
7.5
–55°C to +125°C
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MAX
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7
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Timing Requirements—VCC = 3.3 V ± 0.3 V (continued)
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITION
SH/LD high before CLK↑
SER before CLK↑
tsu
Setup time
CLK INH before CLK↑
TA
MIN
25°C
5
–55°C to +125°C
6
–40°C to +85°C
6
–40°C to +125°C
6
25°C
5
–55°C to +125°C
6
–40°C to +85°C
6
–40°C to +125°C
6
25°C
5
–55°C to +125°C
5
–40°C to +85°C
5
–40°C to +125°C
Data before SH/LD↑
SER data after CLK↑
th
Hold time
Parallel data after SH/LD↑
SH/LD high after CLK↑
UNIT
ns
5
25°C
7.5
–55°C to +125°C
8.5
–40°C to +85°C
8.5
–40°C to +125°C
8.5
25°C
0
–55°C to +125°C
0
–40°C to +85°C
0
–40°C to +125°C
MAX
0
25°C
0.5
–55°C to +125°C
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
0
–55°C to +125°C
0
–40°C to +85°C
0
–40°C to +125°C
0
ns
6.8 Timing Requirements—VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITION
CLK high or low
tw
Pulse duration
SH/LD low
8
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TA
MIN
25°C
4
–55°C to +125°C
4
–40°C to +85°C
4
–40°C to +125°C
4
25°C
5
–55°C to +125°C
5
–40°C to +85°C
6
–40°C to +125°C
6
MAX
UNIT
ns
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Timing Requirements—VCC = 5 V ± 0.5 V (continued)
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 2)
PARAMETER
TEST CONDITION
SH/LD high before CLK↑
SER before CLK↑
tsu
Setup time
CLK INH before CLK↑
Data before SH/LD↑
TA
4
–55°C to +125°C
4
–40°C to +85°C
4
–40°C to +125°C
4
25°C
4
–55°C to +125°C
4
–40°C to +85°C
4
–40°C to +125°C
4
25°C
3.5
–55°C to +125°C
3.5
–40°C to +85°C
3.5
–40°C to +125°C
3.5
25°C
5
–55°C to +125°C
5
–40°C to +85°C
5
–40°C to +125°C
SER data after CLK↑
th
Hold time
Parallel data after SH/LD↑
0.5
–55°C to +125°C
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
25°C
1
–55°C to +125°C
1
–40°C to +85°C
1
0.5
–55°C to +125°C
0.5
–40°C to +85°C
0.5
–40°C to +125°C
0.5
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UNIT
ns
ns
1
25°C
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MAX
5
25°C
–40°C to +125°C
SH/LD high after CLK↑
MIN
25°C
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6.9 Switching Characteristics—VCC = 2.5 V ± 0.2 V
over operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted), (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
CL = 15 pF
fmax
CL = 50 pF
TA
MIN
TYP
25°C
50 (1)
80 (1)
–55°C to +125°C
45
–40°C to +85°C
45
–40°C to +125°C
45
25°C
40
–55°C to +125°C
35
–40°C to +85°C
35
–40°C to +125°C
35
SH/LD
QH or Q
CL = 15 pF
1 (1)
22 (1)
–40°C to +85°C
1
22
–40°C to +125°C
1
23.5 (1)
–40°C to +85°C
1
23.5
–40°C to +125°C
1
12.9
QH or Q
CL = 50 pF
–40°C to +85°C
1
24
–40°C to +125°C
1
24
15.3
(1)
10
23.3
–55°C to +125°C
1
26
–40°C to +85°C
1
26
–40°C to +125°C
1
26
16.1
25.1
–55°C to +125°C
1
28
–40°C to +85°C
1
28
–40°C to +125°C
1
25°C
H
21.7 (1)
24 (1)
1
ns
23.5
(1)
(1)
25°C
SH/LD
21.5 (1)
1 (1)
25°C
tpd
22
13.1 (1)
–55°C to +125°C
–55°C to +125°C
CLK
19.8 (1)
–55°C to +125°C
25°C
H
MHz
65
12.2 (1)
25°C
tpd
UNIT
(1)
25°C
CLK
MAX
ns
28
15.9
25.3
–55°C to +125°C
1
28
–40°C to +85°C
1
28
–40°C to +125°C
1
28
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.10 Switching Characteristics—VCC = 3.3 V ± 0.3 V
over operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted), (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
CL = 15 pF
fmax
CL = 50 pF
TA
MIN
TYP
25°C
65 (1)
115 (1)
–55°C to +125°C
55
(1)
–40°C to +85°C
55
–40°C to +125°C
55
25°C
60
–55°C to +125°C
50
–40°C to +85°C
50
–40°C to +125°C
50
SH/LD
QH or Q
CL = 15 pF
1 (1)
18 (1)
–40°C to +85°C
1
18
–40°C to +125°C
1
1 (1)
18.5 (1)
–40°C to +85°C
1
18.5
–40°C to +125°C
1
8.9
–40°C to +85°C
1
16.5
–40°C to +125°C
1
16.5
10.9
QH or Q
CL = 50 pF
1
16.9
–40°C to +85°C
1
16.9
–40°C to +125°C
1
(1)
16.9
11.3
19.3
–55°C to +125°C
1
22
–40°C to +85°C
1
22
–40°C to +125°C
1
25°C
H
14.9
–55°C to +125°C
25°C
SH/LD
14.1 (1)
16.5 (1)
1
ns
18.5
(1)
(1)
25°C
tpd
15.8 (1)
–55°C to +125°C
–55°C to +125°C
CLK
18
9.1 (1)
25°C
H
15.4 (1)
–55°C to +125°C
25°C
tpd
MHz
90
8.6 (1)
25°C
CLK
MAX UNIT
ns
22
11.1
17.6
–55°C to +125°C
1
20
–40°C to +85°C
1
20
–40°C to +125°C
1
20
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.11 Switching Characteristics—VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (see Figure 2)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
TA
25°C
CL = 15 pF
fmax
CL = 50 pF
–55°C to +125°C
MIN
TYP
110 (1)
165 (1)
90
(1)
–40°C to +85°C
90
–40°C to +125°C
90
25°C
95
–55°C to +125°C
85
–40°C to +85°C
85
–40°C to +125°C
85
SH/LD
QH or Q
CL = 15 pF
1 (1)
11.5 (1)
–40°C to +85°C
1
11.5
–40°C to +125°C
1
1 (1)
11.5 (1)
–40°C to +85°C
1
11.5
–40°C to +125°C
1
6
–40°C to +85°C
1
10.5
–40°C to +125°C
1
10.5
7.7
QH or Q
CL = 50 pF
1
13.5
–40°C to +85°C
1
13.5
–40°C to +125°C
1
(1)
13.5
7.7
11.9
–55°C to +125°C
1
13.5
–40°C to +85°C
1
13.5
–40°C to +125°C
1
25°C
H
11.9
–55°C to +125°C
25°C
SH/LD
9.9 (1)
10.5 (1)
1
ns
11.5
(1)
(1)
25°C
tpd
9.9 (1)
–55°C to +125°C
–55°C to +125°C
CLK
11.5
6 (1)
25°C
H
9.9 (1)
–55°C to +125°C
25°C
tpd
MHz
125
6 (1)
25°C
CLK
MAX UNIT
ns
13.5
7.6
11
–55°C to +125°C
1
12.5
–40°C to +85°C
1
12.5
–40°C to +125°C
1
12.5
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.12 Operating Characteristics
TA = 25°C
PARAMETER
Cpd
12
Power dissipation capacitance
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TEST CONDITIONS
CL = 50 pF
f = 10 MHz
VCC
TYP
3.3 V
36.1
5V
37.5
UNIT
pF
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6.13 Typical Characteristics
16
CL=15pF
CL=50pF
15
14
Tpd typ (ns)
13
12
11
10
9
8
7
6
2.5
2.75
3
3.25
3.5
3.75 4
Vcc(V)
4.25
4.5
4.75
5
D001
Figure 1. TPD Typical (25°C) vs Vcc
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7 Parameter Measurement Information
VCC
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
0V
tw
tsu
VCC
50% VCC
Input
50% VCC
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
tPHL
tPLH
In-Phase
Output
VOH
50% VCC
VOL
50% VCC
VOH
50% VCC
VOL
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
Output
Waveform 1
S1 at VCC
(see Note B)
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
50% VCC
VOH − 0.3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns,
tf ≤ 3 ns.
D.
The outputs are measured one at a time, with one input transition per measurement.
E.
tPLZ and tPHZ are the same as tdis.
tPZL and tPZH are the same as ten.
G.
tPHL and tPLH are the same as tpd.
H.
All parameters and waveforms are not applicable to all devices.
VOH
≈0 V
A.
F.
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
0V
VCC
Output
Control
Figure 2. Load Circuit and Voltage Waveforms
14
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8 Detailed Description
8.1 Overview
The ’LV165A devices are parallel-load, 8-bit shift registers designed for 2-V to 5.5-V VCC operation.
When the devices are clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The
’LV165A devices feature a clock-inhibit function and a complemented serial output, QH.
8.2 Functional Block Diagram
A
SH/LD
CLK INH
CLK
SER
1
B
C
12
11
D
13
E
F
3
14
G
H
5
4
6
15
2
10
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
S
C1
1D
R
9
7
QH
QH
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
Figure 3. Logic Diagram (Positive Logic)
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Functional Block Diagram (continued)
CLK
CLK INH
SER
L
SH/LD
Data
Inputs
A
H
B
L
C
H
D
L
E
H
F
L
G
H
H
H
QH
H
H
L
H
L
H
L
H
QH
L
L
H
L
H
L
H
L
Inhibit
Serial Shift
Load
Figure 4. Typical Shift, Load, and Inhibit Sequences
8.3 Feature Description
The wide operating range allows the device to be used in a variety of systems that use different logic levels. The
low propagation delay allows fast switching and higher speeds of operation. In addition, the low ground bounce
stabilizes the performance of non-switching outputs while another output is switching.
16
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8.4 Device Functional Modes
Table 1 lists the functional modes of SNx4LV165A.
Table 1. Device Functional Modes
INPUTS
OPERATION
SH/LD
CLK
CLK INH
L
X
X
Parallel load
H
H
X
Q0
H
X
H
Q0
H
L
↑
Shift
H
↑
L
Shift
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74LV165A is a low drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low-drive and slow-edge rates minimize overshoot and undershoot on the
outputs.
9.2 Typical Application
CLK
SER
SN74LV165A
SH/LD
CLK INH
MCU
FPGA
CPU
Parallel Inputs
Shift Registers
A
B
C
L
H
L
H
Dip
Switches
D
E
Jumpers
F
G
Any Slow-Changing
Logic Inputs
H
QH
QH
Figure 5. Input Expansion with Shift Registers
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that can exceed maximum limits. The high drive also creates fast edges into light loads so
consider routing and load conditions to prevent ringing.
9.2.2 Detailed Design Procedure
Recommended input conditions:
• Rise time and fall time specs. See the Recommended Operating Conditions section, (Δt/ΔV)
• Specified high and low level. See the Recommended Operating Conditions section, (VIH and VIL)
• Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC
Recommended output conditions:
• Load currents must not exceed 25 mA per output and 50 mA total for the part.
• Outputs must not be pulled above VCC.
18
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Typical Application (continued)
9.2.3 Application Curves
26
16
CL=15pF
CL=50pF
15
CL = 15pF
CL = 50pF
24
14
22
Tpd max (ns)
Tpd typ (ns)
13
12
11
10
20
18
16
9
14
8
12
7
6
2.5
2.75
3
3.25
3.5
3.75 4
Vcc(V)
4.25
4.5
4.75
5
10
2.5
2.75
3
3.25
D001
Figure 6. Switching Characteristics Comparison
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3.5
3.75 4
Vcc (V)
4.25
4.5
4.75
5
D001
Figure 7. Tpd(max) vs VCC
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC
terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices inputs must never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins must
not be left unconnected because the undefined voltages at the outside connections result in undefined
operational states. Specified below are the rules that must be observed under all circumstances. All unused
inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic
level that must be applied to any particular unused input depends on the function of the device. Generally they
are tied to GND or VCC whichever make more sense or is more convenient. Floating outputs is generally
acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it disables the outputs
section of the part when asserted. This does not disable the input section of the IOs so they also cannot float
when disabled.
11.2 Layout Example
Figure 8. Layout Example
20
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation see the following:
• Power-Up Behavior of Clocked Devices
• Introduction to Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LV165A
Click here
Click here
Click here
Click here
Click here
SN74LV165A
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1998–2016, Texas Instruments Incorporated
Product Folder Links: SN54LV165A SN74LV165A
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV165AD
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADE4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADGVR
ACTIVE
TVSOP
DGV
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADRE4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADRG3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ADRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ANSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
74LV165A
SN74LV165APW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165APWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165APWRE4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165APWRG3
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165APWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165APWT
ACTIVE
TSSOP
PW
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165A
SN74LV165ARGYR
ACTIVE
VQFN
RGY
16
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LV165A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
SN74LV165ARGYRG4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGY
16
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
LV165A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV165A :
• Enhanced Product: SN74LV165A-EP
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LV165ADGVR
TVSOP
DGV
16
2000
330.0
12.4
6.8
4.0
1.6
8.0
12.0
Q1
SN74LV165ADR
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV165ADR
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV165ADRG3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV165ADRG4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74LV165ANSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74LV165APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV165APWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV165APWRG3
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV165APWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV165APWT
TSSOP
PW
16
250
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LV165ARGYR
VQFN
RGY
16
3000
330.0
12.4
3.8
4.3
1.5
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Jun-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV165ADGVR
TVSOP
DGV
16
2000
367.0
367.0
35.0
SN74LV165ADR
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV165ADR
SOIC
D
16
2500
364.0
364.0
27.0
SN74LV165ADRG3
SOIC
D
16
2500
364.0
364.0
27.0
SN74LV165ADRG4
SOIC
D
16
2500
333.2
345.9
28.6
SN74LV165ANSR
SO
NS
16
2000
367.0
367.0
38.0
SN74LV165APWR
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV165APWR
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV165APWRG3
TSSOP
PW
16
2000
364.0
364.0
27.0
SN74LV165APWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
SN74LV165APWT
TSSOP
PW
16
250
367.0
367.0
35.0
SN74LV165ARGYR
VQFN
RGY
16
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
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• DALLAS, TEXAS 75265
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