Texas Instruments | SNx4LVC541A Octal Buffers/Drivers With 3-State Outputs (Rev. N) | Datasheet | Texas Instruments SNx4LVC541A Octal Buffers/Drivers With 3-State Outputs (Rev. N) Datasheet

Texas Instruments SNx4LVC541A Octal Buffers/Drivers With 3-State Outputs (Rev. N) Datasheet
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SN54LVC541A, SN74LVC541A
SCAS298N – JANUARY 1993 – REVISED JUNE 2014
SNx4LVC541A Octal Buffers/Drivers With 3-State Outputs
1 Features
2 Applications
•
•
•
•
•
•
•
•
•
•
1
•
•
•
•
•
•
Operate From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 5.1 ns at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Signal Operation on
All Ports (5-V Input/Output Voltage With
3.3-V VCC)
Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
Latch-Up Performance Exceeds 250 mA
Per JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
On Products Compliant to MIL-PRF-38535,
All Parameters Are Tested Unless Otherwise
Noted. On All Other Products, Production
Processing Does Not Necessarily Include Testing
of All Parameters.
Servers
PCs and Notebooks
Network Switches
Wearable Health and Wellness Devices
Telecom Infrastructures
Electronic Points of Sale
3 Description
The SN54LVC541A octal buffer/driver is designed for
2.7-V to 3.6-V VCC operation, and the SN74LVC541A
octal buffer/driver is designed for 1.65-V to 3.6-V VCC
operation.
Device Information(1)
PART NUMBER
SN74LVC541A
PACKAGE
BODY SIZE (NOM)
SSOP (20)
7.20 mm × 5.30 mm
TVSOP (20)
5.00 mm × 4.40 mm
VQFN (20)
4.50 mm × 3.50 mm
SOIC (20)
12.80 mm × 7.50 mm
TSSOP (20)
6.50 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
4 Simplified Schematic
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN54LVC541A, SN74LVC541A
SCAS298N – JANUARY 1993 – REVISED JUNE 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematic.............................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
4
7.1
7.2
7.3
7.4
7.5
7.6
7.7
4
4
5
5
6
7
Absolute Maximum Ratings .....................................
Handling Ratings.......................................................
Recommended Operating Conditions ......................
Thermal Information ..................................................
Electrical Characteristics—DC Limit Changes..........
Switching Characteristics—AC Limit Changes .........
Switching Characteristics, SN74LVC541A –40°C to
85°C ...........................................................................
7.8 Switching Characteristics, SN74LVC541A –40°C to
125°C .........................................................................
7.9 Operating Characteristics..........................................
7.10 Typical Characteristics ............................................
8
7
7
7
8
9
Detailed Description ............................................ 10
9.1
9.2
9.3
9.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
10
10
10
10
10 Application and Implementation........................ 11
10.1 Application Information.......................................... 11
10.2 Typical Application ............................................... 11
11 Power Supply Recommendations ..................... 12
12 Layout................................................................... 12
12.1 Layout Guidelines ................................................. 12
12.2 Layout Example .................................................... 12
13 Device and Documentation Support ................. 13
13.1
13.2
13.3
13.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
13
13
13
14 Mechanical, Packaging, and Orderable
Information ........................................................... 13
Parameter Measurement Information .................. 9
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (May 2005) to Revision N
Page
•
Updated document to new TI data sheet format. ................................................................................................................... 1
•
Removed Ordering Information table. .................................................................................................................................... 1
•
Updated Ioff Feature bullet. ..................................................................................................................................................... 1
•
Updated Features to include Military Disclaimer. ................................................................................................................... 1
•
Added Applications ................................................................................................................................................................ 1
•
Added Device Information table. ............................................................................................................................................ 1
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating free-air temperature from 85°C to 125°C for SN74LVC541A. ....................................................... 5
•
Updated Thermal Information table. ...................................................................................................................................... 5
•
Added –40°C TO 125°C temperature range to Electrical Characteristics table for SN74LVC541A. ..................................... 6
•
Added Switching Characteristics table –40°C TO 125°C temperature range for SN74LVC541A. ........................................ 7
•
Added Typical Characteristics. ............................................................................................................................................... 8
2
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SCAS298N – JANUARY 1993 – REVISED JUNE 2014
6 Pin Configuration and Functions
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1
20
A2
A1
OE1
VCC
18
A1
A2
A3
A4
A5
A6
A7
A8
SN54LVC541A . . . FK PACKAGE
(TOP VIEW)
2
19 OE2
3
18 Y1
4
17 Y2
16 Y3
5
A3
A4
A5
A6
A7
15 Y4
14 Y5
6
7
13 Y6
12 Y7
8
9
10
11
4
3 2
1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
3
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
VCC
19
Y8
20
2
OE1
1
GND
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN74LVC541A . . . RGY PACKAGE
(TOP VIEW)
OE2
SN54LVC541A . . . J OR W PACKAGE
SN74LVC541A . . . DB, DGV, DW, NS,
OR PW PACKAGE
(TOP VIEW)
Pin Functions
PIN
NO.
NAME
I/O
DESCRIPTION
1
OE1
I
Output enable
2
A1
I
A1 input
3
A2
I
A2 input
4
A3
I
A3 input
5
A4
I
A4 input
6
A5
I
A5 input
7
A6
I
A6 input
8
A7
I
A7 input
A8 input
9
A8
I
10
GND
—
Ground pin
11
Y8
O
Y8 output
12
Y7
O
Y7 output
13
Y6
O
Y6 output
14
Y5
O
Y5 output
15
Y4
O
Y4 output
16
Y3
O
Y3 output
17
Y2
O
Y2 output
18
Y1
O
Y1 output
Output enable
19
OE2
I
20
VCC
—
Power pin
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
6.5
UNIT
V
(2)
VI
Input voltage range
–0.5
6.5
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
6.5
V
VO
Voltage range applied to any output in the high or low state (2) (3)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through VCC or GND
(1)
(2)
(3)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the Recommended Operating Conditions table.
7.2 Handling Ratings
Tstg
V(ESD)
(1)
(2)
4
MIN
MAX
UNIT
–65
150
°C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
Storage temperature range
Electrostatic discharge
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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SCAS298N – JANUARY 1993 – REVISED JUNE 2014
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54LVC541A
VCC
Operating
Supply voltage
Data retention only
SN74LVC541A
MIN
MAX
MIN
MAX
2
3.6
1.65
3.6
1.5
High-level input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Low-level input voltage
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
V
2
VCC = 1.65 V to 1.95 V
VIL
High-level output current
0.8
0
5.5
0
5.5
High or low state
0
VCC
0
VCC
3-state
0
5.5
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
–12
VCC = 3 V
–24
–24
TA
(1)
V
V
mA
4
VCC = 2.3 V
Low-level output current
V
0.8
VCC = 1.65 V
IOL
V
1.5
VCC = 1.65 V to 1.95 V
VIH
UNIT
8
VCC = 2.7 V
12
12
VCC = 3 V
24
24
Operating free-air temperature
–55
125
–40
mA
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
over operating free-air temperature range (unless otherwise noted)
SN74LVC541A
THERMAL METRIC (1)
DB
DGV
DW
NS
PW
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
112.1
128.9
99.4
90.3
100.8
RθJC(top)
Junction-to-case (top) thermal resistance
73.6
43.8
66.9
56.6
35.2
RθJB
Junction-to-board thermal resistance
67.3
70.4
66.9
57.8
51.8
ψJT
Junction-to-top characterization parameter
33.3
3.2
33.8
28.7
2.2
ψJB
Junction-to-board characterization parameter
66.9
69.7
66.5
57.4
51.2
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, literature
number SPRA953.
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7.5 Electrical Characteristics—DC Limit Changes
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
–55°C TO 125°C
–40°C TO 85°C
SN54LVC541A
SN74LVC541A
MIN
2.7 V to
3.6 V
(1)
(2)
6
SN74LVC541A
MAX
MIN
VCC – 0.2
VCC – 0.3
TYP (1)
UNIT
MAX
VCC – 0.2
1.65 V
1.20
1.20
2.3 V
1.7
1.7
2.7 V
2.2
2.2
2.2
3V
2.4
2.4
2.4
3V
2.2
2.2
2.2
1.65 V to
3.6 V
IOL = 100 μA
2.7 V to
3.6 V
V
0.2
0.3
0.45
0.45
0.7
0.7
0.2
IOL = 4 mA
1.65 V
IOL = 8 mA
2.3 V
IOL = 12 mA
2.7 V
0.4
0.4
0.4
IOL = 24 mA
3V
0.55
0.55
0.55
II
VI = 0 to 5.5 V
Ioff
VI or VO = 5.5 V
0
IOZ
VO = 0 to 5.5 V
3.6 V
VI = VCC or GND
3.6 V ≤ VI ≤ 5.5 V (2)
ΔICC
TYP (1)
IOH = –8 mA
IOH = –24 mA
ICC
MIN
IOH = –4 mA
IOH = –12 mA
VOL
MAX
1.65 V to
3.6 V
IOH = –100 μA
VOH
TYP (1)
–40°C TO 125°C
3.6 V
IO = 0
One input at VCC – 0.6 V,
Other inputs at VCC or GND
±5
±5
μA
±10
±10
μA
±15
±10
±10
μA
10
10
10
10
10
10
500
500
500
±5
3.6 V
2.7 V to
3.6 V
V
μA
μA
Ci
VI = VCC or GND
3.3 V
4
4
4
pF
Co
VO = VCC or GND
3.3 V
5.5
5.5
5.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
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SCAS298N – JANUARY 1993 – REVISED JUNE 2014
7.6 Switching Characteristics—AC Limit Changes
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN54LVC541A
FROM
(INPUT)
PARAMETER
TO
(OUTPUT)
VCC = 2.7 V
MIN
VCC = 3.3 V ± 0.3 V
UNIT
MAX
MIN
MAX
tpd
A
Y
5.6
1
5.1
ns
ten
OE
Y
7.5
1
7
ns
tdis
OE
Y
7.7
1
7
ns
7.7 Switching Characteristics, SN74LVC541A –40°C to 85°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC541A
–40°C TO 85°C
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
1
15.7
1
7.8
1
5.6
1.5
5.1
ns
ten
OE
Y
1
17.5
1
10.5
1
7.5
1.5
7
ns
tdis
OE
Y
1
16.5
1
9
1
7.7
1.5
7
ns
1
ns
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
UNIT
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
tsk(o)
7.8 Switching Characteristics, SN74LVC541A –40°C to 125°C
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3)
SN74LVC541A
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
–40°C TO 125°C
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN
MAX
MIN
UNIT
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
MAX
MIN
MAX
tpd
A
Y
1
16.3
1
8.3
1
6.1
1
5.6
ns
ten
OE
Y
1
18.5
1
11.1
1
8
1
7.5
ns
tdis
OE
Y
1
17.3
1
9.7
1
8.2
1
7.5
ns
1.5
ns
tsk(o)
7.9 Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per buffer/driver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
65
58
33
2
2
2
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UNIT
pF
7
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7.10 Typical Characteristics
4
6
TPD
5.5
3.5
5
3
4.5
3.5
TPD - ns
TPD - ns
4
3
2.5
2
1.5
2
1
1.5
1
0.5
0.5
TPD
0
0
1
2
VCC - V
3
3.5
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0
-100
-50
D001
Figure 1. SN74LVC541A TPD Across VCC at 25°C
8
2.5
0
50
Temperature (qC)
100
150
D002
Figure 2. SN74LVC541A TPD Across Temperature at 3.3 V
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SCAS298N – JANUARY 1993 – REVISED JUNE 2014
8 Parameter Measurement Information
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VI
VM
Input
VM
0V
VOH
VM
Output
VM
VOL
VM
0V
VLOAD/2
VM
tPZH
VOH
Output
VM
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPHL
VM
tPZL
tPHL
tPLH
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The 'LVC541A devices are ideal for driving bus lines or buffering memory address registers.
These devices feature inputs and outputs on opposite sides of the package to facilitate printed circuit board
layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output enable (OE1
or OE2) input is high, all eight outputs are in the high-impedance state. Inputs can be driven from either 3.3-V or
5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system
environment. These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
9.2 Functional Block Diagram
OE1
OE2
A1
1
19
2
18
Y1
To Seven Other Channels
9.3 Feature Description
•
•
•
Wide operating voltage range
– Operates from 1.65 V to 3.6 V
Allows down voltage translation
– Inputs accept voltages to 5.5 V
Ioff feature
– Allows voltages on the inputs and outputs when VCC is 0 V
9.4 Device Functional Modes
Table 1. Function Table
INPUTS
10
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OE1
OE2
A
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC541A SN74LVC541A
SN54LVC541A, SN74LVC541A
www.ti.com
SCAS298N – JANUARY 1993 – REVISED JUNE 2014
10 Application and Implementation
10.1 Application Information
The SN74LVC541A is a high-drive CMOS device that can be used for a multitude of bus-interface type
applications where the data needs to be retained or latched. It can produce 24 mA of drive current at 3.3 V.
Therefore, this device is ideal for driving multiple outputs and for high-speed applications up to 100 Mhz. The
inputs are 5.5 V tolerant allowing the device to translate down to VCC.
10.2 Typical Application
Regulated 3.3 V
OE1
Vcc
OE2
A1
Y1
uC
System Logic
A8
uC or
System Logic
Y8
LEDs
GND
Figure 4. Typical Application Diagram
10.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. The high drive will also create fast
edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.
10.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 50 mA total for the part.
– Outputs should not be pulled above VCC.
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC541A SN74LVC541A
Submit Documentation Feedback
11
SN54LVC541A, SN74LVC541A
SCAS298N – JANUARY 1993 – REVISED JUNE 2014
www.ti.com
Typical Application (continued)
10.2.3 Application Curves
300
ICC 1.8 V
ICC 2.5 V
ICC 3.3 V
250
ICC - mA
200
150
100
50
0
0
10
20
30
Frequency
40
50
60
D003
Figure 5. ICC vs Frequency
11 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μf is recommended; if there are multiple VCC pins, then 0.01 μf or 0.022 μf is recommended for each
power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μf and a
1 μf are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
12 Layout
12.1 Layout Guidelines
When using multiple bit logic devices inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 6 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC whichever make more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the I/Os, so they cannot float when disabled.
12.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 6. Layout Diagram
12
Submit Documentation Feedback
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC541A SN74LVC541A
SN54LVC541A, SN74LVC541A
www.ti.com
SCAS298N – JANUARY 1993 – REVISED JUNE 2014
13 Device and Documentation Support
13.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54LVC541A
Click here
Click here
Click here
Click here
Click here
SN74LVC541A
Click here
Click here
Click here
Click here
Click here
13.2 Trademarks
All trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1993–2014, Texas Instruments Incorporated
Product Folder Links: SN54LVC541A SN74LVC541A
Submit Documentation Feedback
13
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9759501Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629759501Q2A
SNJ54LVC
541AFK
5962-9759501QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759501QR
A
SNJ54LVC541AJ
5962-9759501QSA
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759501QS
A
SNJ54LVC541AW
SN74LVC541ADBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ADBRG4
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ADGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ADGVRE4
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ADGVRG4
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ADW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC541A
SN74LVC541ADWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC541A
SN74LVC541ADWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC541A
SN74LVC541ANSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LVC541A
SN74LVC541APW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541APWG4
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541APWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 125
LC541A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LVC541APWRE4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541APWRG4
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541APWT
ACTIVE
TSSOP
PW
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
LC541A
SN74LVC541ARGYR
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC541A
SN74LVC541ARGYRG4
ACTIVE
VQFN
RGY
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
LC541A
SNJ54LVC541AFK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629759501Q2A
SNJ54LVC
541AFK
SNJ54LVC541AJ
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759501QR
A
SNJ54LVC541AJ
SNJ54LVC541AW
ACTIVE
CFP
W
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9759501QS
A
SNJ54LVC541AW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54LVC541A, SN74LVC541A :
• Catalog: SN74LVC541A
• Automotive: SN74LVC541A-Q1, SN74LVC541A-Q1
• Enhanced Product: SN74LVC541A-EP, SN74LVC541A-EP
• Military: SN54LVC541A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74LVC541ADBR
SSOP
DB
20
2000
330.0
16.4
SN74LVC541ADGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74LVC541ADWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74LVC541ANSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LVC541APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
SN74LVC541APWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC541APWT
TSSOP
PW
20
250
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74LVC541ARGYR
VQFN
RGY
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC541ADBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74LVC541ADGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74LVC541ADWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LVC541ANSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LVC541APWR
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74LVC541APWR
TSSOP
PW
20
2000
364.0
364.0
27.0
SN74LVC541APWT
TSSOP
PW
20
250
367.0
367.0
38.0
SN74LVC541ARGYR
VQFN
RGY
20
3000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
www.ti.com
EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
GENERIC PACKAGE VIEW
RGY 20
VQFN - 1 mm max height
PLASTIC QUAD FGLATPACK - NO LEAD
3.5 x 4.5, 0.5 mm pitch
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4225264/A
www.ti.com
PACKAGE OUTLINE
RGY0020A
VQFN - 1 mm max height
SCALE 3.000
PLASTIC QUAD FLATPACK - NO LEAD
3.65
3.35
A
B
PIN 1 INDEX AREA
4.65
4.35
1.0
0.8
C
SEATING PLANE
0.05
0.00
0.08 C
2.05 0.1
2X 1.5
(0.2) TYP
10
11
9
EXPOSED
THERMAL PAD
12
14X 0.5
2X
3.5
21
SYMM
3.05 0.1
2
PIN 1 ID
19
20X
20
1
SYMM
0.30
0.18
0.1
0.05
0.5
20X
0.3
C A B
4225320/A 09/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2.05)
SYMM
1
20
20X (0.6)
2
19
20X (0.24)
(1.275)
(4.3)
21
SYMM
(3.05)
14X (0.5)
(0.775)
9
12
(R0.05) TYP
( 0.2) TYP
VIA
11
10
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4225320/A 09/2019
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RGY0020A
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
4X (0.92)
(R0.05) TYP
20
1
20X (0.6)
2
19
20X (0.24)
4X
(1.33)
21
SYMM
(4.3)
(0.77)
14X (0.5)
(0.56)
9
12
METAL
TYP
11
10
(0.75)
TYP
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 21
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
4225320/A 09/2019
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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