Texas Instruments | SNx4AHC594 8-Bit Shift Registers With Output Registers (Rev. G) | Datasheet | Texas Instruments SNx4AHC594 8-Bit Shift Registers With Output Registers (Rev. G) Datasheet

Texas Instruments SNx4AHC594 8-Bit Shift Registers With Output Registers (Rev. G) Datasheet
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SN54AHC594, SN74AHC594
SCLS423G – JUNE 1998 – REVISED JULY 2014
SNx4AHC594 8-Bit Shift Registers With Output Registers
1 Features
3 Description
•
•
The SNx4AHC594 devices contain an 8-bit serial-in,
parallel-out shift register that feeds an 8-bit D-type
storage register. Separate clocks and direct
overriding clear (SRCLR, RCLR) inputs are provided
on the shift and storage registers. A serial (QH′)
output is provided for cascading purposes.
1
•
•
•
•
Operating Range 2-V to 5.5-V VCC
8-Bit Serial-In, Parallel-Out Shift Registers with
Storage
Independent Direct Overriding Clears on Shift and
Storage Registers
Independent Clocks for Shift and Storage
Registers
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Device Information(1)
PART NUMBER
SNx4AHC594
BODY SIZE (NOM)
9.90 mm × 3.91 mm
SSOP (16)
6.20 mm × 5.30 mm
PDIP (16)
19.30 mm × 6.35 mm
SOP (16)
12.60 mm × 5.30 mm
TSSOP (16)
5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
PACKAGE
SOIC (16)
Network Switches
Power Infrastructures
PCs and Notebooks
LED Displays
Servers
Simplified Schematic
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
14
SER
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
R
3D Q
C3
15
R
3D Q
C3
1
R
3D Q
C3
2
R
3D Q
C3
3
R
3D Q
C3
4
R
3D Q
C3
5
R
3D Q
C3
6
R
3D Q
C3
7
QA
QB
QC
QD
QE
QF
QG
QH
9
QH′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN54AHC594, SN74AHC594
SCLS423G – JUNE 1998 – REVISED JULY 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
4
4
4
5
5
6
6
7
8
8
8
9
Absolute Maximum Ratings ......................................
Handling Ratings.......................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements, VCC = 3.3 V ± 0.3 V ..............
Timing Requirements, VCC = 5 V ± 0.5 V .................
Switching Characteristics, VCC = 3.3 V ± 0.3 V ........
Switching Characteristics, VCC = 5 V ± 0.5 V ...........
Noise Characteristics ..............................................
Operating Characteristics........................................
Typical Characteristics ............................................
Parameter Measurement Information ................ 10
8
Detailed Description ............................................ 11
8.1
8.2
8.3
8.4
9
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
11
11
12
12
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Application ................................................. 13
10 Power Supply Recommendations ..................... 14
11 Layout................................................................... 14
11.1 Layout Guidelines ................................................. 14
11.2 Layout Example .................................................... 14
12 Device and Documentation Support ................. 15
12.1
12.2
12.3
12.4
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
13 Mechanical, Packaging, and Orderable
Information ........................................................... 15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (September 2003) to Revision G
Page
•
Updated document to new TI data sheet standards. ............................................................................................................. 1
•
Deleted Ordering Information table. ....................................................................................................................................... 1
•
Added Applications. ................................................................................................................................................................ 1
•
Added Pin Functions table. .................................................................................................................................................... 3
•
Added Handling Ratings table. ............................................................................................................................................... 4
•
Changed MAX operating temperature from 85°C to 125°C in Recommended Operating Conditions table. ........................ 4
•
Added Thermal Information table. .......................................................................................................................................... 5
•
Added Typical Characteristics section. .................................................................................................................................. 9
•
Added Detailed Description section...................................................................................................................................... 11
•
Added Application and Implementation section. ................................................................................................................. 13
•
Added Power Supply Recommendations and Layout sections............................................................................................ 14
2
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Product Folder Links: SN54AHC594 SN74AHC594
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SCLS423G – JUNE 1998 – REVISED JULY 2014
5 Pin Configuration and Functions
2
15
3
14
4
13
5
12
6
11
7
10
8
9
QC
QB
VCC
QA
SER
RCLR
RCLK
SRCLK
SRCLR
QH′
QD
QE
NC
QF
QG
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
SER
RCLR
NC
RCLK
SRCLK
SRCLR
16
QH
1
GND
NC
Q H′
QB
QC
QD
QE
QF
QG
QH
GND
NC
VCC
QA
SN54AHC594 . . . FK PACKAGE
(TOP VIEW)
SN54AHC594 . . . J OR W PACKAGE
SN74AHC594 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
NC − No internal connection
Pin Functions
Pin
SN54AHC594
Name
GND
SN74AHC594
I/O
Description
8
—
Ground Pin
—
—
—
No connect
FK
J, W
D, DB, N,
NS, PW
10
8
1
NC
6
11
16
QA
19
15
15
O
QA Output
QB
2
1
1
O
QB Output
QC
3
2
2
O
QC Output
QD
4
3
3
O
QD Output
QE
5
4
4
O
QE Output
QF
7
5
5
O
QF Output
QG
8
6
6
O
QG Output
QH
9
7
7
O
QH Output
QH'
12
9
9
O
QH' Output
RCLK
15
12
12
I
RCLK Input
RCLR
17
13
13
I
RCLR Input
SER
18
14
14
I
SER Input
SRCLK
14
11
11
I
SRCLK Input
SRCLR
13
10
10
I
SRCLR Input
VCC
20
16
16
—
Power pin
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
–0.5
7
V
–0.5
VCC + 0.5
VI
Input voltage range
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±20
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
±75
mA
Continuous current through VCC or GND
(1)
(2)
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 Handling Ratings
Tstg
Storage temperature range
V(ESD)
(1)
(2)
Electrostatic discharge
MIN
MAX
UNIT
°C
–65
150
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (1)
0
2000
Charged device model (CDM), per JEDEC specification
JESD22-C101, all pins (2)
0
1000
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
SN54AHC594 (2)
VCC
Supply voltage
VIH
High-level input voltage
MAX
MIN
MAX
2
5.5
2
5.5
VCC = 2 V
1.5
VCC = 3 V
2.1
2.1
3.85
3.85
VCC = 5.5 V
VCC = 2 V
VIL
Low-level input voltage
VCC = 3 V
Input voltage
VO
Output voltage
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise and fall time
TA
Operating free-air temperature
(1)
(2)
4
V
V
0.5
0.9
0.9
1.65
1.65
0
5.5
0
5.5
0
VCC
0
V
V
VCC
V
–50
–50
µA
VCC = 3 V ± 0.3 V
–4
–4
VCC = 5.5 V ± 0.5 V
–8
–8
VCC = 2 V
VCC = 2 V
IOH
UNIT
1.5
0.5
VCC = 5.5 V
VI
SN74AHC594
MIN
50
50
VCC = 3 V ± 0.3 V
4
4
VCC = 5.5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3 V ± 0.3 V
VCC = 5.5 V ± 0.5 V
–55
125
–40
125
mA
µA
mA
ns/V
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, (SCBA004).
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6.4 Thermal Information
SN74AHC594
THERMAL METRIC (1)
D
DB
N
NS
PW
UNIT
16 PINS
RθJA
Junction-to-ambient thermal resistance
80.2
97.5
47.5
79.1
105.7
RθJC(top)
Junction-to-case (top) thermal resistance
39.1
47.7
34.9
35.4
40.4
RθJB
Junction-to-board thermal resistance
27.7
48.1
27.5
39.9
50.7
ψJT
Junction-to-top characterization parameter
9.9
9.8
19.8
5.4
3.7
ψJB
Junction-to-board characterization
parameter
37.4
47.6
27.4
39.5
50.1
RθJC(bot)
Junction-to-case (bottom) thermal
resistance
n/a
n/a
n/a
n/a
n/a
(1)
°C/W
For more information about traditional and new thermal metrics, see the TI application report IC Package Thermal Metrics (SPRA953).
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VOH
IOH = –4 mA
IOH = –8 mA
QA – QH
IOH = –8 mA
IOL = 50 µA
VOL
IOL = 4 mA
IOL = 8 mA
II
(1)
(2)
VI = VCC or
GND
Ci
VI = VCC or GND
TYP
2V
1.9
2
1.9
1.9
3V
2.9
3
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
3V
2.58
2.48
2.48
3.94
3.8
3.8
3.94
3.8
3.8
4.5 V
MAX
MIN
MAX
SN74AHC594
MIN
MIN
MAX
UNIT
V
2V
0.1
0.1
0.1
3V
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.36
0.5
0.44
0.36
0.5
0.44
±0.1
±1 (2)
±1
µA
4
40
40
µA
10
pF
0 to 5.5
V
IO = 0
SN54AHC594 (1)
TA = 25°C
4.5 V
VI = 5.5 V or GND
ICC
VCC
5.5 V
5V
2
10
V
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
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6.6 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
TA = 25°C
MIN
tw
Pulse Duration
RCLK or SRCLK high or low
th
(1)
(2)
Hold time,
data after CLK↑
MAX
MIN
5.5
5.5
5
5
5
3.5
3.5
3.5
8
8.5
8.5
8
9
9
SRCLR high (inactive) before SRCLK↑
4.2
4.8
4.8
RCLR high (inactive) before RCLK↑
4.6
5.3
5.3
SER after SRCLK↑
1.5
1.5
1.5
SRCLK↑ before RCLK↑
Setup time
MIN
SN74AHC594
5.5
RCLR or SRCLR low
SER before SRCLK↑
tsu
MAX
SN54AHC594 (1)
(2)
SRCLR low before SRCLK↑
MAX
UNIT
ns
ns
ns
Product Preview
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
6.7 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
TA = 25°C
MIN
tw
tsu
th
(1)
(2)
6
Pulse Duration
Setup time
Hold time,
data after CLK↑
RCLK or SRCLK high or low
SN54AHC594 (1)
MAX
MIN
MAX
SN74AHC594
MIN
5
5
5
RCLR or SRCLR low
5.2
5.2
5.2
SER before SRCLK↑
3
3
3
SRCLK↑ before RCLK↑ (2)
5
5
5
SRCLR low before SRCLK↑
5
5
5
SRCLR high (inactive) before SRCLK↑
2.9
3.3
3.3
RCLR high (inactive) before RCLK↑
3.2
3.7
3.7
2
2
2
SER after SRCLK↑
MAX
UNIT
ns
ns
ns
Product Preview
This setup time allows the storage register to receive stable data from the shift register. The clocks can be tied together, in which case
the shift register is one clock pulse ahead of the storage register.
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SCLS423G – JUNE 1998 – REVISED JULY 2014
SRCLK
SER
RCLK
SRCLR
RCLR
QA
QB
QC
QD
QE
QF
QG
QH
QH′
Figure 1. Timing Diagram
6.8 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
tPHL
tPLH
tPHL
tPHL
tPHL
TYP
CL = 15 pF
80 (2)
120 (1)
70 (2)
70
CL = 50 pF
55
105
50
50
tPLH
QA – QH
CL = 15 pF
SRCLK
QH'
CL = 15 pF
RCLR
QA – QH
QH'
MAX
MIN
MAX
MIN
MAX
MHz
4.6 (3)
8 (3)
1 (3)
8.5 (3)
1
8.5
(3)
(3)
(3)
8.8 (3)
1
8.8
4.9
8.2
1
UNIT
ns
5.4 (3)
9.1 (3)
1 (3)
9.7 (3)
1
9.7
5.5 (3)
9.2 (3)
1 (3)
9.9 (3)
1
9.9
CL = 15 pF
6 (3)
9.8 (3)
1 (3)
10.6 (3)
1
10.6
ns
CL = 15 pF
(3)
(3)
(3)
10 (3)
1
10
ns
5.6
9.2
1
6.9
10.5
1
11.1
1
11.1
8.1
11.9
1
13.1
1
13.1
7.7
11.7
1
12.4
1
12.4
8.4
12.5
1
13.9
1
13.9
ns
RCLK
QA – QH
CL = 50 pF
SRCLK
QH'
CL = 50 pF
tPHL
RCLR
QA – QH
CL = 50 pF
9.1
13.1
1
14.4
1
14.4
ns
tPHL
SRCLR
QH'
CL = 50 pF
8.5
12.4
1
14
1
14
ns
tPHL
tPLH
tPHL
(1)
(2)
(3)
RCLK
SRCLR
SN74AHC594
MIN
fmax
tPLH
SN54AHC594 (1)
TA = 25°C
LOAD
CAPACITANCE
ns
ns
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
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6.9 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tPLH
tPHL
tPLH
tPHL
tPHL
tPHL
tPLH
CL = 15 pF
135 (2)
170 (2)
115 (2)
115
CL = 50 pF
120
140
95
95
CL = 15 pF
SRCLK
QH'
CL = 15 pF
RCLR
QA – QH
QH'
MIN
MAX
MIN
MAX
MHz
3.3 (2)
6.2 (2)
1 (2)
6.5 (2)
1
6.5
(2)
(2)
(2)
(2)
1
6.9
3.7
6.5
1
6.9
UNIT
ns
3.7 (2)
6.8 (2)
1 (1)
7.2 (2)
1
7.2
4.1 (2)
7.2 (2)
1 (2)
7.6 (2)
1
7.6
CL = 15 pF
4.5 (2)
7.6 (2)
1 (2)
8.2 (2)
1
8.2
ns
CL = 15 pF
(2)
(2)
(2)
7.6 (2)
1
7.6
ns
4.1
7.1
1
4.9
7.8
1
8.3
1
8.3
5.8
8.9
1
9.7
1
9.7
5.5
8.6
1
9.1
1
9.1
6
9.2
1
10.1
1
10.1
ns
RCLK
QA – QH
CL = 50 pF
SRCLK
QH'
CL = 50 pF
tPHL
RCLR
QA – QH
CL = 50 pF
6.6
10
1
10.7
1
10.7
ns
tPHL
SRCLR
QH'
CL = 50 pF
6
9.2
1
10.1
1
10.1
ns
tPHL
tPLH
tPHL
(1)
(2)
TYP
QA – QH
MAX
SN74AHC594
MIN
RCLK
SRCLR
SN54AHC594 (1)
TA = 25°C
ns
ns
Product Preview
On products compliant to MIL-PRF-38535, this parameter is not production tested.
6.10 Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (1)
SN74AHC594
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
1
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.6
V
VOH(V)
Quiet output, minimum dynamic VOH
3.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
3.5
V
1.5
V
TYP
UNIT
112
pF
Characteristics are for surface-mount packages only.
6.11 Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
8
Power dissipation capacitance
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TEST CONDITIONS
No load,
f = 1 MHz
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6.12 Typical Characteristics
6
8
TPD in ns
7
5
6
TPD (ns)
TPD (ns)
4
3
5
4
3
2
2
1
1
TPD in ns
0
-100
0
-50
0
50
Temperature (qC)
100
150
0
1
D001
Figure 2. SN74AHC594 TPD vs Temperature, 15 pF Load
RCLK to Q
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2
3
VCC (V)
4
5
6
D002
Figure 3. TPD vs VCC
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7 Parameter Measurement Information
From Output
Under Test
Test
Point
From Output
Under Test
RL = 1 kΩ
S1
VCC
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
50% VCC
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
50% VCC
VCC
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 4. Load Circuit and Voltage Waveforms
10
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Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC594 SN74AHC594
SN54AHC594, SN74AHC594
www.ti.com
SCLS423G – JUNE 1998 – REVISED JULY 2014
8 Detailed Description
8.1 Overview
The SNx4AHC594 devices contain an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding clear (SRCLR, RCLR) inputs are provided on the shift and storage
registers. A serial (QH′) output is provided for cascading purposes. The shift register (SRCLK) and storage
register (RCLK) clocks are positive-edge triggered. If the clocks are tied together, the shift register always is one
clock pulse ahead of the storage register.
8.2 Functional Block Diagram
13
RCLR
12
RCLK
10
SRCLR
11
SRCLK
14
SER
1D Q
C1
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
2D Q
C2
R
R
3D Q
C3
15
R
3D Q
C3
1
R
3D Q
C3
2
R
3D Q
C3
3
R
3D Q
C3
4
R
3D Q
C3
5
R
3D Q
C3
6
R
3D Q
C3
7
QA
QB
QC
QD
QE
QF
QG
QH
9
QH′
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC594 SN74AHC594
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11
SN54AHC594, SN74AHC594
SCLS423G – JUNE 1998 – REVISED JULY 2014
www.ti.com
8.3 Feature Description
•
•
•
Allows for down translation
– Inputs are tolerant up to 5.5 V
Slow edges for reduced noise
Low power
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
12
FUNCTION
SER
SRCLK
SRCLR
RCLK
RCLR
X
X
L
X
X
Shift register is cleared.
L
↑
H
X
X
First stage of shift register goes low.
Other stages store the data of previous stage, respectively.
H
↑
H
X
X
First stage of shift register goes high.
Other stages store the data of previous stage, respectively.
L
↓
H
X
X
Shift register state is not changed.
X
X
X
X
L
Storage register is cleared.
X
X
X
↑
H
Shift register data is stored in the storage register.
X
X
X
↓
H
Storage register state is not changed.
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Product Folder Links: SN54AHC594 SN74AHC594
SN54AHC594, SN74AHC594
www.ti.com
SCLS423G – JUNE 1998 – REVISED JULY 2014
9 Application and Implementation
9.1 Application Information
The SN74AHC594 is a low-drive CMOS device that can be used for a multitude of bus interface type applications
where output ringing is a concern. The low drive and slow edge rates will minimize overshoot and undershoot on
the outputs. The inputs accept voltages up to 5.5 V allowing down translation to the VCC level. Figure 6 shows
how the slower edges can reduce ringing on the output compared to higher drive parts like AC.
QA
VCC
11
10
13
QC
RCLK
QE
QF
OE
QG
QH
8
1K
R9
SRCLR
QB
QD
12
µC
SRCLK
GND
QH’
16
15
270
LED2
R3
270
LED3
R4
270
LED4
R5
270
LED5
R6
270
LED6
R7
270
LED7
R8
270
LED8
1
2
3
4
5
6
7
9
SN74AHC594
VCC
GND
GND
VCC
GND
SER
GND
R2
IC1
14
GND
LED1
GND
270
GND
R1
GND
VCC
GND
9.2 Typical Application
Figure 5. Typical Application Schematic
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus
contention because it can drive currents that would exceed maximum limits. Outputs can be combined to
produce higher drive but the high drive will also create faster edges into light loads, so routing and load
conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs: See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels: See (VIH and VIL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as 5.5 V at any valid VCC.
2. Recommend Output Conditions
– Load currents should not exceed 25 mA per output and 75 mA total for the part.
– Outputs should not be pulled above VCC.
Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC594 SN74AHC594
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13
SN54AHC594, SN74AHC594
SCLS423G – JUNE 1998 – REVISED JULY 2014
www.ti.com
Typical Application (continued)
9.2.3 Application Curves
AC594
HC594
AHC594
Figure 6. Switching Characteristics Comparison
10 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the
Recommended Operating Conditions table.
Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single
supply, 0.1 μF is recommended; if there are multiple VCC pins, then 0.01 μF or 0.022 μF is recommended for
each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF
and a 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as
possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple-bit logic devices, inputs should never float.
In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two
inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. Figure 7 specifies the rules that must be observed under all circumstances. All unused inputs of digital
logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should
be applied to any particular unused input depends on the function of the device. Generally they will be tied to
GND or VCC, whichever makes more sense or is more convenient. It is generally acceptable to float outputs,
unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the output section of the
part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.
11.2 Layout Example
Vcc
Unused Input
Input
Output
Output
Unused Input
Input
Figure 7. Layout Diagram
14
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Product Folder Links: SN54AHC594 SN74AHC594
SN54AHC594, SN74AHC594
www.ti.com
SCLS423G – JUNE 1998 – REVISED JULY 2014
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
SN54AHC594
Click here
Click here
Click here
Click here
Click here
SN74AHC594
Click here
Click here
Click here
Click here
Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 1998–2014, Texas Instruments Incorporated
Product Folder Links: SN54AHC594 SN74AHC594
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15
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC594D
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC594
SN74AHC594DBR
ACTIVE
SSOP
DB
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA594
SN74AHC594DG4
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC594
SN74AHC594DR
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC594
SN74AHC594DRG4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC594
SN74AHC594N
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC594N
SN74AHC594NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC594
SN74AHC594PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA594
SN74AHC594PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA594
SN74AHC594PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA594
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
(4)
24-Aug-2018
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AHC594DR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
SN74AHC594NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHC594PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
20-Dec-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC594DR
SOIC
D
16
2500
333.2
345.9
28.6
SN74AHC594NSR
SO
NS
16
2000
367.0
367.0
38.0
SN74AHC594PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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