Texas Instruments | SN54AHC74, SN74AHC74 (Rev. K) | Datasheet | Texas Instruments SN54AHC74, SN74AHC74 (Rev. K) Datasheet

Texas Instruments SN54AHC74, SN74AHC74 (Rev. K) Datasheet
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
Dual Positive-Edge-Triggered D-Type Flip-Flops With Clear and Preset
Check for Samples: SN54AHC74, SN74AHC74
FEATURES
DESCRIPTION
•
•
The ’AHC74 dual positive-edge-triggered devices are
D-type flip-flops.
1
•
Operating Range 2-V to 5.5-V VCC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
A low level at the preset (PRE) or clear (CLR) inputs
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2013, Texas Instruments Incorporated
SN54AHC74, SN74AHC74
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Table 1. Function Table (Each Flip-Flop)
INPUTS
(1)
2
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high)
level.
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
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SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
UNIT
Supply voltage range, VCC
–0.5 V to 7 V
Input voltage range, VI ( (2))
–0.5 V to 7 V
Output voltage range, VO ( (2))
–0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0)
–20 mA
Output clamp current, IOK (VO < 0 or VO > VCC)
±20 mA
Continuous output current, IO (VO = 0 to VCC)
±25 mA
Continuous current through VCC or GND
±50 mA
D package
Package thermal impedance, ΘJA
86°C/W
DB package (3)
96°C/W
DGV package (3)
127°C/W
N package (3)
80°C/W
NS package (3)
76°C/W
PW package (3)
113°C/W
RGY package (4)
47°C/W
Storage temperature range, Tstg
(1)
(2)
(3)
(4)
–65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions (1)
SN54AHC74
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
VCC = 3V
VCC = 5.5 V
VIL
Low-level input voltage
MAX
2
5.5
1.5
MIN
MAX
2
5.5
UNIT
V
1.5
2.1
2.1
3.85
3.85
V
VCC = 2 V
0.5
VCC = 3 V
0.9
0.9
1.65
1.65
VCC = 5.5 V
0.5
V
VI
Input voltage
0
5.5
0
5.5
VO
Output voltage
0
VCC
0
VCC
V
–50
–50
µA
VCC = 3.3 V ± 0.3 V
–4
–4
VCC = 5 V ± 0.5 V
–8
–8
VCC = 2 V
VCC = 2 V
IOH
IOL
(1)
SN74AHC74
MIN
High-level output current
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
50
50
VCC = 3.3 V ± 0.3 V
4
4
VCC = 5 V ± 0.5 V
8
8
100
100
20
20
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
–55
125
–40
V
mA
µA
mA
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
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SN54AHC74, SN74AHC74
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
2V
1.9
2
1.9
1.9
1.9
3V
2.9
3
2.9
2.9
2.9
4.5 V
4.4
4.5
4.4
4.4
4.4
IOH = -4 mA
3V
2.58
2.48
2.48
2.48
IOH = -8 mA
4.5 V
3.94
(1)
VI = VCC or GND
3.8
MIN
UNIT
MAX
V
3.8
0.1
0.1
3V
0.1
0.1
0.1
0.1
4.5 V
0.1
0.1
0.1
0.1
3V
0.36
0.5
0.44
0.5
4.5 V
0.36
0.5
0.44
0.5
0 V to 5.5 V
±0.1
±1 (1)
±1
±1
µA
2
20
20
20
µA
IOH = 8 mA
Ci
3.8
MAX
0.1
IOL = 4 mA
ICC
MIN
0.1
VOL
VI = VCC or
GND,
MAX
2V
IOL = 50 mA
VI = 5.5 V or GND
MIN
–40°C to 125°C
SN74AHC74
TYP
VOH
MAX
–40°C to 85°C
SN74AHC74
MIN
IOH = -50 mA
II
–55°C to 125°C
SN54AHC74
TA = 25°C
VCC
IO = 0
5.5 V
5V
2
10
10
V
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
MAX
SN54AHC74
MIN
MAX
–40°C to 85°C
SN74AHC74
MIN
MAX
–40°C to 125°C
SN74AHC74
MIN
PRE or CLR low
6
7
7
7
CLK
6
7
7
7
Data
6
7
7
7
PRE or CLR inactive
5
5
5
5
0.5
0.5
0.5
0.5
UNIT
MAX
ns
ns
ns
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
4
MAX
SN54AHC74
MIN
MAX
–40°C to 85°C
SN74AHC74
MIN
MAX
–40°C to 125°C
SN74AHC74
MIN
PRE or CLR low
5
5
5
5
CLK
5
5
5
5
Data
5
5
5
5
PRE or CLR inactive
3
3
3
3
0.5
0.5
0.5
0.5
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UNIT
MAX
ns
ns
ns
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
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SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
(1)
TA = 25°C
LOAD
CAPACITANCE
MIN
TYP
CL = 15 pF
80 (1)
125 (1)
CL = 50 pF
50
75
PRE or CLR
Q or Q
CL = 15 pF
CLK
Q or Q
CL = 15 pF
PRE or CLR
Q or Q
CL = 50 pF
CLK
Q or Q
CL = 50 pF
7.6
–40°C to
85°C
SN74AHC74
SN54AHC74
MAX
MIN
MAX
70 (1)
45
(1)
12.3
(1)
1
(1)
14.5
(1)
MIN
MAX
–40°C to
125°C
SN74AHC74
MIN
70
70
45
45
UNIT
MAX
MHz
1
14.5
1
14.5
7.6
12.3
1 (1)
14.5 (1)
1
14.5
1
14.5
6.7
11.9
1 (1)
14 (1)
1
14
1
14
6.7
11.9
1 (1)
14 (1)
1
14
1
14
10.1
15.8
1
18
1
18
1
18
10.1
15.8
1
18
1
18
1
18
9.2
15.4
1
17.5
1
17.5
1
17.5
9.2
15.4
1
17.5
1
17.5
1
17.5
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
fmax
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
(1)
TA = 25°C
SN54AHC74
MIN
TYP
130 (1)
170 (1)
110 (1)
110
110
CL = 50 pF
90
115
75
75
75
Q or Q
CL = 15 pF
CLK
Q or Q
CL = 15 pF
PRE or CLR
Q or Q
CL = 50 pF
CLK
Q or Q
CL = 50 pF
MIN
MAX
MIN
MAX
–40°C to
125°C
SN74AHC74
CL = 15 pF
PRE or CLR
MAX
–40°C to
85°C
SN74AHC74
MIN
MAX
MHz
4.8 (1)
7.7 (1)
1 (1)
9 (1)
1
9
1
9
(1)
(1)
(1)
9 (1)
1
9
1
9
4.8
7.7
1
4.6 (1)
7.3 (1)
1 (1)
8.5 (1)
1
8.5
1
8.5
(1)
(1)
(1)
8.5 (1)
1
8.5
1
8.5
4.6
7.3
1
UNIT
6.3
9.7
1
11
1
11
1
11
6.3
9.7
1
11
1
11
1
11
6.1
9.3
1
10.5
1
10.5
1
10.5
6.1
9.3
1
10.5
1
10.5
1
10.5
ns
ns
ns
ns
On products compliant to MIL-PRF-38535, this parameter is not production tested.
Noise Characteristics
VCC = 5 V, CL = 50 pF, TA = 25°C (see
(1)
)
SN74AHCT74
PARAMETER
MIN
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
4.7
VIH(D)
High-level dynamic input voltage
3.5
VIL(D)
Low-level dynamic input voltage
(1)
V
V
1.5
V
Characteristics are for surface-mount packages only.
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
f = 1 MHz
TYP
32
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UNIT
pF
5
SN54AHC74, SN74AHC74
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
www.ti.com
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
SN54AHC74, SN74AHC74
www.ti.com
SCLS255K – DECEMBER 1995 – REVISED DECEMBER 2013
REVISION HISTORY
Changes from Revision J (September 2002) to Revision K
Page
•
Updated document to new TI data sheet format. ................................................................................................................. 1
•
Added ESD warning. ............................................................................................................................................................ 2
•
Removed Ordering Information table. ................................................................................................................................... 2
•
Updated operating temperature range. ................................................................................................................................. 3
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHC74 SN74AHC74
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7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9686001Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629686001Q2A
SNJ54AHC
74FK
5962-9686001QCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686001QC
A
SNJ54AHC74J
5962-9686001QDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686001QD
A
SNJ54AHC74W
SN74AHC74D
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC74
SN74AHC74DBR
ACTIVE
SSOP
DB
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74DGVR
ACTIVE
TVSOP
DGV
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74DR
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC74
SN74AHC74DRE4
ACTIVE
SOIC
D
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC74
SN74AHC74N
ACTIVE
PDIP
N
14
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHC74N
SN74AHC74NSR
ACTIVE
SO
NS
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC74
SN74AHC74PW
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74PWG4
ACTIVE
TSSOP
PW
14
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74PWR
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74PWRG4
ACTIVE
TSSOP
PW
14
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HA74
SN74AHC74RGYR
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA74
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AHC74RGYRG4
ACTIVE
VQFN
RGY
14
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
HA74
SNJ54AHC74FK
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
59629686001Q2A
SNJ54AHC
74FK
SNJ54AHC74J
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686001QC
A
SNJ54AHC74J
SNJ54AHC74W
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9686001QD
A
SNJ54AHC74W
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHC74, SN74AHC74 :
• Catalog: SN74AHC74
• Enhanced Product: SN74AHC74-EP, SN74AHC74-EP
• Military: SN54AHC74
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74AHC74DGVR
TVSOP
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DGV
14
2000
330.0
12.4
6.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
4.0
1.6
8.0
12.0
Q1
SN74AHC74DR
SOIC
D
14
2500
330.0
16.4
6.5
9.0
2.1
8.0
16.0
Q1
SN74AHC74NSR
SO
NS
14
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
SN74AHC74PWR
TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHC74RGYR
VQFN
RGY
14
3000
330.0
12.4
3.75
3.75
1.15
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Dec-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC74DGVR
TVSOP
DGV
14
2000
367.0
367.0
35.0
SN74AHC74DR
SOIC
D
14
2500
367.0
367.0
38.0
SN74AHC74NSR
SO
NS
14
2000
367.0
367.0
38.0
SN74AHC74PWR
TSSOP
PW
14
2000
367.0
367.0
35.0
SN74AHC74RGYR
VQFN
RGY
14
3000
367.0
367.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
J0014A
CDIP - 5.08 mm max height
SCALE 0.900
CERAMIC DUAL IN LINE PACKAGE
PIN 1 ID
(OPTIONAL)
A
4X .005 MIN
[0.13]
.015-.060 TYP
[0.38-1.52]
1
14
12X .100
[2.54]
14X .014-.026
[0.36-0.66]
14X .045-.065
[1.15-1.65]
.010 [0.25] C A B
.754-.785
[19.15-19.94]
8
7
B
.245-.283
[6.22-7.19]
.2 MAX TYP
[5.08]
C
.13 MIN TYP
[3.3]
SEATING PLANE
.308-.314
[7.83-7.97]
AT GAGE PLANE
.015 GAGE PLANE
[0.38]
0 -15
TYP
14X .008-.014
[0.2-0.36]
4214771/A 05/2017
NOTES:
1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.
www.ti.com
EXAMPLE BOARD LAYOUT
J0014A
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE
(.300 ) TYP
[7.62]
SEE DETAIL A
SEE DETAIL B
1
14
12X (.100 )
[2.54]
SYMM
14X ( .039)
[1]
8
7
SYMM
LAND PATTERN EXAMPLE
NON-SOLDER MASK DEFINED
SCALE: 5X
.002 MAX
[0.05]
ALL AROUND
(.063)
[1.6]
METAL
( .063)
[1.6]
SOLDER MASK
OPENING
METAL
(R.002 ) TYP
[0.05]
.002 MAX
[0.05]
ALL AROUND
SOLDER MASK
OPENING
DETAIL A
DETAIL B
SCALE: 15X
13X, SCALE: 15X
4214771/A 05/2017
www.ti.com
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
0,15 M
15
0,25
0,09
8,20
7,40
5,60
5,00
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
2,00 MAX
0,10
0,05 MIN
PINS **
14
16
20
24
28
30
38
A MAX
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30
DIM
4040065 /E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0,15.
Falls within JEDEC MO-150
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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