Texas Instruments | Rad-Tolerant, Quadruple 2-Input Positive-NAND Gate (Rev. A) | Datasheet | Texas Instruments Rad-Tolerant, Quadruple 2-Input Positive-NAND Gate (Rev. A) Datasheet

Texas Instruments Rad-Tolerant, Quadruple 2-Input Positive-NAND Gate (Rev. A) Datasheet
SN54AC00-DIE
www.ti.com
SCHS391A – APRIL 2013 – REVISED NOVEMBER 2013
RAD-TOLERANT, QUADRUPLE 2-INPUT POSITIVE-NAND GATE
Check for Samples: SN54AC00-DIE
FEATURES
1
•
•
•
2-V to 6-V VCC Operation
Inputs Accept Voltages to 6 V
Max tpd of 7 ns at 5 V
DESCRIPTION/ORDERING INFORMATION
The SN54AC00-DIE device contains four independent 2-input NAND gates. Each gate performs the Boolean
function of Y = A • B or Y = A + B in positive logic.
ORDERING INFORMATION (1)
(1)
(2)
PRODUCT
PACKAGE
DESIGNATOR
PACKAGE
SN54AC00
TD
Bare die in waffle pack (2)
ORDERABLE PART NUMBER
PACKAGE QUANTITY
SN54AC00VTD1
100
SN54AC00VTD2
10
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Processing is per the Texas Instruments space production baseline and is in compliance with the Texas Instruments Quality Control
System in effect at the time of manufacture. Electrical screening consists of DC parametric and functional testing at room temperature
only. Unless otherwise specified by Texas Instruments AC performance and performance over temperature is not warranted. Visual
Inspection is performed in accordance with MIL-STD-883 Test Method 2010 Condition B at 75X minimum.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54AC00-DIE
SCHS391A – APRIL 2013 – REVISED NOVEMBER 2013
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BARE DIE INFORMATION
2
DIE THICKNESS
BACKSIDE FINISH
BACKSIDE
POTENTIAL
BOND PAD
METALLIZATION COMPOSITION
BOND PAD
THICKNESS
10.5 mils.
Silicon with backgrind
Floating
AlCuTiW
830 nm
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN54AC00-DIE
SN54AC00-DIE
www.ti.com
SCHS391A – APRIL 2013 – REVISED NOVEMBER 2013
Table 1. Bond Pad Coordinates in Microns
DESCRIPTION
PAD NUMBER
X MIN
Y MIN
X MAX
Y MAX
1A
1
96.25
510.5
201.25
615.5
1B
2
95
94
200
199
1Y
3
508
94
613
199
2A
4
1149
94
1254
199
2B
5
1562
94
1667
199
2Y
6
1841.5
145.5
1946.5
250.5
GND
7
1841.5
445.5
1946.5
550.5
3Y
8
1841
783
1946
888
3A
9
1750.5
991
1855.5
1096
3B
10
1176.5
991
1281.5
1096
4Y
11
921
991
1026
1096
4A
12
736
991
841
1096
4B
13
95
991
200
1096
VCC
14
102.5
692
207.5
797
xxx
REVISION HISTORY
Changes from Original (April 2013) to Revision A
Page
•
Changed bare die diagram ................................................................................................................................................... 2
•
Changed Bond Pad Coordinates .......................................................................................................................................... 3
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN54AC00-DIE
3
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN54AC00VTD1
ACTIVE
0
100
TBD
Call TI
N / A for Pkg Type
25 to 25
SN54AC00VTD2
ACTIVE
0
10
TBD
Call TI
N / A for Pkg Type
25 to 25
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
13-Jun-2019
OTHER QUALIFIED VERSIONS OF SN54AC00-DIE :
• Space: SN54AC00-SP
NOTE: Qualified Version Definitions:
• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
Addendum-Page 2
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