Texas Instruments | CF4320H (Rev. B) | Datasheet | Texas Instruments CF4320H (Rev. B) Datasheet

Texas Instruments CF4320H (Rev. B) Datasheet
CF4320H
www.ti.com
SCES655B – APRIL 2006 – REVISED AUGUST 2013
CompactFlash™ BUS-INTERFACE CHIP
WITH ±15-kV ESD PROTECTION, TRANSLATION, AND CARD-DETECT CIRCUITRY
Check for Samples: CF4320H
FEATURES
TARGET APPLICATIONS
•
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
±15-kV Human-Body Model (HBM) ESD
Protection on Card Side
Logic-Level Translation Between 1.8-V, 2.5-V,
3.3-V, and 5-V Supplies
Integrated Card-Detect Circuitry
Integrated Pullup/Pulldown Resistors Save
Board Space and Cost
Matched Pinout With CompactFlash™ (CF)
Connector Pin Configurations to Optimize PCB
Layout
Input-Disable Feature Allows Floating Input
Conditions
Ioff Supports Partial-Power-Down Mode
Operation
Offered in 114-Ball LFBGA Package for SpaceConstrained Applications
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Performance
– ±15-kV HBM
– ±4-kV IEC61000-4-2, Contact Discharge
(Latch-Up Immune)
GPS PDAs
PDA Phones
Industrial PDAs
High-End Digital Cameras
DESCRIPTION
The CF4320H is a CompactFlash™ (CF) interface
device designed to provide a single-chip solution for
CF card interfaces. Separate VCC rails for the systembus side and the CF connector-bus side allow
voltage-level shifting. This is helpful for interfacing
between a core chipset that may operate from 3.3 V
down to 1.65 V, and CF cards that operate from 3.3V or 5-V supply voltages. All the input buffers feature
the input-disable function, which allows conditional
floating input signals. The input, output, and I/O
buffers on the CF connector side have been defined
to comply with CF+ and CF specification revisions 1.4
and 2.0.
TYPICAL APPLICATION
VCC_CF
LDO
VIN
EN
CF+ Module
(GPS, WLAN, etc.)
Micro-Drive
Memory Card
Card Detect
Data
Address
Command
Status
CF Connector
±15-kV HBM ESD Protection
VCC_CF
VCC_S
Card-Detect
Circuitry
Data
BusTransceiver
Circuitry
Address
CF Controller
Command
Status
CF4320H
Host System
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
CompactFlash is a trademark of Sandisk Corporation.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
www.ti.com
CARD-DETECT CIRCUIT
The CF4320H has an integrated card-detect circuit that generates a LOW card-detect signal when a CF card is
plugged into the socket. This circuit is supplied by a separate power-supply pin, VCC_SD, which operates from
1.65 V to 5.5 V. The card-detect signal can be used to control a voltage regulator, which may power the CF slot
and the CF side of the CF4320H. The inputs to this circuitry (CD1 and CD2) have internal pullup resistors to pull
them to a HIGH logic state if there is no card in the CF slot. VCC_SD is particularly helpful when the core
processor operates at a low VCC, but the regulator needs a higher control-signal voltage.
Table 1. CARD-DETECT
SIGNALS
INPUTS
CD1
CD2
OUTPUT
SCD
L
L
L
L
H
H
H
L
H
H
H
H
BUS-TRANSCEIVER CIRCUIT
Command and Status Bits
Most CF controllers are embedded in processors or microcontrollers and use GPIOs to send command signals
and receive status signals from the card to manage operation. The CF interface consists of eight control signals
and six status signals. The CF standard requires that each of these signals have a 100-kΩ pullup resistor. The
CF4320H includes an internal 100-kΩ pullup resistor on the input of each of these signals, which saves board
real estate and lowers overall system cost
COMMAND LINE BUFFERS (1)
(BVD1, BVD2, INPACK, OE, IORD, IOWR,
READY, REG, CE1, CE2, WAIT, WE, WP)
INPUTS
(1)
MASTER_EN
BUF_EN
INPUT
L
L
H
OUTPUT
H
L
L
L
L
L
H
X
Z, Command line buffer inputs can float.
H
X
X
Z, low-power mode
X = H or L
RESET (1)
INPUTS
MASTER_EN
SRESET
OUTPUT
RESET
L
H
H
L
L
L
H
X
Z, low-power mode
(1)
X = H or L
Data Bits
The CF4320H has 16 data lines organized as two groups of 8 bits each. The ENL signal controls the lower 8 bits
(D07–D00), while the ENH signal controls the upper 8 bits (D15–D08).
2
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LOWER 8-BIT DATA BUS TRANSCEIVERS (1)
(D07–D00, SD07–SD00)
INPUTS
(1)
MASTER_EN
ENL
DIR (S/CF)
L
L
H
OPERATION
SD data to D bus
L
L
L
D data to SD bus
L
H
X
Isolation. D07–D00 and SD07–SD00 inputs can float.
H
X
X
Isolation, low-power mode
X = H or L
UPPER 8-BIT DATA BUS TRANSCEIVERS (1)
(D15–D08, SD15–SD08)
INPUTS
(1)
MASTER_EN
ENH
DIR (S/CF)
L
L
H
OPERATION
SD data to D bus
L
L
L
D data to SD bus
L
H
X
Isolation. D15–D08 and SD15–SD08 inputs can float.
H
X
X
Isolation, low-power mode
X = H or L
Address Bits
The CF4320H has 11 unidirectional address bits flowing from the system to the CF card.
ADDRESS BUS BUFFERS (1)
INPUTS
MASTER_EN
BUF_EN
SA
OUTPUT
A
L
L
H
H
L
L
L
L
L
H
X
Z, SA inputs can float.
H
X
X
Z, low-power mode
(1)
X = H or L
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CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
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Direction Signal Bit
The DIR(S/CF) input controls the data direction between the system bus and the CF card. The CF4320H has
circuitry to generate a DIR_OUT signal using the SOE and SIORD signals. DIR(S/CF) and DIR_OUT are placed
adjacent to each other, which is convenient for connecting DIR(S/CF) and DIR_OUT, if DIR_OUT is used. This
saves an additional signal from the system controller to control the data direction. When either SOE or SIORD is
low, the data direction is from the CF card side to the system side (DIR_OUT = L).
DIR_OUT (1)
INPUTS
(1)
4
SIORD
OUTPUT
DIR_OUT
L
L
L
L
H
L
L
H
L
L
H
BUF_EN
MASTER_EN
SOE
L
L
L
L
L
L
L
H
H
H
L
X
X
L
X
H
X
X
Z, low-power mode
X = H or L
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
BOARD-OPTIMIZED PIN CONFIGURATION
GKF OR ZKF PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
D12
D04
D03
SD14
SD12
SD11
B
D13
D05
D11
SD13
SD10
SD09
C
D14
D06
SD15
SINPACK
SD08
SD07
D
D15
D07
VCC_CF
VCC_S
SD06
SD05
E
CE2
CE1
GND
GND
SD04
SD03
F
OE
A10
VCC_CF
VCC_S
SD02
SD01
G
A09
IORD
GND
GND
SD00
SCE1
H
A08
IOWR
VCC_CF
VCC_S
ENL
ENH
J
A07
WE
GND
GND
MASTER_EN
BUF_EN
K
A06
READY
A05
SCE2
SOE
SIORD
L
A04
RESET
GND
GND
SWE
SIOWR
M
A03
WAIT
VCC_CF
VCC_S
SREADY
SRESET
N
A02
INPACK
GND
GND
SWAIT
SREG
SBVD1
P
A01
REG
VCC_CF
GND
SBVD2
R
A00
BVD2
VCC_CF
VCC_S
SA10
SWP
T
D00
BVD1
VCC_SD
DIR(S/CF)
SA08
SA09
U
D01
D08
CD1
DIR_OUT
SA06
SA07
V
D02
D09
CD2
SA00
SA04
SA05
W
WP
D10
SCD
SA01
SA02
SA03
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
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TERMINAL FUNCTIONS
TERMINAL
REFERENCED
TO
I/O (1)
Data bit 12 connected to card
VCC_CF
I/O
Data bit 13 connected to card
VCC_CF
I/O
D14
Data bit 14 connected to card
VCC_CF
I/O
D15
Data bit 15 connected to card
VCC_CF
I/O
E1
CE2
Card enable connected to card
VCC_CF
O
F1
OE
Output enable connected to card
VCC_CF
O
G1
A09
Address bit 9 connected to card
VCC_CF
O
H1
A08
Address bit 8 connected to card
VCC_CF
O
J1
A07
Address bit 7 connected to card
VCC_CF
O
K1
A06
Address bit 6 connected to card
VCC_CF
O
L1
A04
Address bit 4 connected to card
VCC_CF
O
M1
A03
Address bit 3 connected to card
VCC_CF
O
N1
A02
Address bit 2 connected to card
VCC_CF
O
P1
A01
Address bit 1 connected to card
VCC_CF
O
R1
A00
Address bit 0 connected to card
VCC_CF
O
T1
D00
Data bit 0 connected to card
VCC_CF
I/O
U1
D01
Data bit 1 connected to card
VCC_CF
I/O
V1
D02
Data bit 2 connected to card
VCC_CF
I/O
W1
WP
Write protect connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
A2
D04
Data bit 4 connected to card
VCC_CF
I/O
B2
D05
Data bit 5 connected to card
VCC_CF
I/O
C2
D06
Data bit 6 connected to card
VCC_CF
I/O
D2
D07
Data bit 7 connected to card
VCC_CF
I/O
E2
CE1
Card enable connected to card
VCC_CF
O
F2
A10
Address bit 10 connected to card
VCC_CF
O
G2
IORD
I/O read connected to card
VCC_CF
O
H2
IOWR
I/O write connected to card
VCC_CF
O
J2
WE
Write enable connected to card
VCC_CF
O
K2
READY
Ready connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
L2
RESET
Reset connected to card
VCC_CF
O
M2
WAIT
Wait connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
N2
INPACK
Input acknowledge connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
P2
REG
Register connected to card
VCC_CF
O
R2
BVD2
BVD2 connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
T2
BVD1
BVD1 connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_CF
I
U2
D08
Data bit 8 connected to card
VCC_CF
I/O
V2
D09
Data bit 9 connected to card
VCC_CF
I/O
W2
D10
Data bit 10 connected to card
VCC_CF
I/O
A3
D03
Data bit 3 connected to card
VCC_CF
I/O
B3
D11
Data bit 11 connected to card
VCC_CF
I/O
C3
SD15
Data bit 15 connected to controller
VCC_S
D3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
E3
GND
Ground
F3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
G3
GND
Ground
NO.
NAME
A1
D12
B1
D13
C1
D1
(1)
6
DESCRIPTION
I/O
Power
Power
I = input, O = output, I/O = input/output
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TERMINAL FUNCTIONS (continued)
TERMINAL
REFERENCED
TO
DESCRIPTION
I/O (1)
NO.
NAME
H3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
J3
GND
Ground
K3
A05
Address bit 5 connected to card
L3
GND
Ground
M3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
N3
GND
Ground
P3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
Power
R3
VCC_CF
Card-side supply voltage. VCC_CF powers all card-side inputs, outputs, and I/Os.
Power
T3
VCC_SD
Card-detect supply voltage. VCC_SD powers the card-detect circuitry.
U3
CD1
Card detect connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_SD
V3
CD2
Card detect connected to card. Pulled up to VCC_CF through 100 kΩ.
VCC_SD
I
W3
SCD
Card detect connected to controller
VCC_SD
O
A4
SD14
Data bit 14 connected to controller
VCC_S
I/O
B4
SD13
Data bit 13 connected to controller
VCC_S
I/O
C4
SINPACK
Input acknowledge connected to controller
VCC_S
I/O
D4
VCC_S
Controller-side supply voltage. VCC_S powers all controller-side inputs, outputs,
and I/Os.
E4
GND
Ground
F4
VCC_S
Controller-side supply voltage. VCC_S powers all controller-side inputs, outputs,
and I/Os.
G4
GND
Ground
H4
VCC_S
Controller-side supply voltage. VCC_S powers all controller-side inputs, outputs,
and I/Os.
J4
GND
Ground
K4
SCE2
Card enable connected to controller
L4
GND
Ground
M4
VCC_S
Controller-side supply voltage. VCC_S powers all controller-side inputs, outputs,
and I/Os.
N4
GND
Ground
P4
GND
Ground
R4
VCC_S
Controller-side supply voltage. VCC_S powers all controller-side inputs, outputs,
and I/Os.
T4
DIR(S/CF)
Direction controls flow of data from system to CF and vice-versa
VCC_S
I
U4
DIR_OUT
Data direction generated by CF4320H. Can be connected to DIR(S/CF).
VCC_S
O
V4
SAO0
Address bit 0 connected to controller
VCC_S
I
W4
SAO1
Address bit 1 connected to controller
VCC_S
I
A5
SD12
Data bit 12 connected to controller
VCC_S
I/O
B5
SD10
Data bit 10 connected to controller
VCC_S
I/O
C5
SD08
Data bit 8 connected to controller
VCC_S
I/O
D5
SD06
Data bit 6 connected to controller
VCC_S
I/O
E5
SD04
Data bit 4 connected to controller
VCC_S
I/O
F5
SD02
Data bit 2 connected to controller
VCC_S
I/O
G5
SD00
Data bit 0 connected to controller
VCC_S
I/O
H5
ENL
Enable for data bits 0–7. Pulled up to VCC_S through 100 kΩ.
VCC_S
I
J5
MASTER_EN
Enable for all transceivers and buffers except the card-detect circuitry
VCC_S
I
K5
SOE
Output enable connected to controller
VCC_S
I
L5
SWE
Write enable connected to controller
VCC_S
I
M5
SREADY
Ready connected to controller
VCC_S
O
Power
VCC_CF
O
Power
Power
I
Power
Power
Power
VCC_S
I
Power
Power
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TERMINAL FUNCTIONS (continued)
TERMINAL
REFERENCED
TO
I/O (1)
Wait connected to controller
VCC_S
O
BVD2 connected to controller
VCC_S
O
SA10
Address bit 10 connected to controller
VCC_S
I
T5
SA08
Address bit 8 connected to controller
VCC_S
I
U5
SA06
Address bit 6 connected to controller
VCC_S
I
V5
SA04
Address bit 4 connected to controller
VCC_S
I
W5
SA02
Address bit 2 connected to controller
VCC_S
I
A6
SD11
Data bit 11 connected to controller
VCC_S
I/O
B6
SD09
Data bit 9 connected to controller
VCC_S
I/O
C6
SD07
Data bit 7 connected to controller
VCC_S
I/O
D6
SD05
Data bit 5 connected to controller
VCC_S
I/O
E6
SD03
Data bit 3 connected to controller
VCC_S
I/O
F6
SD01
Data bit 1 connected to controller
VCC_S
I/O
G6
SCE1
Card enable connected to controller
VCC_S
I
H6
ENH
Enable for data bits 8–15. Pulled up to VCC_S through 100 kΩ.
VCC_S
I
J6
BUF_EN
Enable for address and control/status lines. Pulled up to VCC_S through 100 kΩ.
VCC_S
I
K6
SIORD
I/O read connected to controller
VCC_S
I
L6
SIOWR
I/O write connected to controller
VCC_S
I
M6
SRESET
Reset connected to controller
VCC_S
I
N6
SREG
Register connected to controller
VCC_S
I
P6
SBVD1
BVD1 connected to controller
VCC_S
O
R6
SWP
Write protect connected to controller
VCC_S
O
T6
SA09
Address bit 9 connected to controller
VCC_S
I
U6
SA07
Address bit 7 connected to controller
VCC_S
I
V6
SA05
Address bit 5 connected to controller
VCC_S
I
W6
SA03
Address bit 3 connected to controller
VCC_S
I
NO.
NAME
N5
SWAIT
P5
SBVD2
R5
8
DESCRIPTION
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
LOGIC DIAGRAM
VCC_SD
VCC_SD
R INT
CD1
VCC_SD
SCD
R INT
CD2
VCC_CF
VCC_S
SIORD−INT
SOE−INT
DIR_OUT
DIR(S/CF)
VCC_S
R INT
ENL
MASTER_EN
D07−D00
8
8
SD07−SD00
To 7 Other Channels
VCC_S
N
To 7 Other Channels
O
R INT
A
T
I
ENH
8
L
8
SD15−SD08
To 7 Other Channels
R
A
To 7 Other Channels
N
S
D15−D08
RESET
SRESET
T
VCC_S
R INT
BUF_EN
A10−A00
11
11
SIORD−INT
SOE−INT
CE1, CE2, IORD,
IOWR, OE, REG, WE
BVD1, BVD2, INPACK,
READY, WAIT, WP
SA10−SA00
2
7
7
VCC_CF
R INT
6
6
SCE1, SCE2, SIORD,
SIOWR, SOE, SREG,
SWE
SBVD1, SBVD2, SINPACK,
SREADY, SWAIT, SWP
NOTE: R INT ≥ 100 kΩ
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TPS766xx
VCC_CF
R1
3.3 KW
1
2
5
C1
0.1 µF
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6
NC/FB
PG
EN
OUT
IN
OUT
IN
GND
4
7
VCC_CF
8
3
4.7 µF
3D
3F
3H
3M
3P
3R
3W
3U
3V
VCC_CF
GND
CD1
D03
D11
D04
D12
D05
D13
D06
D14
D07
D15
CE1
CE2
A10
VS1
OE
IORD
A09
IOWR
A08
WE
A07
READY
VCC
VCC
A06
CSEL
A05
VS2
A04
RESET
A03
WAIT
A02
INPACK
A01
REG
A00
BVD2
D00
BVD1
D01
D08
D02
D09
WP
D10
CD2
GND
1
26
2
27
3
28
4
29
5
30
6
31
7
32
8
33
9
34
10
35
11
36
12
37
13
38
14
39
15
40
16
41
17
42
18
43
19
44
20
45
21
46
22
47
23
48
24
49
25
50
CD1
D03
D11
D04
D12
D05
D13
D06
D14
D07
D15
CE1
CE2
A10
VS1
OE
IORD
A09
IOWR
A08
WE
A07
READY
A06
CSEL
A05
VS2
A04
RESET
A03
WAIT
A02
INPACK
A01
REG
A00
BVD2
D00
BVD1
D01
D08
D02
D09
WP
D10
CD2
J1
67155-CF CONNECTOR
10
VCC_SYS
C2
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
RESET
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
CE1
CE2
IORD
IOWR
OE
REG
WE
BVD1
BVD2
INPACK
READY
WAIT
WP
1T
1U
1V
3A
2A
2B
2C
2D
2U
2V
2W
3B
1A
1B
1C
1D
2L
1R
1P
1N
1M
1L
3K
1K
1J
1H
1G
2F
2E
1E
2G
2H
1F
2P
2J
2T
2R
2N
2K
2M
1W
3E
3G
3J
3L
3N
U1
VCC_CF
VCC_S
VCC_CF
VCC_S
VCC_CF
VCC_S
VCC_CF
VCC_S
VCC_CF
VCC_S
VCC_CF
VCC_S
SCD
CD1
CD2
MASTER_EN
BUF_EN
DIR(S/CF)
DIR_OUT
EN_L
EN_H
D00
SD00
D01
SD01
D02
SD02
D03
SD03
D04
SD04
D05
SD05
D06
SD06
D07
SD07
D08
SD08
D09
SD09
D10
SD10
D11
SD11
D12
SD12
D13
SD13
D14
SD14
D15
SD15
RESET
SRESET
A00
SA00
A01
SA01
A02
SA02
A03
SA03
A04
SA04
A05
SA05
A06
SA06
A07
SA07
A08
SA08
A09
SA09
A10
SA10
CE1
SCE1
CE2
SCE2
IORD
SIORD
IOWR
SIOWR
OE
SOE
REG
SREG
WE
SWE
BVD1
SBVD1
BVD2
SBVD2
INPACK
SINPACK
READY
SREADY
WAIT
SWAIT
WP
SWP
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
3T
4D
4F
4H
4M
4R
5J
6J
4T
4U
5H
6H
5G
6F
5F
6E
5E
6D
5D
6C
5C
6B
5B
6A
5A
4B
4A
3C
6M
4V
4W
5W
6W
5V
6V
5U
6U
5T
6T
5R
6G
4K
6K
6L
5K
6N
5L
6P
5P
4C
5M
5N
6R
4E
4G
4L
4N
4P
C3
0.1 µF
U2
VCC_S
MASTER_EN
BUF_EN
EN_L
EN_H
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
RESET
ADD_0
ADD_1
ADD_2
ADD_3
ADD_4
ADD_5
ADD_6
ADD_7
ADD_8
ADD_9
ADD_10
CE1
CE2
IORD
IOWR
OE
REG
WE
BVD1
BVD2
INPACK
READY
WAIT
WP
GND
CF_PROCESSOR
CF4320H
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
–0.5
4.6
–0.5
6.5
SD, SA (2)
–0.5
4.6
D, A
–0.5
6.5
SCE1, SCE2, SIORD,
SIOWR, SOE, SREG, SWE
–0.5
4.6
BVD1, BVD2, READY,
INPACK, WAIT, WP
–0.5
6.5
DIR(S/CF), MASTER_EN,
ENL, ENH
–0.5
4.6
VCC_S
VCC_CF
VCC_SD
Supply voltage range
I/O ports
VI
Input voltage range
Input ports
Control ports
UNIT
V
V
Voltage range applied to any output
in the high-impedance or power-off
state (2)
System port
–0.5
4.6
VO
CF port
–0.5
6.5
VO
Voltage range applied to any output
in the high or low state (2) (3)
System port
–0.5
VCC_S + 0.5
CF port
–0.5
VCC_CF + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
Continuous current through each VCC_S, VCC_CF, VCC_SD, or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
±100
–65
V
V
mA
36
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 6.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Recommended Operating Conditions (1)
(2) (3)
MIN
MAX
VCC_SD
Card-detect supply voltage
VCCI
1.65
5.5
V
VCC_S
System-side supply voltage
1.65
VCC_CF
V
VCC_CF
CF-side supply voltage
3
5.5
V
VIH
High-level input voltage
Card-detect inputs
(CD1, CD2)
1.65 V to 5.5 V
VIL
Low-level input voltage
Card-detect inputs
(CD1, CD2)
1.65 V to 5.5 V
VIH
High-level input voltage
System port
(SD, SA, SRESET)
VIL
VIH
VIL
Low-level input voltage
System port
(SD, SA, SRESET)
Control inputs
High-level input voltage (DIR, MASTER_EN,
ENL, ENH, BUF_EN)
Low-level input voltage
Control inputs
(DIR, MASTER_EN,
ENL, ENH, BUF_EN)
VIH
High-level input voltage CF port (D, A)
VIL
Low-level input voltage
VO
IOH
IOL
IOH
IOL
CF port (D, A)
VCC_SD × 0.35
1.65 V to 1.95 V
VCC_S × 0.65
1.95 V to 2.7 V
1.7
2.7 V to 3.6 V
2
VCC_S × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
VCC_S × 0.65
1.95 V to 2.7 V
1.7
2.7 V to 3.6 V
2
VCC_S × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
2
4.5 V to 5.5 V
3 V to 3.6 V
0.8
VCC_CF × 0.3
0
0
VCC_S
CF-side output voltage
0
VCC_CF
High-level
output current
Low-level
output current
High-level
output current
Low-level
output current
Card detect
Card detect
System port
System port
CF port
IOL
Low-level
output current
CF port
V
V
VCC_CF × 0.7
4.5 V to 5.5 V
V
V
1.65 V to 1.95 V
3 V to 3.6 V
V
V
1.65 V to 1.95 V
1.65 V to 1.95 V
UNIT
V
System-side output voltage
High-level
output current
12
VCC_SD × 0.65
Card-detect output voltage
IOH
(1)
(2)
(3)
VCCO
V
VCC_SD
1.65 V to 1.95 V
–2
1.95 V to 2.7 V
–4
2.7 V to 3.6 V
–8
4.5 V to 5.5 V
–12
1.65 V to 1.95 V
2
1.95 V to 2.7 V
4
2.7 V to 3.6 V
8
4.5 V to 5.5 V
12
1.65 V to 1.95 V
2
1.95 V to 2.7 V
6
2.7 V to 3.6 V
12
1.65 V to 1.95 V
2
1.95 V to 2.7 V
6
2.7 V to 3.6 V
12
3 V to 3.6 V
12
4.5 V to 5.5 V
16
3 V to 3.6 V
12
4.5 V to 5.5 V
16
V
mA
mA
mA
mA
mA
mA
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
Recommended Operating Conditions(1) (2)
(3)
(continued)
VCCI
Δt/Δv
Input transition rise or fall rate
TA
VCCO
MIN
MAX
1.65 V to 2.7 V
>20
2.7 V to 3.6 V
>20
4.5 V to 5.5 V
>20
Operating free-air temperature
–40
85
UNIT
ns/V
°C
Electrical Characteristics
over recommended operating free-air temperature range (CF card-detect logic) (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 μA
VOH
VI = VIH
VOL
VI = VIL
1.65 V to 5.5 V
MIN
–40°C to 85°C
TYP MAX
VCC_SD – 0.1
VCC_SD – 0.2
1.2
1.2
1.65 V
IOH = –4 mA
2.3 V
2
2
IOH = –6 mA
2.7 V
2.3
2.3
IOH = –8 mA
3V
2.4
2.4
IOH = –12 mA
4.5 V
3.8
3.8
IOL = 100 μA
1.65 V to 5.5 V
0.1
0.2
1.65 V
0.2
0.2
IOL = 4 mA
2.3 V
0.2
0.2
IOL = 6 mA
2.7 V
0.3
0.3
IOL = 8 mA
3V
0.4
0.4
IOL = 12 mA
4.5 V
0.5
0.5
Ioff
VI or VO = 0 to 5.5 V
RINT
CD1 = GND, CD2 = GND
1.65 V to 5.5 V
0V
1.65 V to 5.5 V
CD1 and CD2 = VCC_SD,
IO_SD = 0
CI
CD1 or CD2
CD1 or CD2 = GND,
CD2 or CD1 = VCC_SD,
IO_SD = 0
5.5 V
VI = VCC_SD or GND
5.5 V
±0.5
±1
–55
–60
55
150
300
100
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V
μA
60
μA
300
kΩ
0.5
1
10
10
μA
9
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UNIT
V
IOL = 2 mA
VI = 0 V
ICC_SD
MIN MAX
IOH = –2 mA
VI = VCC_SD
II
TA = 25°C
VCC_SD
pF
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CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
Electrical Characteristics (1)
www.ti.com
(2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_S
SOE, SCE1,
SCE2, SIORD,
SIOWR, SWE,
SREG
VT+
VT–
1.4
0.9
1.8
1.49
1
2
2.2
3 V to 5.5 V
3V
1.67
1.2
1.65 V
0.66
0.19
0.8
2.3 V
0.87
0.39
1.15
0.98
0.49
1.32
3V
1.08
0.59
1.5
1.65 V
0.31
0.1
0.7
0.46
0.25
0.7
0.52
0.3
0.9
VT+
BVD1, BVD2,
READY,
INPACK, WAIT
1.65 V
to 3.6 V
VT–
BVD1, BVD2,
READY,
INPACK, WAIT,
WP
1.65 V
to 3.6 V
ΔVT
BVD1, BVD2,
READY,
INPACK, WAIT
1.65 V
to 3.6 V
VT+
BUF_EN, ENH,
ENL,
MASTER_EN
2.7 V
3 V to 5.5 V
3 V to 5.5 V
3V
0.61
0.4
0.9
3V
1.67
1.3
2.2
4.5 V
2.44
1.9
3.1
3V
1.11
0.6
1.5
4.5 V
1.43
1
2
3V
0.58
0.35
1
4.5 V
1.02
0.6
1.5
1.65 V
1
0.6
1.4
2.3 V
1.37
1.1
1.8
1.54
1.1
2
2.7 V
3 V to 5.5 V
3V
1.72
1.3
2.2
1.65 V
0.34
0.15
1
0.63
0.15
1.2
0.75
0.2
1.32
2.3 V
2.7 V
3 V to 5.5 V
3V
0.88
0.4
1.5
1.65 V
0.67
0.08
1.1
0.76
0.2
1.2
0.8
0.26
1.3
0.86
0.3
1.4
2.3 V
2.7 V
3 V to 5.5 V
3V
VOH_S
VOL_S
(1)
(2)
14
VI = VIH
VI = VIL
MAX
0.6
2.3 V
BUF_EN, ENH,
ENL,
MASTER_EN
MIN
1.32
2.7 V
BUF_EN, ENH,
ENL,
MASTER_EN
TYP MAX
0.95
ΔVT
ΔVT
MIN
–40°C to 85°C
2.3 V
SOE, SCE1,
SCE2, SIORD,
SIOWR, SWE,
SREG
VT–
TA = 25°C
1.65 V
2.7 V
SOE, SCE1,
SCE2, SIORD,
SIOWR, SWE,
SREG
VCC_CF
IOH = –100 μA
1.65 V
to 3.6 V
IOH = –2 mA
1.65 V
3 V to 5.5 V
VCC_S
– 0.1
VCC_S
– 0.2
1.2
1.2
2
2
IOH = –4 mA
2.3 V
IOH = –6 mA
2.7 V
2.3
2.3
IOH = –12 mA
3V
2.4
2.4
IOL = 100 μA
1.65 V
to 3.6 V
IOL = 2 mA
1.65 V
IOL = 4 mA
2.3 V
IOL = 6 mA
IOL = 12 mA
V
V
V
V
V
V
V
V
V
V
0.1
0.2
0.2
0.2
0.2
0.2
2.7 V
0.3
0.3
3V
0.5
0.5
3 V to 5.5 V
UNIT
V
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
Electrical Characteristics (1)
(2)
(continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC_S
VOL_CF
VI = VIH
II
Inputs with
pullup resistor
VI = VCCI
IOH = 16 mA
5.5 V
3.8
3.8
IOL = 100 μA
3 V to
5.5 V
0.1
0.2
3V
0.5
0.5
5.5 V
0.5
0.5
3.6 V to
5.5 V
±0.5
±1
±0.5
±1
1.65 V
to 3.6 V
(3)
1.65 V
to 3.6 V
(3)
VI = 0 V
S port
Ioff
VI or VO = 0 to 5.5 V
CF port
S or CF output
ports
IOZ
(4)
CF outputs
ICC_S
Inputs
(SD15–SD00,
SA10–SA00,
VI = VCC_S or
SCE1, SCE2,
GND
SIORD, SIOWR,
SOE, SREG,
SWE)
Control inputs
(ENL, ENH,
BUF_EN)
(1)
(2)
(3)
(4)
VO = VCCO or
GND,
VI = VCCI or GND
ENL = ENH =
BUF_EN = VCC_S
One of ENL,
ENH, BUF_EN =
GND,
Others = VCC_S
MAX
2.4
IOL = 12 mA
VI = GND to VCCI
MIN
2.4
IOL = 16 mA
Inputs without
pullup resistor
TYP MAX
3V
IOH = 12 mA
VI = VIL
MIN
–40°C to 85°C
VCC_CF
– 0.2
1.65 V
to 3.6 V
3 V to
5.5 V
UNIT
V
55
60
0V
0 to
5.5 V
±0.5
±1
0 to
3.6 V
0V
±0.5
±1
5.5 V
±0.5
±1
0V
±0.5
±1
1.5
3
1.5
3
36
36
MASTER_EN = VIH
MASTER_EN =
don't care
3 V to
5.5 V
TA = 25°C
VCC_CF
– 0.1
IOH = –100 μA
VOH_CF
VCC_CF
V
μA
μA
μA
3.6 V
IO = 0,
ENL = VCC_S,
ENH = VCC_S,
BUF_EN = VCC_S,
DIR(S/CF) = VCC_S
1.65 V 3.6 V to
to 3.6 V
5.5 V
IO = 0,
DIR(S/CF) = VCC_S,
All other inputs =
VCC_S or GND
μA
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
VCCI = VCC_S for DIR(S/CF), ENL, ENH, SD15–SD00, SA10–SA00, MASTER_EN, SRESET, SCE1, SCE2, SIORD, SIOWR, SOE,
SREG, SWE, BUF_EN
VCCI = VCC_CF for D15–D00, BVD1, BVD2, INPACK, READY, WAIT, WP
For I/O ports, the parameter IOZ includes the input leakage current.
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
ICC_CF
TEST CONDITIONS
Input
(D15–D00)
VI = VCC_CF
or GND
IO = 0,
DIR(S/CF) = GND,
BVD1, BVD2, INPACK,
READY, WAIT, WP =
VCC_CF
Inputs
(BVD1, BVD2,
INPACK,
READY, WAIT,
WP)
BVD1 = BVD2 =
INPACK =
READY WAIT =
WP = VCC_CF
IO = 0,
DIR(S/CF) = GND,
D15–D00 = VCC_CF or
GND
One of BVD1,
DVD2, INPACK,
READY, WAIT,
WP = GND, All
others = VCC_CF
IO = 0,
DIR(S/CF) = GND,
D15–D00 = VCC_CF or
GND
VCC_S
1.65 V
to 3.6 V
1.65 V
to 3.6 V
RINT
VCC_CF
3 V to
5.5 V
SAxx, SOE,
SCE1, SCE2,
SIORD, SIOWR,
SREG, SWE
VI = 3.3 V or GND
16
S I/O ports
CF I/O ports
–40°C to 85°C
TYP MAX
150
MIN
MAX
1.5
3
1.5
3
60
60
300
300
UNIT
μA
kΩ
3
3
3.3 V
3.3 V
Axx, BVD1,
BVD2, READY,
INPACK, WAIT,
WP
Cio
MIN
3 V to
5.5 V
Control inputs
CI
TA = 25°C
pF
9
VO = 3.3 V or GND
3.3 V
3.3 V
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7
12
pF
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
Switching Characteristics
over recommended operating free-air temperature range (CD1, CD2) (see Figure 1)
PARAMETER
tpd
FROM
(INPUT)
TO
(OUTPUT)
CD1 or CD2
SCD
TA = 25°C
VCC_SD
–40°C to 85°C
MIN
TYP
MAX
MIN
MAX
1.8 V ± 0.15 V
3.1
7.1
13.5
1.8
15.5
2.5 V ± 0.2 V
2.7
4.6
7.1
1.6
9.1
2.7 V
2.4
4
5.7
1.6
9.1
2
3.4
5.1
1.2
6.8
1.7
2.6
3.6
1
5.5
3.3 V ± 0.3 V
5 V ± 0.5 V
UNIT
ns
Switching Characteristics
over recommended operating free-air temperature range (BVD1, BVD2, INPACK, READY, WAIT, WP) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC_S
CF input
S output
MASTER_EN =
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
MASTER_EN
S output
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
MASTER_EN
S output
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
BUF_EN
S output
MASTER_EN =
VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
BUF_EN
S output
MASTER_EN =
VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
–40°C to
85°C
TA = 25°C
MIN
1.8 V ± 0.15 V
tpd
VCC_CF
TYP MAX
UNIT
MIN MAX
3.3 V ± 0.3 V
3.1
6
10.2
2.4
12.9
5 V ± 0.5 V
2.9
5.6
9.6
2.2
13.9
3.3 V ± 0.3 V
2.7
4.6
6.5
1.9
10
5 V ± 0.5 V
2.5
4.2
5.8
1.7
8.6
3.3 V ± 0.3 V
2.5
4
5.6
1.6
8.8
5 V ± 0.5 V
2.3
3.6
4.9
1.5
7
3.3 V ± 0.3 V
11.1
18.9
30.7
9.2
35.5
5 V ± 0.5 V
11.1
19.3
30.9
8
35.6
3.3 V ± 0.3 V
9.9
12.9
17.4
6.9
22.6
5 V ± 0.5 V
9.9
13.1
17.4
7
22.6
3.3 V ± 0.3 V
9.5
11.2
13.4
6.3
18.3
5 V ± 0.5 V
9.5
11.3
13.5
6.3
18.2
3.3 V ± 0.3 V
6.8
13.7
23.9
6
25.1
5 V ± 0.5 V
6.1
13.4
22
5.4
23.3
3.3 V ± 0.3 V
4.9
8.6
13.3
4
14.5
5 V ± 0.5 V
4.6
8.5
13.6
3.9
14.5
3.3 V ± 0.3 V
5
8.1
12.2
4.2
13.2
5 V ± 0.5 V
4.5
8
12.2
3.6
18.2
3.3 V ± 0.3 V
8.7
17.7
33.2
7.6
35.5
10.7 18..3
29.3
8.7
35.6
3.3 V ± 0.3 V
5 V ± 0.5 V
9.6
12.4
16.6
6.6
22.6
5 V ± 0.5 V
9.6
12.6
16.7
6.6
22.6
3.3 V ± 0.3 V
9.2
10.9
13
6.1
18.3
5 V ± 0.5 V
9.2
10.9
13
6.1
18.2
3.3 V ± 0.3 V
6.9
12.9
22.3
5.9
24.2
5 V ± 0.5 V
5.4
12.4
20.5
4.8
22.8
3.3 V ± 0.3 V
4.4
8
12.7
3.6
14.5
5 V ± 0.5 V
4.2
7.9
12.8
3.6
14.2
3.3 V ± 0.3 V
4.6
7.7
11.7
3.8
12.3
5 V ± 0.5 V
4.1
7.6
11.7
3.3
12.4
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17
CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (data bus I/Os) (see Figure 1)
PARAMETER
FROM
(INPUT)
D
TO
(OUTPUT)
TEST
CONDITIONS
SD
MASTER_EN =
ENL = ENH = VIL
tpd
SD
D
D
ten
MASTER_EN
D
MASTER_EN
18
–40°C to
85°C
TA = 25°C
TYP MAX
UNIT
MIN
MAX
1.8 V ±
0.15 V
3.3 V ± 0.3 V
4.2
7.2
11.8
3
13.7
5 V ± 0.5 V
3.7
6.4
10.7
2.7
13.9
2.5 V ±
0.2 V
3.3 V ± 0.3 V
3.8
5.7
8
2.4
10
5 V ± 0.5 V
3.3
4.9
6.8
2.1
12.4
3.3 V ±
0.3 V
3.3 V ± 0.3 V
3.5
5.1
6.9
2.2
8.8
3
4.3
5.7
1.8
7
1.8 V ±
0.15 V
3.3 V ± 0.3 V
3.4
5.7
9.8
2.6
11.1
5 V ± 0.5 V
3.1
5.4
9.6
2.4
9.6
2.5 V ±
0.2 V
3.3 V ± 0.3 V
2.8
4.3
6.2
1.9
8.2
5 V ± 0.5 V
2.6
3.8
5.4
1.7
7
3.3 V ±
0.3 V
3.3 V ± 0.3 V
2.5
3.7
5.2
1.5
7.2
5 V ± 0.5 V
2.2
3.3
4.5
1.4
6
1.8 V ±
0.15 V
3.3 V ± 0.3 V
13.7
18.2
24.4
9.4
27.9
5.5 V ± 0.5 V
13.7
17.9
29.9
8
31
2.5 V ±
0.2 V
3.3 V ± 0.3 V
12.3
15.1
18.8
7.9
23
5.5 V ± 0.5 V
12.3
14.8
17.6
8
21.8
3.3 V ±
0.3 V
3.3 V ± 0.3 V
11.6
14
17.1
7.3
21.4
5.5 V ± 0.5 V
11.6
13.7
15.9
7.4
20.3
1.8 V ±
0.15 V
3.3 V ± 0.3 V
11.6
19.6
31.8
9.4
36.3
5.5 V ± 0.5 V
11.7
20.1
32
9.5
36.2
2.5 V ±
0.2 V
3.3 V ± 0.3 V
10.3
13.4
18
7.2
22.6
5.5 V ± 0.5 V
10.3
13.6
18.1
7.1
22.6
3.3 V ±
0.3 V
3.3 V ± 0.3 V
9.8
11.6
14
6.4
18.3
5.5 V ± 0.5 V
9.8
11.7
14
6.4
18.2
1.8 V ±
0.15 V
3.3 V ± 0.3 V
8.6
12.8
18.1
7.3
20.2
5.5 V ± 0.5 V
7.6
11.5
16.4
6.3
17.8
2.5 V ±
0.2 V
3.3 V ± 0.3 V
7.8
10.8
14.7
6.4
16.4
5.5 V ± 0.5 V
6.7
9.4
12.6
5.4
13.8
3.3 V ±
0.3 V
3.3 V ± 0.3 V
7.2
9.9
13.4
5.9
15
5.5 V ± 0.5 V
6.1
8.6
11.4
4.8
12.5
1.8 V ±
0.15 V
3.3 V ± 0.3 V
6.9
12.9
21.7
6
24.2
5.5 V ± 0.5 V
6.1
12.6
20.8
5.3
22.8
2.5 V ±
0.2 V
3.3 V ± 0.3 V
4.9
7.9
11.8
4.1
14.5
5.5 V ± 0.5 V
4.7
7.8
11.7
3.9
14.2
3.3 V ±
0.3 V
3.3 V ± 0.3 V
5
7.1
9.8
4
12
5.5 V ± 0.5 V
4.7
7
9.8
3.8
18.2
ENL = ENH = VIL
SD
VCC_CF
MIN
ENL = ENH = VIL
SD
tdis
VCC_S
5 V ± 0.5 V
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CF4320H
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
Switching Characteristics (continued)
over recommended operating free-air temperature range (data bus I/Os) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
D
ten
ENL or ENH
D
ENL or ENH
–40°C to
85°C
TA = 25°C
TYP MAX
MIN
MAX
1.8 V ±
0.15 V
3.3 V ± 0.3 V
9.4
17.6
23.4
8.3
27.2
5.5 V ± 0.5 V
13.5
17.4
22.6
7.7
27.8
2.5 V ±
0.2 V
3.3 V ± 0.3 V
12.3
15
18.5
7.9
22.8
5.5 V ± 0.5 V
12.3
14.7
17.4
8
21.6
3.3 V ±
0.3 V
3.3 V ± 0.3 V
11.7
14.1
17
7.3
21.4
5.5 V ± 0.5 V
11.6
13.7
16
7.4
20.3
1.8 V ±
0.15 V
3.3 V ± 0.3 V
9.5
18.7
30.5
9.1
35.5
5.5 V ± 0.5 V
9.6
19.1
30.5
9.1
35.6
2.5 V ±
0.2 V
3.3 V ± 0.3 V
10
13
17.4
6.8
22.6
5.5 V ± 0.5 V
10
13.2
17.4
6.8
22.6
3.3 V ±
0.3 V
3.3 V ± 0.3 V
9.6
11.3
13.6
6.2
18.3
5.5 V ± 0.5 V
9.6
11.4
13.6
6.3
18.2
1.8 V ±
0.15 V
3.3 V ± 0.3 V
8.5
12.1
16.8
7.2
20.2
5.5 V ± 0.5 V
7.7
10.8
15
6.3
16.6
2.5 V ±
0.2 V
3.3 V ± 0.3 V
7.6
10.4
13.8
6.2
16.4
5.5 V ± 0.5 V
6.9
9.1
11.9
5.4
13.1
3.3 V ±
0.3 V
3.3 V ± 0.3 V
7.3
9.7
12.9
5.9
15
5.5 V ± 0.5 V
6.5
8.4
11
5.2
12
1.8 V ±
0.15 V
3.3 V ± 0.3 V
6.5
12
20
5.7
24.2
5.5 V ± 0.5 V
5.7
11.8
19
5
22.8
2.5 V ±
0.2 V
3.3 V ± 0.3 V
4.6
7.4
11.1
3.8
14.5
5.5 V ± 0.5 V
4.4
7.3
11.1
3.7
14.2
3.3 V ±
0.3 V
3.3 V ± 0.3 V
4.9
6.8
9.3
4
12
5.5 V ± 0.5 V
4.3
6.7
9.2
3.5
18.2
MASTER_EN = VIL
SD
VCC_CF
MIN
MASTER_EN = VIL
SD
tdis
VCC_S
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UNIT
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CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
www.ti.com
Switching Characteristics
over recommended operating free-air temperature range (SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE)
(see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CF output
(control)
tpd
TEST
CONDITIONS
MASTER_EN
= BUF_EN =
VIL
VCC_S
1.8 V ±
0.15 V
3.3 V ± 0.3 V
CF output
(A pins)
CF output
(control)
BUF_EN = VIL
6.1
9.8
2.5
10.4
5.8
9.7
2.4
10.2
2.5 V ±
0.2 V
3.3 V ± 0.3 V
2.6
4.5
6.7
1.8
8.4
5 V ± 0.5 V
2.4
4.1
6
1.7
6.8
3.3 V ±
0.3 V
3.3 V ± 0.3 V
2.2
3.9
5.8
1.4
7
2
3.5
5
1.3
5.8
1.8 V ±
0.15 V
3.3 V ± 0.3 V
3.4
5.7
8.7
2.8
10.3
5 V ± 0.5 V
3.3
5.4
8.2
2.8
9.7
2.5 V ±
0.2 V
3.3 V ± 0.3 V
2.9
4.3
6.2
1.9
8.4
6.8
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
MASTER_EN
CF output
(control)
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
BUF_EN
CF output
(A pins)
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
BUF_EN
CF output
(A pins)
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
BUF_EN
CF output
(A pins)
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
20
UNIT
MIN MAX
3
1.8 V ± 0.15 V
MASTER_EN
TYP MAX
3.4
3.3 V ± 0.3 V
ten
–40°C to
85°C
TA = 25°C
MIN
S input
MASTER_EN
= BUF_EN =
VIL
VCC_CF
5 V ± 0.5 V
5 V ± 0.5 V
5 V ± 0.5 V
2.7
3.9
5.4
1.9
3.3 V ± 0.3 V
2.6
3.7
5.2
1.7
7
5 V ± 0.5 V
2.3
3.3
4.4
1.5
5.8
3.3 V ± 0.3 V
10.8
17.9
24.8
7.9
29.7
5 V ± 0.5 V
10.8
17.5
26.2
8.1
30.2
3.3 V ± 0.3 V
9.4
14.2
19.4
6.4
23.3
5 V ± 0.5 V
9.4
14.1
19.3
6.6
23.1
3.3 V ± 0.3 V
8.7
13.1
17.8
5.8
21.4
5 V ± 0.5 V
8.7
13
17.5
6
21.2
3.3 V ± 0.3 V
7.3
13.8
22.5
6.2
25.8
5 V ± 0.5 V
6.8
12.1
19.7
5.9
26.3
3.3 V ± 0.3 V
6.1
11.8
19.2
4.9
20.2
5 V ± 0.5 V
5.9
10
16.3
4.6
19.8
3.3 V ± 0.3 V
5.6
11
18.3
4.6
19.1
5 V ± 0.5 V
5.4
9.2
15.5
3.9
18
3.3 V ± 0.3 V
12.9
17.5
23.7
7.7
29.7
5 V ± 0.5 V
13.3
17.8
24.4
9.4
30.2
3.3 V ± 0.3 V
11.7
14.4
17.9
7.5
23.3
5 V ± 0.5 V
11.8
14.3
17.1
7.7
23.1
11
13.3
16.2
6.9
21.4
3.3 V ± 0.3 V
5 V ± 0.5 V
11.1
13.2
15.3
6.5
21.2
3.3 V ± 0.3 V
8.9
13.6
19.7
7.5
25.8
5 V ± 0.5 V
7.6
11.8
17.1
6.6
26.3
8
11.6
16
6.6
20.1
5 V ± 0.5 V
6.7
9.7
13.2
5
19.8
3.3 V ± 0.3 V
7.7
10.6
14.7
6
18.2
5 V ± 0.5 V
6.1
8.9
11.9
4.9
18
3.3 V ± 0.3 V
12.3
16.4
21.9
7.7
27.2
5 V ± 0.5 V
12.6
16.7
22.6
8.6
29.1
3.3 V ± 0.3 V
11.2
13.8
17
7.1
21.7
5 V ± 0.5 V
11.4
13.7
16.3
7.3
21.5
3.3 V ± 0.3 V
10.7
12.9
15.6
6.7
19.5
5 V ± 0.5 V
10.8
12.8
14.8
6.5
19.6
3.3 V ± 0.3 V
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ns
ns
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: CF4320H
CF4320H
www.ti.com
SCES655B – APRIL 2006 – REVISED AUGUST 2013
Switching Characteristics (continued)
over recommended operating free-air temperature range (SA10–SA00, SCE1, SCE2, SIORD, SIOWR, SOE, SREG, SWE)
(see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
VCC_S
BUF_EN
CF output
(A pins)
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
BUF_EN
CF output
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
BUF_EN
CF output
MASTER_EN
= VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
ten
MASTER_EN
DIR_OUT
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tdis
MASTER_EN
DIR_OUT
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tpd
SIORD or
SOE
DIR_OUT
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
1.8 V ± 0.15 V
tpd
BUF_EN
DIR_OUT
BUF_EN = VIL
2.5 V ± 0.2 V
3.3 V ± 0.3 V
–40°C to
85°C
TA = 25°C
MIN
1.8 V ± 0.15 V
tdis
VCC_CF
TYP MAX
3.3 V ± 0.3 V
8.4
13.9
21.2
7.2
23.2
5 V ± 0.5 V
7.6
12.3
18.5
6.6
23.7
3.3 V ± 0.3 V
7.7
12.3
18.2
6.4
19.8
5 V ± 0.5 V
6.7
10.6
15.3
5
18.4
3.3 V ± 0.3 V
7.2
11.5
16.4
5.9
18
5 V ± 0.5 V
6.4
10
14.3
4.9
17
3.3 V ± 0.3 V
12.5
16.6
22.3
8.7
27.2
5 V ± 0.5 V
12.8
17
23.1
8.8
29.1
3.3 V ± 0.3 V
11.4
14.1
17.5
7.3
21.7
5 V ± 0.5 V
11.6
14
16.9
7.4
21.5
3.3 V ± 0.3 V
10.9
13.2
16
6.8
20
5 V ± 0.5 V
11
13.1
15.3
6.5
19.6
3.3 V ± 0.3 V
8.6
13.9
21.5
7.4
23.2
5 V ± 0.5 V
7.7
12.1
19.8
6.6
23.7
3.3 V ± 0.3 V
7.9
12.3
18.5
6.5
19.8
5 V ± 0.5 V
6.6
10.4
17.1
5
18.4
3.3 V ± 0.3 V
7.4
11.7
17.5
6.1
18.9
5 V ± 0.5 V
6.1
9.7
16.2
4.9
17
3.3 V ± 0.3 V
6.1
14.2
29.6
4.9
32.8
5 V ± 0.5 V
6
14.2
30
4.9
33.2
3.3 V ± 0.3 V
4.8
8.8
15.4
3.4
19.3
5 V ± 0.5 V
4.8
8.8
15.5
3.4
19.3
3.3 V ± 0.3 V
4.2
6.9
11.1
2.7
14.4
5 V ± 0.5 V
4.2
6.9
11.1
2.6
14.4
3.3 V ± 0.3 V
5.4
10
16.6
4.2
32.6
5 V ± 0.5 V
5.4
9.9
16.1
4.8
32.6
3.3 V ± 0.3 V
3.9
6.5
10.5
1.5
19.3
5 V ± 0.5 V
3.9
6.6
10.4
1.7
19.3
3.3 V ± 0.3 V
4.4
6.7
10.3
1.4
14.4
5 V ± 0.5 V
4.3
6.7
10.1
1.5
14.4
3.3 V ± 0.3 V
5
9.3
15.7
4
17.9
5 V ± 0.5 V
5
9.3
15.7
4
17.9
3.3 V ± 0.3 V
3.9
6
8.5
2.8
11
5 V ± 0.5 V
3.9
6
8.5
2.8
11
3.3 V ± 0.3 V
3.3
4.7
6.2
2.2
8.2
5 V ± 0.5 V
3.3
4.7
6.2
2.2
8.2
3.3 V ± 0.3 V
8.9
19.5
35.9
7.1
39.2
5 V ± 0.5 V
8.9
19.5
35.8
7
39.3
3.3 V ± 0.3 V
6.8
11.9
19.1
5
22.8
5 V ± 0.5 V
6.8
11.9
19.2
4.9
22.8
3.3 V ± 0.3 V
5.8
9
13.3
4
15.8
5 V ± 0.5 V
5.8
9
13.3
3.9
15.9
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UNIT
MIN MAX
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21
CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
www.ti.com
Operating Characteristics
VCCS and VCC_CF = 3.3 V, TA = 25°C
PARAMETER
TEST CONDITIONS
System-port input,
CF-port output
CpdS
Power dissipation capacitance
per transceiver
CF-port input,
system-port output
System-port input,
CF-port output
CpdCF
Power dissipation capacitance
per transceiver
CF-port input,
system-port output
22
Outputs
enabled
Outputs
disabled
Outputs
enabled
TYP
1.93
0.04
CL = 0,
f = 10 MHz
pF
14.35
Outputs
disabled
0.04
Outputs
enabled
22.85
Outputs
disabled
Outputs
enabled
Outputs
disabled
Submit Documentation Feedback
UNIT
0.04
CL = 0,
f = 10 MHz
pF
4.66
3.65
Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: CF4320H
CF4320H
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SCES655B – APRIL 2006 – REVISED AUGUST 2013
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL
(see Note A)
RL
S1
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V ± 0.15 V
2.5 ± 0.2 V
2.7 V
3.3 V ± 0.3 V
5.5 V ± 0.5 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
6V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
0.3 V
0.5 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
VLOAD/2
VM
VOH
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + V∆
VOL
tPHZ
tPZH
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: CF4320H
23
CF4320H
SCES655B – APRIL 2006 – REVISED AUGUST 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (August 2006) to Revision B
•
24
Page
Removed Ordering Information table. ................................................................................................................................... 2
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Copyright © 2006–2013, Texas Instruments Incorporated
Product Folder Links: CF4320H
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
CF4320HZKFR
LIFEBUY
Package Type Package Pins Package
Drawing
Qty
LFBGA
ZKF
114
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
CF4320
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CF4320HZKFR
Package Package Pins
Type Drawing
LFBGA
ZKF
114
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.8
B0
(mm)
K0
(mm)
P1
(mm)
16.3
1.8
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CF4320HZKFR
LFBGA
ZKF
114
1000
336.6
336.6
41.3
Pack Materials-Page 2
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