Texas Instruments | SN54AHCT540, SN74AHCT540 (Rev. M) | Datasheet | Texas Instruments SN54AHCT540, SN74AHCT540 (Rev. M) Datasheet

Texas Instruments SN54AHCT540, SN74AHCT540 (Rev. M) Datasheet
SN54AHCT540
SN74AHCT540
www.ti.com
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS
Check for Samples: SN54AHCT540, SN74AHCT540
FEATURES
1
•
Inputs Are TTL-Voltage Compatible
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54AHCT540 . . . J OR W PACKAGE
SN74AHCT540 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
DESCRIPTION
The ’AHCT540 octal buffers/drivers are ideal for
driving bus lines or buffer memory address registers.
These devices feature inputs and outputs on opposite
sides of the package to facilitate printed circuit board
layout.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
SN54AHCT540 . . . FK PACKAGE
(TOP VIEW)
A2
A1
OE1
VCC
The 3-state control gate is a two-input AND gate with
active-low inputs so that if either output-enable (OE1
or OE2) input is high, all corresponding outputs are in
the high-impedance state. The outputs provide
inverted data when they are not in the highimpedance state.
A3
A4
A5
A6
A7
4
3 2 1 20 19
18
5
17
6
16
7
15
8
14
9 10 11 12 13
Y1
Y2
Y3
Y4
Y5
A8
GND
Y8
Y7
Y6
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
OE2
•
•
FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUTS
OUTPUT
A
Y
OE1
OE2
L
L
L
L
L
H
L
H
X
X
Z
X
H
X
Z
H
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1995–2013, Texas Instruments Incorporated
SN54AHCT540
SN74AHCT540
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE1
OE2
A1
19
2
18
Y1
To Seven Other Channels
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
VALUE
UNIT
Supply voltage range, VCC
–0.5 to 7
V
Input voltage range, VI (2)
–0.5 to 7
V
–0.5 to VCC + 0.5
V
Input clamp current, IIK (VI < 0)
–20
mA
Output clamp current, IOK (VO < 0 or VO > VCC)
±20
mA
Continuous output current, IO (VO = 0 to VCC)
±25
mA
±75
mA
Output voltage range, VO (2)
Continuous current through VCC or GND
Package thermal impedance, θJA
(3)
DB package
70
DGV package
92
DW package
58
N package
69
NS package
60
PW package
83
Storage temperature range, Tstg
(1)
(2)
(3)
2
–65 to 150
°C/W
°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHCT540 SN74AHCT540
SN54AHCT540
SN74AHCT540
www.ti.com
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
RECOMMENDED OPERATING CONDITIONS (1)
SN54AHCT540
SN74AHCT540
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level Input voltage
0.8
V
VI
Input voltage
0
5.5
0
5.5
V
VO
Output voltage
0
VCC
0
VCC
V
IOH
High-level output current
–8
–8
IOL
Low-level output current
8
8
mA
Δt/Δv
Input Transition rise or fall rate
20
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
2
V
2
V
0.8
–55
125
–40
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
IOH = –50 µA
4.5 V
IOH = –8 mA
IOL = 50 µA
TA = 25°C
VCC
MIN
TYP
4.4
4.5
3.94
4.5 V
IOH = 8 mA
MAX
TA = –40°C TO
85°C
SN54AHCT540
SN74AHCT540
MIN
MAX
MIN
MAX
TA = –40°C TO
125°C
Recommended
UNIT
SN74AHCT540
MIN
4.4
4.4
4.4
3.8
3.8
3.8
MAX
V
0.1
0.1
0.1
0.1
0.36
0.44
0.44
0.44
V
II
VI = 5.5 V or GND
0 V to 5.5
V
±0.1
±1 (1)
±1
±1
µA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
±2.5
±2.5
µA
ICC
VI = VCC or
GND,
5.5 V
4
40
20
40
µA
5.5 V
1.35
1.5
1.5
1.5
mA
ΔICC (2)
(1)
(2)
TEST CONDITIONS
TA = –55°C TO
125°C
IO = 0
One input at 3.4 V,
Other inputs at VCC or
GND
Ci
VI = VCC or GND
5V
2
CO
VO = VCC or GND
5V
4
10
10
pF
pF
On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC.
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHCT540 SN74AHCT540
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SN54AHCT540
SN74AHCT540
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
tPLH
tPZL
tPHZ
tPLZ
Y
CL = 15 pF
OE
Y
CL = 15 pF
OE
Y
CL = 15 pF
A
Y
CL = 50 pF
OE
Y
CL = 50 pF
OE
Y
CL = 50 pF
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
(1)
(2)
LOAD
CAPACITANCE
A
tPHL
tPZH
TO
(OUTPUT)
CL = 50 pF
TA = 25°C
TA = –55°C TO
125°C
TA = –40°C TO
85°C
SN54AHCT540
SN54AHCT540
MIN
MAX
MIN
MAX
TA = –40°C TO
125°C
Recommended
UNIT
SN54AHCT540
TYP
MAX
4.0 (1)
6.0 (1)
1 (1)
7.5 (1)
1
7.5
1
7.5
4.0 (1)
6.0 (1)
1 (1)
7.5 (1)
1
7.5
1
7.5
5.5 (1)
8.0 (1)
1 (1)
9 (1)
1
9.0
1
9.0
5.5 (1)
8.0 (1)
1 (1)
9 (1)
1
9.0
1
9.0
5.0 (1)
8.0 (1)
1 (1)
9 (1)
1
9
1
9
5.0 (1)
8.0 (1)
1 (1)
9 (1)
1
9
1
9
6.0
8.5
1
10
1
10
1
10
6.0
8.5
1
10
1
10
1
10
7.5
11.0
1
12
1
12
1
12
7.5
11.0
1
12
1
12
1
12
8.0
11.0
1
12
1
12
1
12
8.0
11.0
1
12
1
12
1
12
1 (2)
MIN
MAX
ns
ns
ns
ns
ns
ns
1
On products compliant to MIL-PRF-38535, this parameter is not production tested.
On products compliant to MIL-PRF-38535, this parameter does not apply
OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
4
Power dissipation capacitance
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TEST CONDITIONS
No load,
f = 1 MHz
TYP
12
UNIT
pF
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHCT540 SN74AHCT540
SN54AHCT540
SN74AHCT540
www.ti.com
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
In-Phase
Output
50% VCC
tPHL
Out-of-Phase
Output
50% VCC
VOL
Output
Waveform 1
S1 at VCC
(see Note B)
1.5 V
VOH
50% VCC
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZL
tPLZ
≈VCC
50% VCC
tPZH
tPLH
50% VCC
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
A.
CL includes probe and jig capacitance.
B.
Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output
control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output
control.
C.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf
≤ 3 ns.
D.
The outputs are measured one at a time with one input transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHCT540 SN74AHCT540
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5
SN54AHCT540
SN74AHCT540
SCLS268M – OCTOBER 1995 – REVISED JUNE 2013
www.ti.com
REVISION HISTORY
Changes from Revision L (July 2003) to Revision M
Page
•
Changed document format from Quicksilver to DocZone. .................................................................................................... 1
•
Extended operating temperature range to 125°C ................................................................................................................. 3
6
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Copyright © 1995–2013, Texas Instruments Incorporated
Product Folder Links: SN54AHCT540 SN74AHCT540
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9685101QRA
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685101QR
A
SNJ54AHCT540J
SN74AHCT540DBR
ACTIVE
SSOP
DB
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB540
SN74AHCT540DGVR
ACTIVE
TVSOP
DGV
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB540
SN74AHCT540DW
ACTIVE
SOIC
DW
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT540
SN74AHCT540DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT540
SN74AHCT540DWRE4
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT540
SN74AHCT540N
ACTIVE
PDIP
N
20
20
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
SN74AHCT540N
SN74AHCT540NSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHCT540
SN74AHCT540PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB540
SN74AHCT540PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
HB540
SNJ54AHCT540J
ACTIVE
CDIP
J
20
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9685101QR
A
SNJ54AHCT540J
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54AHCT540, SN74AHCT540 :
• Catalog: SN74AHCT540
• Military: SN54AHCT540
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
7.5
2.5
12.0
16.0
Q1
SN74AHCT540DBR
SSOP
DB
20
2000
330.0
16.4
SN74AHCT540DGVR
TVSOP
DGV
20
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
SN74AHCT540DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74AHCT540NSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74AHCT540PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
8.2
B0
(mm)
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHCT540DBR
SSOP
DB
20
2000
367.0
367.0
38.0
SN74AHCT540DGVR
TVSOP
DGV
20
2000
367.0
367.0
35.0
SN74AHCT540DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74AHCT540NSR
SO
NS
20
2000
367.0
367.0
45.0
SN74AHCT540PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DB0020A
SSOP - 2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
C
8.2
TYP
7.4
A
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
18X 0.65
20
1
2X
7.5
6.9
NOTE 3
5.85
10
11
20X
B
5.6
5.0
NOTE 4
SEE DETAIL A
(0.15) TYP
0.38
0.22
0.1
C A B
2 MAX
0.25
GAGE PLANE
0 -8
0.95
0.55
0.05 MIN
DETAIL A
A 15
TYPICAL
4214851/B 08/2019
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.
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EXAMPLE BOARD LAYOUT
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.85)
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
11
10
(7)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4214851/B 08/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DB0020A
SSOP - 2 mm max height
SMALL OUTLINE PACKAGE
20X (1.85)
SYMM
(R0.05) TYP
1
20
20X (0.45)
SYMM
18X (0.65)
10
11
(7)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4214851/B 08/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
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