Texas Instruments | SN74AVCB164245-EP 16-Bit Dual-Supply Bus Transceiver (Rev. A) | Datasheet | Texas Instruments SN74AVCB164245-EP 16-Bit Dual-Supply Bus Transceiver (Rev. A) Datasheet

Texas Instruments SN74AVCB164245-EP 16-Bit Dual-Supply Bus Transceiver (Rev. A) Datasheet
SN74AVCB164245-EP
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SCES845A – JANUARY 2013 – REVISED FEBRUARY 2013
16-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
Check for Samples: SN74AVCB164245-EP
FEATURES
1
•
2
•
•
•
•
•
•
•
Member of the Texas Instruments Widebus™
Family
DOC™ Circuitry Dynamically Changes Output
Impedance, Resulting in Noise Reduction
Without Speed Degradation
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA at
2.5-V VCC
Control Inputs VIH and VIL Levels Are
Referenced to VCCB Voltage
If Either VCC Input Is at GND, Both Ports Are in
the High-Impedance State
Overvoltage-Tolerant Inputs and Outputs
Allow Mixed-Voltage-Mode Data
Communications
Ioff Supports Partial-Power-Down Mode
Operation
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over Full 1.4-V to 3.6-V
Power-Supply Range
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 750-V Charged-Device Model (C101)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
(1)
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Military (-55°C to 125°C)
Temperature Ranges (1)
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
Custom temperature ranges available
DESCRIPTION
This 16-bit (dual-octal) noninverting bus transceiver uses two separate configurable power-supply rails. The
A port is designed to track VCCA. VCCA accepts any supply voltage from 1.4 V to 3.6 V. The B port is designed to
track VCCB. VCCB accepts any supply voltage from 1.4 V to 3.6 V. This allows for universal low-voltage
bidirectional translation between any of the 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVCB164245 is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the directioncontrol (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively
isolated.
The SN74AVCB164245 is designed so that the control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCB.
To ensure the high-impedance state during power up or power down, OE should be tied to VCCB through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. If either VCC input is at GND,
both ports are in the high-impedance state.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
SN74AVCB164245-EP
SCES845A – JANUARY 2013 – REVISED FEBRUARY 2013
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Table 1. ORDERING INFORMATION (1)
TA
–55°C to 125°C
(1)
PACKAGE
TSSOP-DGG
ORDERABLE PART NUMBER
Reel of 2000
CAVCB164245MDGGREP
Tube of 40
CAVCB164245MDGGEP
TOP-SIDE MARKING
AVCB164245M
VID NUMBER
V62/13602-01XE
V62/13602-01XE-T
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
TERMINAL ASSIGNMENTS
DGG PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCCB
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCCB
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCCA
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCCA
2A5
2A6
GND
2A7
2A8
2OE
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
2
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
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Figure 1. LOGIC DIAGRAM (POSITIVE LOGIC)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
Pin numbers shown are for the DGG and DGV packages.
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
VI
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5 VCCA + 0.5
B port
–0.5 VCCB + 0.5
Supply voltage range
Input voltage range
(2)
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or power-off
state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
150
°C
(3)
Continuous current through VCCA, VCCB, or GND
TJ
Maximum junction temperature
Tstg
Storage temperature range
(1)
(2)
(3)
–65
V
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
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THERMAL INFORMATION
SN74AVCB164245
THERMAL METRIC (1)
DGG
UNITS
48 PINS
Junction-to-ambient thermal resistance (2)
θJA
(3)
59.9
θJCtop
Junction-to-case (top) thermal resistance
θJB
Junction-to-board thermal resistance (4)
27.1
ψJT
Junction-to-top characterization parameter (5)
0.5
ψJB
Junction-to-board characterization parameter (6)
26.8
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
(1)
(2)
(3)
(4)
(5)
(6)
(7)
4
13.9
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Spacer
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RECOMMENDED OPERATING CONDITIONS (1) (2) (3)
TA = −55°C to 125°C, over recommended input voltage range (unless otherwise noted)
VCCI
VCCO
MIN
MAX
UNIT
VCCA
Supply voltage
1.4
3.6
V
VCCB
Supply voltage
1.4
3.6
V
VIH
High-level input voltage
VIL
Low-level input voltage
Data inputs
Data inputs
1.4 V to 1.95 V
VCCI × 0.65
1.95 V to 2.7 V
1.7
2.7 V to 3.6 V
2
1.4 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Control inputs
(referenced to VCCB)
Control inputs
(referenced to VCCB)
Output voltage
IOH
1.95 V to 2.7 V
1.7
2.7 V to 3.6 V
2
V
1.4 V to 1.95 V
VCCB × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
0
3.6
0
VCCO
3-state
0
3.6
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
(3)
VCCB × 0.65
Active state
High-level output current
V
0.8
1.4 V to 1.95 V
Input voltage
VO
V
1.4 V to 1.6 V
–2
1.65 V to 1.95 V
–4
2.3 V to 2.7 V
–8
3 V to 3.6 V
–12
1.4 V to 1.6 V
2
1.65 V to 1.95 V
4
2.3 V to 2.7 V
8
3 V to 3.6 V
12
5
–55
125
V
V
V
mA
mA
ns/V
°C
VCCI is the VCC associated with the data input port.
VCCO is the VCC associated with the data output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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ELECTRICAL CHARACTERISTICS (1) (2)
TA = −55°C to 125°C, over recommended input voltage range (unless otherwise noted)
PARAMETER
VOH
VOL
II
Control inputs
A port
Ioff
B port
TEST CONDITIONS
(4)
B port
1.4 V to 3.6 V
TYP (3)
MAX
UNIT
IOH = –2 mA
VI = VIH
1.4 V
1.4 V
1.05
IOH = –4 mA
VI = VIH
1.65 V
1.65 V
1.2
IOH = –8 mA
VI = VIH
2.3 V
2.3 V
1.7
IOH = –12 mA
VI = VIH
3V
3V
2.2
IOH = 100 μA
VI = VIL
1.4 V to 3.6 V
1.4 V to 3.6 V
0.2
IOH = 2 mA
VI = VIL
1.4 V
1.4 V
0.35
IOH = 4 mA
VI = VIL
1.65 V
1.65 V
0.45
IOH = 8 mA
VI = VIL
2.3 V
2.3 V
0.6
IOH = 12 mA
VI = VIL
3V
3V
0.75
1.4 V to 3.6 V
3.6 V
±2.5
0V
0 to 3.6 V
±10
0 to 3.6 V
0V
±10
3.6 V
3.6 V
±12.5
0V
3.6 V
±12.5
3.6 V
0V
±12.5
VI = VCCB or GND
VI or VO = 0 to 3.6 V
OE = VIH
VO = VCCO or GND,
VI = VCCI or GND
VI = VCCI or GND,
ICCB
1.4 V to 3.6 V
MIN
VI = VIH
A port
ICCA
VCCB
IOH = –100 μA
A or B ports
IOZ
VCCA
VI = VCCI or GND,
OE = don't care
IO = 0
IO = 0
VCCO – 0.2
V
1.6 V
1.6 V
35
1.95 V
1.95 V
35
2.7 V
2.7 V
45
0V
3.6 V
-50
3.6 V
0V
50
3.6 V
3.6 V
50
1.6 V
1.6 V
35
1.95 V
1.95 V
35
2.7 V
2.7 V
45
0V
3.6 V
50
3.6 V
0V
-50
3.6 V
3.6 V
V
μA
μA
μA
μA
μA
50
Ci
Control inputs
VI = 3.3 V or GND
3.3 V
3.3 V
4
pF
Cio
A or B ports
VO = 3.3 V or GND
3.3 V
3.3 V
5
pF
(1)
(2)
(3)
(4)
6
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
All typical values are at TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
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1000000
Estimated Life (Hours)
100000
WB Voiding Fail Mode
10000
1000
100
80
90
100
110
120
130
140
150
160
Junction Temperature, TJ (°C)
(1)
See datasheet for absolute maximum and minimum recommended operating conditions.
Figure 2. SN74AVCB164245-EP Operating Life Derating Chart
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Switching Characteristics
TA = −40°C to 85°C, VCCA = 1.5 V ± 0.1 V (see )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
tpd
ten
OE
tdis
OE
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.7
6.7
1.9
6.3
1.8
5.5
1.7
5.8
A
1.8
6.8
2.2
7.4
2.1
7.6
2.1
7.3
A
2.5
8.4
2.4
7.4
2.1
5.2
1.9
4.2
B
2.1
9
2.9
9.8
3.2
10
3
9.8
A
2.2
6.9
2.3
6.1
1.3
3.6
1.3
3
B
2.1
7.1
2.3
6.4
1.7
5.1
1.6
4.8
ns
ns
ns
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 1.5 V ± 0.1 V (see Figure 4)
PARAMETER
tpd
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
12.7
12.3
11.5
11.8
B
A
12.8
13.4
13.6
13.3
A
14.8
13.9
12.4
11.9
B
15
15.8
16
15.8
A
12.9
12.1
9.6
9
B
13.1
12.4
11.1
10.8
ten
OE
tdis
OE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
ns
ns
ns
Switching Characteristics
TA = −40°C to 85°C, VCCA = 1.8 V ± 0.15 V (see )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
tpd
ten
OE
tdis
OE
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.7
6.7
1.8
6
1.7
4.7
1.6
4.3
A
1.4
5.5
1.8
6
1.8
5.8
1.8
5.5
A
2.6
8.5
2.5
7.5
2.2
5.3
1.9
4.2
B
1.8
7.6
2.6
7.7
2.6
7.6
2.6
7.4
A
2.3
7
2.3
6.1
1.3
3.6
1.3
3
B
1.8
7
2.5
6.3
1.8
4.7
1.7
4.4
ns
ns
ns
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 1.8 V ± 0.15 V (see Figure 4)
PARAMETER
tpd
8
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
12.7
12
10.7
10.3
B
A
11.5
12
11.8
11.5
A
14.5
13.5
12.1
11.9
B
13.6
13.7
13.6
13.4
A
13
12.1
9.6
9
B
13
12.3
10.7
10.4
ten
OE
tdis
OE
MIN
MAX
MIN
MAX
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MIN
MAX
MIN
UNIT
MAX
ns
ns
ns
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Switching Characteristics
TA = −40°C to 85°C, VCCA = 2.5 V ± 0.2 V (see )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
tpd
ten
OE
tdis
OE
VCCB = 1.5 V
± 0.1 V
MIN
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
MAX
MIN
MAX
MIN
MAX
MIN
MAX
1.6
6
1.8
5.6
1.5
4
1.4
3.4
1.3
4.6
1.7
4.4
1.5
4
1.4
3.7
A
3.1
8.5
2.5
7.5
2.2
5.3
1.9
4.2
B
1.7
5.7
2.2
5.5
2.2
5.3
2.2
5.1
A
2.4
7
3
6.1
1.4
3.6
1.2
3
B
1.2
5.8
1.9
5
1.4
3.6
1.3
3.3
ns
ns
ns
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 2.5 V ± 0.2 V (see Figure 4)
PARAMETER
tpd
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
12
11.6
10
9.4
B
A
10.6
10.4
10
9.7
A
14.5
13.5
11.3
10.2
B
11.7
11.5
11.3
11.1
A
13
12.1
9.6
9
B
11.8
11
9.6
9.3
ten
OE
tdis
OE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
UNIT
MAX
ns
ns
ns
Switching Characteristics
TA = −40°C to 85°C, VCCA = 3.3 V ± 0.3 V (see )
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
tpd
ten
OE
tdis
OE
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
B
1.5
5.9
1.7
5.4
1.5
3.7
1.4
3.1
A
1.3
4.5
1.6
3.8
1.5
3.3
1.4
3.1
A
2.6
8.3
2.5
7.4
2.2
5.2
1.9
4.1
B
1.6
4.9
2
4.5
2
4.3
1.9
4.1
A
2.3
7
3
6
1.3
3.5
1.2
3.5
B
1.3
6.9
2.1
5.5
1.6
3.8
1.5
3.5
UNIT
ns
ns
ns
SWITCHING CHARACTERISTICS
TA = −55°C to 125°C, VCCA = 3.3 V ± 0.3 V (see Figure 4)
PARAMETER
tpd
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
A
B
11.9
11.4
9.7
9.1
B
A
10.5
9.8
9.3
9.1
A
14.3
13.4
11.2
10.1
B
11.3
10.5
10.3
10.1
ten
OE
tdis
OE
MIN
MAX
MIN
MAX
MIN
MAX
MIN
A
13
12
9.5
9.5
B
12.9
11.5
9.8
9.5
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Product Folder Links: SN74AVCB164245-EP
UNIT
MAX
ns
ns
ns
9
SN74AVCB164245-EP
SCES845A – JANUARY 2013 – REVISED FEBRUARY 2013
www.ti.com
OPERATING CHARACTERISTICS
VCCA and VCCB = 3.3 V, TA = 25°C
PARAMETER
CpdA
(VCCA)
CpdB
(VCCB)
TEST CONDITIONS
TYP
Power dissipation capacitance per transceiver,
A-port input, B-port output
Outputs enabled
Power dissipation capacitance per transceiver,
B-port input, A-port output
Outputs enabled
Outputs disabled
7
Power dissipation capacitance per transceiver,
A-port input, B-port output
Outputs enabled
20
Power dissipation capacitance per transceiver,
B-port input, A-port output
Outputs enabled
UNIT
14
Outputs disabled
CL = 0,
Outputs disabled
CL = 0,
7
f = 10 MHz
20
7
f = 10 MHz
14
Outputs disabled
pF
pF
7
OUTPUT DESCRIPTION
The DOC™ circuitry is implemented, which, during the transition, initially lowers the output impedance to
effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs
IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of
the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive
standard-output device. For more information, refer to the TI application reports, AVC Logic Family Technology
and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry Technology and
Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
− Output Voltage − V
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL − Output Voltage − V
2.8
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL − Output Current − mA
136
153
170
VCC = 2.5 V
VCC = 1.8 V
−160 −144 −128 −112 −96 −80 −64 −48
IOH − Output Current − mA
−32 −16
0
Figure 3. Typical Output Voltage vs Output Current
10
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN74AVCB164245-EP
SN74AVCB164245-EP
www.ti.com
SCES845A – JANUARY 2013 – REVISED FEBRUARY 2013
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
t pd
t PLZ/t PZL
t PHZ/t PZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
30 pF
30 pF
30 pF
500 Ω
500 Ω
500 Ω
500 Ω
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCB
Output
Control
(low-level
enabling)
VCCB /2
VCCB/2
0V
t PLZ
t PZL
VCCI
Input
VCCI/2
VCCI/2
0V
t PLH
Output
t PHL
VOH
VCCO/2
VOL
VCCO/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
t PHZ
t PZH
Output
Waveform 2
S1 at GND
(see Note B)
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 4. Load Circuit and Voltage Waveforms
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Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: SN74AVCB164245-EP
11
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
CAVCB164245MDGGEP
ACTIVE
TSSOP
DGG
48
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
AVCB164245M
CAVCB164245MDGGREP
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
AVCB164245M
V62/13602-01XE
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
AVCB164245M
V62/13602-01XE-T
ACTIVE
TSSOP
DGG
48
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
AVCB164245M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF SN74AVCB164245-EP :
• Catalog: SN74AVCB164245
• Automotive: SN74AVCB164245-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CAVCB164245MDGGRE
P
Package Package Pins
Type Drawing
TSSOP
DGG
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
24.4
Pack Materials-Page 1
8.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.0
1.8
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CAVCB164245MDGGREP
TSSOP
DGG
48
2000
367.0
367.0
45.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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