Texas Instruments | SDIO, UART, and Audio Voltage-Translation Transceiver, TWL1200-Q1 (Rev. A) | Datasheet | Texas Instruments SDIO, UART, and Audio Voltage-Translation Transceiver, TWL1200-Q1 (Rev. A) Datasheet

Texas Instruments SDIO, UART, and Audio Voltage-Translation Transceiver, TWL1200-Q1 (Rev. A) Datasheet
TWL1200-Q1
www.ti.com
SCES832A – MARCH 2012 – REVISED MARCH 2012
SDIO, UART, AND AUDIO VOLTAGE-TRANSLATION TRANSCEIVER
Check for Samples: TWL1200-Q1
FEATURES
1
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following
Results:
– Device Temperature Grade 3: –40°C to
+85°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H1C
– Device CDM ESD Classification Level C3B
Level Translator
– VCCA and VCCB Range of 1.1 V to 3.6 V
Seamlessly Bridges 1.8-V/2.6-V DigitalSwitching Compatibility Gap Between 2.6-V
processors and TI’s Wi-Link (WL1271 and
WL1273)
•
Latch-Up Performance Exceeds 100 mA per
JESD 78, Class II
36
35
34
33
32
31
30
29
28
27
26
25
SDIO_DATA0_B
SDIO_DATA3_B
SDIO_DATA1_B
SDIO_DATA2_B
VCCB
WLAN_IRQ_B
WLAN_EN_B
CLK_REQ_B
BT_EN_B
BT_UART_CTS_B
GND
BT_UART_RX_B
PFB PACKAGE
(TOP VIEW)
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
BT_UART_RTS_B
BT_UART_TX_B
AUD_IN_B
PCM_AUD_OUT_B
GND
SLOW_CLK_A
SLOW_CLK_B
PCM_AUDIO_OUT_A
AUDIO_IN_A
BT_UART_TX_A
GND
BT_UART_RX_A
SDIO_CLK_A
VCCA
SDIO_DATA3_A
SDIO_DATA1_A
SDIO_DATA2_A
WLAN_IRQ_A
WLAN_EN_A
GND
CLK_REQ_A
BT_EN_A
BT_UART_CTS_A
BT_UART_RTS_A
1
2
3
4
5
6
7
8
9
10
11
12
SDIO_CLK_B
VCCB
SDIO_CMD_B
AUDIO_F_SYNK_B
AUDIO_CLK_B
OE
AUD_DIR
VCCA
AUD_CLK_A
AUDIO_F_SYNK_A
SDIO_CMD_A
SDIO_DATA0_A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated
TWL1200-Q1
SCES832A – MARCH 2012 – REVISED MARCH 2012
www.ti.com
DESCRIPTION
The TWL1200-Q1 is a 19-bit voltage translator specifically designed to bridge seamlessly the 1.8-V/2.6-V digitalswitching compatibility gap between 2.6-V baseband and the TI Wi-Link-6 (WL1271/3). The device is optimized
for SDIO, UART, and audio functions. The TWL1200-Q1 has two supply-voltage pins, VCCA and VCCB, that can
be operated over the full range of 1.1 V to 3.6 V. The TWL1200-Q1 enables system designers easily to interface
applications processors or digital basebands to peripherals operating at a different I/O voltage levels, such as the
TI Wi-Link-6 (WL1271/3) or other SDIO/memory cards.
The TWL1200-Q1 is offered in a thin quad flat pack [TQFP (PFB)] package. Low static power consumption and
small package size make the TWL1200-Q1 an ideal choice for mobile-phone applications.
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION (1)
–40°C to 85°C
(1)
(2)
ORDERABLE
PART NUMBER
TOP-SIDE MARKING
TWL1200IPFBRQ1
TWL1200Q1
PACKAGE (2)
TA
TQFP – PFB
Tape and reel
For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
TERMINAL FUNCTIONS
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
AUD_CLK_A
45
I/O
Connected to baseband audio subsystem; drive strength = 4 mA
AUDIO_CLK_B
41
I/O
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
AUD_DIR
43
I
AUDIO_F_SYNK_A
46
I/O
Connected to baseband audio subsystem; drive strength = 4 mA
AUDIO_F_SYNK_B
40
I/O
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
AUDIO_IN_A
16
I
Connected to baseband audio subsystem
AUD_IN_B
22
O
Connected to Wi-Link-6 PCM subsystem; drive strength = 4 mA
BT_EN_A
10
I
Connected to baseband UART subsystem
BT_EN_B
28
O
Connected to BT UART subsystem of Wi-Link-6; drive strength = 2 mA
BT_UART_CTS_A
11
I
Connected to baseband UART subsystem
BT_UART_CTS_B
27
O
Connected to BT UART subsystem of Wi-Link-6; drive strength = 4 mA
BT_UART_RTS_A
12
O
Connected to baseband UART subsystem; drive strength = 4 mA
BT_UART_RTS_B
24
I
Connected to BT UART subsystem of Wi-Link-6
BT_UART_RX_A
13
I
Connected to baseband UART subsystem
BT_UART_RX_B
25
O
Connected to BT UART subsystem of Wi-Link-6; drive strength = 8 mA
BT_UART_TX_A
15
O
Connected to baseband UART subsystem; drive strength = 8 mA
BT_UART_TX_B
23
I
Connected to BT UART subsystem of Wi-Link-6
CLK_REQ_A
9
O
Connected to baseband SDIO controller; drive strength = 4 mA
CLK_REQ_B
29
I
Connected to SD/SDIO peripheral
8, 14,
20, 26
GND
Direction control signal for AUDIO_CLK and AUDIO_F-SYNC signals
Ground
OE
42
I
Output enable (active low)
PCM_AUDIO_OUT_A
17
O
Connected to baseband audio subsystem; drive strength = 4 mA
PCM_AUD_OUT_B
21
I
Connected to Wi-Link-6 PCM subsystem
SDIO_CLK_A
1
I
Clock signal connected to baseband SDIO controller. Referenced to VCCA
SDIO_CLK_B
37
O
Clock signal connected to SD/SDIO peripheral. Referenced to VCCB; drive strength = 8
mA
2
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TERMINAL FUNCTIONS (continued)
TERMINAL
NAME
NO.
TYPE
DESCRIPTION
SDIO_CMD_A
47
I/O
Command bit connected to baseband SDIO controller. Referenced to VCCA.
SDIO_CMD_B
39
I/O
Command bit connected to SD/SDIO peripheral. Includes a 15-kΩ pullup resistor to VCCB.
SDIO_DATA0_A
48
I/O
Data bit 1 connected to baseband SDIO controller
SDIO_DATA0_B
36
I/O
Data bit 0 connected to SD/SDIO peripheral
SDIO_DATA1_A
4
I/O
Data bit 1 connected to baseband SDIO controller
SDIO_DATA1_B
34
I/O
Data bit 1 connected to SD/SDIO peripheral
SDIO_DATA2_A
5
I/O
Data bit 2 connected to baseband SDIO controller
SDIO_DATA2_B
33
I/O
Data bit 2 connected to SD/SDIO peripheral
SDIO_DATA3_A
3
I/O
Data bit 3 connected to baseband SDIO controller
SDIO_DATA3_B
35
I/O
Data bit 3 connected to SD/SDIO peripheral
SLOW_CLK_A
19
I
Low frequency 32-kHz clock connected to baseband device
SLOW_CLK_B
18
O
Low frequency 32-kHz clock connected to Wi-Link-6 device; drive strength = 2 mA
VCCA
2, 44
Pwr
A-side supply voltage (1.1 V to 3.6 V)
VCCB
B-side supply voltage (1.1 V to 3.6 V)
32, 38
Pwr
WLAN_EN_A
7
I
Connected to baseband SDIO controller
WLAN_EN_B
30
O
Connected to SD/SDIO peripheral; drive strength = 2 mA
WLAN_IRQ_A
6
O
Connected to baseband SDIO controller; drive strength = 4 mA
WLAN_IRQ_B
31
I
Connected to SD/SDIO peripheral
Table 1. FUNCTION TABLE
CONTROL INPUTS
OPERATION
OE
AUD_DIR
H
X
All outputs are Hi-Z
L
H
AUDIO_CLK_A to AUDIO_CLK_B and
AUDIO_F-SYNC_A_ to AUDIO_F-SYNC_B
L
L
AUDIO_CLK_B to AUDIO_CLK_A and
AUDIO_F-SYNC_B to AUDIO_F-SYNC_A
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LOGIC DIAGRAM
VCCA
VCCB
Control
Logic
OE
BT_EANBLE(A)
BT_EANBLE(B)
BT_UART_RX(A)
BT_UART_RX(B)
BT_UART_CTS(A)
BT_UART_CTS(B)
BT_UART_TX(A)
BT_UART_TX(B)
BT_UART_RTS(A)
BT_UART_RTS(B)
AUDIO_IN(A)
AUDIO_IN(B)
AUDIO_OUT(A)
AUDIO_OUT(B)
SLOW_CLK(A)
SLOW_CLK(B)
Audio
Control
AUD_DIR
AUDIO_CLK(A)
AUDIO_CLK(B)
AUDIO_FSYNC(A)
SDIO Bit
AUDIO_F_SYNC(B)
VCCA
R1
(see Note A)
SDIO-CMD(A)
VCCB
R2
(see Note A)
One-Shot
Translator
Gate Control
One-Shot
SDIO-CMD(B)
One-Shot
Translator
One-Shot
SDIO Bit
VCCA
R1
(see Note A)
SDIO-DATA0(A)
VCCB
R2
(see Note A)
One-Shot
Translator
Gate Control
One-Shot
SDIO-DATA0(B)
One-Shot
Translator
One-Shot
SDIO Bit
VCCA
R1
(see Note A)
SDIO-DATA1(A)
VCCB
R2
(see Note A)
One-Shot
Translator
Gate Control
One-Shot
SDIO-DATA1(B)
One-Shot
Translator
One-Shot
SDIO Bit
VCCA
R1
(see Note A)
SDIO-DATA2(A)
VCCB
R2
(see Note A)
One-Shot
Translator
Gate Control
One-Shot
SDIO-DATA2(B)
One-Shot
Translator
One-Shot
SDIO Bit
R1
(see Note A)
SDIO-DATA3(A)
VCCA
VCCB
R2
(see Note A)
One-Shot
Translator
Gate Control
One-Shot
SDIO-DATA3(B)
One-Shot
Translator
One-Shot
SDIO-CLK(A)
SDIO-CLK(B)
WLAN-ENABLE(A)
4
WLAN-ENABLE(B)
WLAN-IRQ(A)
WLAN-IRQ(B)
CLK-REQ(A)
CLK-REQ(B)
A.
R1 and R2 resistor values are determined based upon the logic level applied to the A port or B port as follows:
R1 and R2 = 25 kΩ when a logic-level low is applied to the A port or B port.
R1 and R2 = 4 kΩ when a logc- level high is applied to the A port or B port.
R1 and R2 = 70 kΩ when the port is deselected (or in Hi-Z state).
B.
OE controls all output buffers. When OE = high, all outputs are Hi-Z.
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TYPICAL APPLICATION BLOCK DIAGRAM
1.8 V
2.6 V
Wi-Link-6 (WL1271/3)
Baseband Processor
VCCA
SDIO
Controller
SDIO_DATA0(A)
SDIO_DATA0(B)
SDIO_DATA1(A)
SDIO_DATA1(B)
SDIO_DATA2(A)
SDIO_DATA2(B)
SDIO_DATA3(A)
SDIO_DATA3(B)
SDIO_CMD(A)
SDIO_CMD(B)
SDIO_CLK(A)
SDIO_CLK(B)
WLAN_ENABLE(A)
WLAN_ENABLE(B)
WLAN_IRQ(A)
WLAN_IRQ(B)
CLK_REQ(A)
CLK_REQ(B)
BT_ENABLE(A)
UART
Audio
VCCB
SD/SDIO
Peripheral
BT_ENABLE(B)
TWL1200
BT_UART_RX(A)
BT_UART_RX(B)
BT_UART_CTS(A)
BT_UART_CTS(B)
BT_UART_TX(A)
BT_UART_TX(B)
BT_UART_RTS(A)
BT_UART_RTS(B)
AUDIO_IN(A)
AUDIO_IN(B)
AUDIO_CLK(A)
AUDIO_CLK(B)
AUDIO F-SYNK(A)
AUDIO F-SYNK(B)
AUDIO_OUT(A)
AUDIO_OUT(B)
SLOW_CLK(A)
BT UART
PCM
SLOW_CLK(B)
AUD_DIR (see Note A)
OE (see Note B)
GND
A.
AUD_DIR must be biased to determine audio direction (see Function Table for properly establishing the bias).
B.
OE is an active-low pin that must be grounded to 0 V to enable operation of the TWL1200-Q1 device.
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
VCCA
Supply voltage range
–0.5
4.6
V
VCCB
Supply voltage range
–0.5
4.6
V
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
VI
Input voltage range
V
VO
Voltage range applied to any output in the high-impedance or power-off
state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
150
°C
Continuous current through VCCA, VCCB, or GND
V
Tstg
Storage temperature range
ESD
rating
Human-body model (HBM) AEC-Q100 Classification Level H1C
1.5
kV
Charged-device model (CDM) AEC-Q100 Classification Level C3B
750
V
(1)
(2)
–65
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
THERMAL INFORMATION
TWL1200-Q1
THERMAL METRIC (1)
PFB
UNIT
48 PINS
θJA
Junction-to-ambient thermal resistance (2)
70.1
°C/W
θJCtop
Junction-to-case (top) thermal resistance (3)
20.8
°C/W
θJB
Junction-to-board thermal resistance (4)
32.8
°C/W
(5)
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter (6)
32.6
°C/W
θJCbot
Junction-to-case (bottom) thermal resistance (7)
N/A
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
6
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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RECOMMENDED OPERATING CONDITIONS (1)
MIN
MAX
VCCA
Supply voltage
VCCI
1.1
3.6
V
VCCB
Supply voltage
1.1
3.6
V
VCCI × 0.65
3.6
VCCA × 0.65
3.6
VCCI – 0.2
VCCI
0
VCCI × 0.35
0
VCCA × 0.35
0
0.15
V
V
VIH
High-level input voltage
VIH
High-level input voltage
Low-level input voltage
VIL
Buffer type
VCCO
1.1 V to 3.6 V
1.1 V to 3.6 V
Switch type
1.1 V to 3.6 V
1.1 V to 3.6 V
Buffer type and
Control Logic
1.1 V to 3.6 V
1.1 V to 3.6 V
OE and AUD_DIR
OE and AUD_DIR
VIL
(2)
VI
Low-level input voltage
Output voltage
IOH
1.1 V to 3.6 V
0
3.6
Active state
0
VCCO
High-impedance state
0
3.6
High-level output current
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
TA
Operating free-air temperature
(2)
1.1 V to 3.6 V
Input voltage
VO
(1)
Switch type
1.1 V to 1.3 V
–0.5
1.4 V to 1.6 V
–1
1.65 V to 1.95 V
–2
2.3 V to 2.7 V
–4
3 V to 3.6 V
–8
1.1 V to 1.3 V
0.5
1.4 V to 1.6 V
1
1.65 V to 1.95 V
2
2.3 V to 2.7 V
4
3 V to 3.6 V
8
–40
UNIT
V
V
V
V
mA
mA
5
ns/V
85
°C
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Note, the max VIL value is provided to ensure that a valid VOL is maintained. The VOL value is the VIL + the voltage-drop across the
pass-gate transistor.
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
A port
(Buffer-type output,
8-mA drive)
VOH
A port
(Buffer-type output,
4-mA drive)
VOH
A port
(Switch-type
outputs)
A port
(Buffer-type output,
8-mA drive)
VOL
A port
(Buffer-type output,
4-mA drive)
VOL
A port
(Switch-type
outputs)
B port
(Buffer-type output,
8-mA drive)
VOH
B port
(Buffer-type output,
4-mA drive)
B port
(Buffer-type output,
2-mA drive)
B port
(Switch-type
outputs)
B port
(Buffer-type output,
8-mA drive)
VOL
B port
(Buffer-type output,
4-mA drive)
B port
(Buffer-type output,
2-mA drive)
B port
(Switch-type
outputs)
II
ICCA
(1)
8
TEST CONDITIONS
IOH = –100 μA
IOH = –8 mA
IOH = –100 μA
IOH = –4 mA
IOH = –20 μA
IOL = 100 μA
IOL = 8 mA
IOL = 100 μA
IOL = 4 mA
MIN
TYP (1) MAX UNIT
VCCA
VCCB
1.1 V to 3.6 V
1.1 V to 3.6 V
1.65 V
1.65 V
1.2
2.5 V
2.5 V
1.97
1.1 V to 3.6 V
1.1 V to 3.6 V
1.65 V
1.65 V
1.2
2.5 V
2.5 V
1.97
1.65 V
1.65 V
1.5
2.5 V
2.5 V
2.3
1.1 V to 3.6 V
1.1 V to 3.6 V
0.2
1.65 V
1.65 V
0.45
VCCO – 0.2
V
VCCO – 0.2
V
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.1 V to 3.6 V
0.2
1.65 V
1.65 V
0.45
2.5 V
2.5 V
0.55
IOL = 220 μA, VIN = 0.15 V
1.65 V
1.65 V
0.45
IOL = 300 μA, VIN = 0.15 V
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.1 V to 3.6 V
1.65 V
1.65 V
1.2
2.5 V
2.5 V
1.97
1.1 V to 3.6 V
1.1 V to 3.6 V
1.65 V
1.65 V
1.2
2.5 V
2.5 V
1.97
1.1 V to 3.6 V
1.1 V to 3.6 V
1.65 V
1.65 V
1.2
2.5 V
2.5 V
1.97
1.65 V
1.65 V
1.5
2.5 V
2.5 V
2.3
1.1 V to 3.6 V
1.1 V to 3.6 V
0.2
1.65 V
1.65 V
0.45
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.1 V to 3.6 V
0.2
1.65 V
1.65 V
0.45
IOH = –100 μA
IOH = –8 mA
IOH = –100 μA
IOH = –4 mA
IOH = –100 μA
IOH = –2 mA
IOH = –20 μA
IOL = 100 μA
IOL = 8 mA
IOL = 100 μA
IOL = 4 mA
IOL = 100 μA
IOL = 2 mA
VCC0 – 0.2
V
VCC0 – 0.2
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.1 V to 3.6 V
0.2
1.65 V
1.65 V
0.45
2.5 V
2.5 V
0.55
1.65 V
1.65 V
0.45
IOL = 300 μA, VIN = 0.15 V
2.5 V
2.5 V
0.55
1.1 V to 3.6 V
1.1 V to 3.6 V
±1
1.1 V to 3.6 V
1.1 V to 3.6 V
15
3.6 V
0V
14
0V
3.6 V
–12
Switch-type I/O are open and all
other inputs are biased at either
VCC or GND
V
VCC0 – 0.2
IOL = 220 μA, VIN = 0.15 V
VI = VCCA or GND
V
V
μA
μA
All typical values are at TA = 25°C.
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SCES832A – MARCH 2012 – REVISED MARCH 2012
ELECTRICAL CHARACTERISTICS (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Switch-type I/O are open and all
other inputs are biased at either
VCC or GND
ICCB
ICCA + ICCB
VI = VCCI or GND, IO = 0
Auto-Dir (SDIO
Cio (2) lines)
Bi-Dir buffer
Ci (2)
Co (2)
(2)
TEST CONDITIONS
MIN
TYP (1) MAX UNIT
VCCA
VCCB
1.1 V to 3.6 V
1.1 V to 3.6 V
15
3.6 V
0V
–12
0V
3.6 V
14
1.1 V to 3.6 V
1.1 V to 3.6 V
30
VI = VCCI
5.5
VI = VCCX or GND
4.5
AUD_DIR / OE
VI = VCCA or GND
4
Buffer
VI = VCCX or GND
4
2-mA buffer
VI = VCCX or GND
5
4-mA buffer
VI = VCCX or GND
5
8-mA buffer
VI = VCCX or GND
6
μA
μA
pF
pF
pF
Not production tested
OUTPUT DRIVE STRENGTH
2 mA
4 mA
8 mA
WLAN_EN_B
AUDIO_OUT_A
SDIO_CLK_B
SLOW_CLK_B
WLAN_IRQ_A
BT_UART_TX_A
BT_EN_B
CLK_REQ_A
BT_UART_RX_B
AUDIO_IN_B
AUDIO_CLK_A
BT_UART CTS_B
BT_UART RTS_A
AUDIO_F-SYNC_A
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TIMING REQUIREMENTS (1)
VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
SDIO_CMD
Data rate
SDIO_CLK
SDIO_DATAx
SDIO_CMD
tW
Pulse duration
SDIO_CLK
SDIO_DATAx
(1)
Push-pull driving
60
Open-drain driving
1
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
UNIT
MAX
Mbps
50
MHz
60
Mbps
17
ns
1
μs
10
ns
17
ns
Not production tested
TIMING REQUIREMENTS (1)
VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
VCCB = 1.8 V
± 0.15 V
MIN
SDIO_CMD
Data rate
SDIO_CLK
SDIO_DATAx
SDIO_CMD
tW
Pulse duration
SDIO_CLK
SDIO_DATAx
(1)
10
Push-pull driving
60
Open-drain driving
1
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
UNIT
MAX
Mbps
50
MHz
60
Mbps
17
ns
1
μs
10
ns
17
ns
Not production tested
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SWITCHING CHARACTERISTICS (1)
VCCA = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
SDIO_CMD_A
SDIO_CMD_B
TEST CONDITIONS
VCCB = 1.8 V
± 0.15 V
MIN
Push-pull driving
7
Open-drain driving (H-to-L)
1.1
7
Open-drain driving (L-to-H)
30
510
Open-drain driving (H-to-L)
1
7.5
Open-drain driving (L-to-H)
30
515
1
6.5
1
7
1
7
7.6
Push-pull driving
SDIO_CMD_B
tpd
SDIO_CMD_A
SDIO_CLK_B
SDIO_DATAx_A
SDIO_DATAx_B
SDIO_DATAx_B
SDIO_DATAx_A
Buffered input
2-mA drive strength output
Push-pull driving
1
Buffered input
4-mA drive strength output
Push-pull driving
1
7
Buffered input
8-mA drive strength output
Push-pull driving
1
6.5
2-mA drive strength output
Push-pull driving
16
4-mA drive strength output
Push-pull driving
19
8-mA drive strength output
Push-pull driving
18
Switch-type output
Push-pull driving
1
2-mA drive strength output
Push-pull driving
17
4-mA drive strength output
Push-pull driving
16.5
8-mA drive strength output
Push-pull driving
16
Switch-type outputs
Push-pull driving
tdis
trA
OE
OE
SDIO_CMD_A rise time
SDIO_DATAx_A rise time
SDIO_CMD_B rise time
trB
SDIO_CLK_B rise time
SDIO_DATAx_B rise time
tfA
SDIO_CMD_A fall time
SDIO_DATAx_A fall time
SDIO_CMD_B fall time
tfB
SDIO_CLK_B fall time
SDIO_DATAx_B fall time
tsk(O)
Push-pull driving
Push-pull driving
1
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
1
5
15
420
1
4.7
1
9.7
15
420
0.5
6
1
9.7
Push-pull driving
0.7
8.3
Open-drain driving
1.6
8.3
Push-pull driving
1
8.3
Push-pull driving
1
9.9
1.6
10.9
0.5
5.3
1
9.9
Open-drain driving
Push-pull driving
SDIO Ch-A to Ch-B skew
Push-pull driving
0.4
SDIO Ch-B to Ch-A skew
Push-pull driving
0.4
SDIO channel-to-clock skew
Push-pull driving
1.3
Push-pull driving
60
SDIO_CMD
Max data rate
SDIO_CLK
SDIO_DATAx
(1)
7
SDIO_CLK_A
ten
Open-drain driving
Push-pull driving
UNIT
MAX
1
ns
ns
μs
ns
μs
ns
ns
ns
ns
ns
Mbps
50
MHz
60
Mbps
Not production tested
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SWITCHING CHARACTERISTICS (1)
VCCA = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
SDIO_CMD_A
SDIO_CMD_B
TEST CONDITIONS
VCCB = 1.8 V
± 0.15 V
MIN
Push-pull driving
7
Open-drain driving (H-to-L)
1.1
7
Open-drain driving (L-to-H)
30
510
Open-drain driving (H-to-L)
1
7.5
Open-drain driving (L-to-H)
30
515
1
6.5
1
7
1
7
7.6
Push-pull driving
SDIO_CMD_B
tpd
SDIO_CMD_A
SDIO_CLK_B
SDIO_DATAx_A
SDIO_DATAx_B
SDIO_DATAx_B
SDIO_DATAx_A
Buffered input
2-mA drive strength output
Push-pull driving
1
Buffered input
4-mA drive strength output
Push-pull driving
1
7
Buffered -nput
8-mA drive strength output
Push-pull driving
1
6.5
2-mA drive strength output
Push-pull driving
16
4-mA drive strength output
Push-pull driving
19
8-mA drive strength output
Push-pull driving
19
Switch-type output
Push-pull driving
1
2-mA drive strength output
Push-pull driving
17
4-mA drive strength output
Push-pull driving
16
8-mA drive strength output
Push-pull driving
16
Switch-type output
Push-pull driving
tdis
trA
OE
OE
SDIO_CMD_A rise time
SDIO_DATAx_A rise time
SDIO_CMD_B rise time
trB
SDIO_CLK_B rise time
SDIO_DATAx_B rise time
tfA
SDIO_CMD_A fall time
SDIO_DATAx_A fall time
SDIO_CMD_B fall time
tfB
SDIO_CLK_B fall time
SDIO_DATAx_B fall time
tsk(O)
Push-pull driving
Open-drain driving
Push-pull driving
Push-pull driving
Open-drain driving
Push-pull driving
1
1
15
420
1
4.25
1
9.5
15
420
0.5
5.9
1
9.6
Push-pull driving
0.7
8.2
Open-drain driving
1.6
8.2
Push-pull driving
1
8.2
Push-pull driving
1
9.2
1.6
10.8
0.5
5.2
1
9.8
Open-drain driving
Push-pull driving
0.4
SDIO Ch-B to Ch-A skew
Push-pull driving
0.4
SDIO Channel-to-Clock skew
Push-pull driving
1.3
Push-pull driving
60
SDIO_CLK
SDIO_DATAx
Open-drain driving
Push-pull driving
ns
ns
μs
ns
μs
4.25
Push-pull driving
Max data rate
12
Push-pull driving
SDIO Ch-A to Ch-B skew
SDIO_CMD
(1)
7
SDIO_CLK_A
ten
Push-pull driving
UNIT
MAX
1
ns
ns
ns
ns
ns
Mbps
50
MHz
60
Mbps
Not production tested
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SCES832A – MARCH 2012 – REVISED MARCH 2012
OPERATING CHARACTERISTICS (1)
TA = 25°C
PARAMETER
Enabled
DATAx and CMD
Disabled
Enabled
Clock
Disabled
Enabled
2-mA buffer
Disabled
Enabled
4-mA buffer
Disabled
Enabled
8-mA buffer
Disabled
Enabled
4-mA I/O
Disabled
(1)
TEST CONDITIONS
Cpd input side
VCCA = VCCB
= 1.8 V
VCCA = VCCB
= 2.5 V
18.3
20.3
18.25
19.52
0.8
0.8
Cpd output side
0.1
0.1
Cpd input side
0.6
0.9
8.8
10.1
0.1
0.1
Cpd output side
0.1
0.1
Cpd input side
0.6
1
7.1
7.9
0.1
0.1
Cpd output side
0.1
0.1
Cpd input side
0.6
1.0
7.6
8.6
0.1
0.1
0.1
0.1
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
Cpd output side
Cpd input side
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
Cpd output side
Cpd input side
Cpd output side
Cpd input side
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
Cpd output side
Cpd input side
Cpd output side
Cpd input side
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
Cpd output side
0.6
1
8.8
10.1
0.1
0.1
0.1
0.1
0.6
0.95
8.2
9.1
0.1
0.1
0.1
0.1
UNIT
pF
pF
pF
pF
pF
pF
Not production tested
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TYPICAL CHARACTERISTICS
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.25
0.28
Sw itch Type
V CCA = V CCB = 1.8 V
V IN = 0.15 V
0.24
0.26
0.23
0.25
0.22
0.24
TA = 85°C
TA = 85°C
0.23
0.21
TA = 25°C
V OL (V)
V OL (V)
Sw itch Type
V CCA = V CCB = 2.6 V
V IN = 0.15 V
0.27
0.20
TA = -40°C
0.19
TA = 25°C
0.22
0.21
TA = -40°C
0.20
0.19
0.18
0.18
0.17
0.17
0.16
0.16
0.15
0.15
0
20
40
60
80 100 120 140 160 180 200 220
0
60
90
120 150 180 210 240 270 300
IOL (µA)
IOL (µA)
Figure 1.
Figure 2.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.10
0.09
30
0.10
2-m A Buffer Type
V CCA = V CCB = 1.8 V
V IN = 0.0 V
0.09
0.08
2-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 0.0 V
0.08
TA = 85°C
0.07
0.07
0.06
0.06
TA = 25°C
V OL (V)
V OL (V)
TA = 85°C
0.05
0.04
0.05
TA = 25°C
0.04
TA = -40°C
0.03
0.03
0.02
0.02
0.01
0.01
0.00
TA = -40°C
0.00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.0
0.2
IOL (m A)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
IOL (m A)
Figure 3.
14
0.4
Figure 4.
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TYPICAL CHARACTERISTICS (continued)
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.15
0.15
4-m A Buffer Type
V CCA = V CCB = 1.8 V
V IN = 0.0 V
0.14
0.13
0.13
0.12
0.12
0.11
0.11
TA = 85°C
0.10
0.10
0.09
V OL (V)
0.09
V OL (V)
4-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 0.0 V
0.14
TA = 25°C
0.08
0.07
TA = 85°C
0.08
0.07
TA = 25°C
0.06
0.06
TA = -40°C
0.05
0.05
0.04
0.04
0.03
0.03
0.02
0.02
0.01
0.01
TA = -40°C
0.00
0.00
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
0.0
4.0
0.4
0.8
1.2
1.6
2.4
2.8
3.2
3.6
4.0
7.2
8.0
IOL (m A)
IOL (m A)
Figure 5.
Figure 6.
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
0.20
0.20
8-m A Buffer Type
V CCA = V CCB = 1.8 V
V IN = 0.0 V
0.18
8-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 0.0 V
0.18
0.16
0.16
0.14
0.14
TA = 85°C
0.12
V OL (V)
0.12
V OL (V)
2.0
TA = 25°C
0.10
0.08
TA = 85°C
0.10
TA = 25°C
0.08
0.06
0.06
TA = -40°C
0.04
0.04
0.02
0.02
0.00
TA = -40°C
0.00
0.0
0.8
1.6
2.4
3.2
4.0
4.8
5.6
6.4
7.2
8.0
0.0
0.8
1.6
2.4
3.2
4.0
IOL (m A)
IOL (m A)
Figure 7.
Figure 8.
4.8
5.6
6.4
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TYPICAL CHARACTERISTICS (continued)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
1.81
1.80
1.79
2.61
Sw itch Type
V CCA = V CCB = 1.8 V
V IN = 1.8 V
2.60
2.59
1.78
2.58
2.57
TA = -40°C
V OH (V)
V OH (V)
1.77
1.76
1.75
TA = 25°C
2.56
TA = -40°C
2.55
TA = 25°C
1.74
2.54
TA = 85°C
1.73
2.52
1.71
2.51
-18
-16
-14
-12
TA = 85°C
2.53
1.72
1.70
-20
Sw itch Type
V CCA = V CCB = 2.6 V
V IN = 2.6 V
-10
-8
-6
-4
-2
2.50
-20
0
-18
-16
-14
-12
IOH (µA)
1.79
-8
-6
Figure 9.
Figure 10.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
-4
-2
0
2.61
1.81
1.80
-10
IOH (µA)
2-m A Buffer Type
V CCA = V CCB = 1.8 V
V IN = 1.8 V
2.60
2.59
2-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 2.6 V
1.78
2.58
1.77
2.57
TA = -40°C
V OH (V)
V OH (V)
1.76
1.75
1.74
TA = 25°C
1.73
1.72
TA = -40°C
2.56
TA = 25°C
2.55
2.54
TA = 85°C
TA = 85°C
2.53
1.71
2.52
1.70
16
1.69
2.51
1.68
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
2.50
-2.0 -1.8 -1.6 -1.4 -1.2 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
IOH (m A)
IOH (m A)
Figure 11.
Figure 12.
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TYPICAL CHARACTERISTICS (continued)
1.81
1.80 4-m A Buffer Type
1.79 V CCA = V CCB = 1.8 V
1.78 V IN = 1.8 V
1.77
1.76
1.75
1.74
TA = -40°C
1.73
1.72
1.71
TA = 25°C
1.70
1.69
TA = 85°C
1.68
1.67
1.66
1.65
1.64
1.63
-4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.61
2.60
2.59
2.57
2.56
1.77
2.50
2.49
2.48
-4.0 -3.6 -3.2 -2.8 -2.4 -2.0 -1.6 -1.2 -0.8 -0.4 0.0
IOH (m A)
Figure 13.
Figure 14.
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.61
8-m A Buffer Type
V CCA = V CCB = 1.8 V
V IN = 1.8 V
2.59
8-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 2.6 V
2.57
2.55
TA = -40°C
2.53
V OH (V)
V OH (V)
TA = 85°C
IOH (m A)
1.69
TA = 25°C
TA = -40°C
2.51
TA = 25°C
2.49
1.65
1.63
TA = 25°C
2.54
2.51
1.73
1.67
2.55
2.52
1.75
1.71
TA = -40°C
2.53
1.81
1.79
4-m A Buffer Type
V CCA = V CCB = 2.6 V
V IN = 2.6 V
2.58
V OH (V)
V OH (V)
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
2.47
TA = 85°C
1.61
TA = 85°C
2.45
1.59
2.43
1.57
1.55
-8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0
2.41
-8.0 -7.2 -6.4 -5.6 -4.8 -4.0 -3.2 -2.4 -1.6 -0.8 0.0
IOH (m A)
IOH (m A)
Figure 15.
Figure 16.
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TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME (HIGH TO LOW)
vs
LOAD CAPACITANCE
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
LOAD CAPACITANCE
6
6
Sw itch Type
TA = -40°C
5
5
4
4
t PD(L-H) (ns)
t PD(H-L) (ns)
Sw itch Type
TA = -40°C
V CCA = V CCB = 1.8 V
3
V CCA = V CCB = 1.8 V
3
2
2
V CCA = V CCB = 2.6 V
V CCA = V CCB = 2.6 V
1
1
0
0
0
10
20
30
40
50
0
60
30
40
50
CL (pF)
Figure 17.
Figure 18.
PROPAGATION DELAY TIME (HIGH TO LOW)
vs
LOAD CAPACITANCE
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
LOAD CAPACITANCE
60
6
Sw itch Type
TA = 25°C
Sw itch Type
TA = 25°C
5
5
4
4
V CCA = V CCB = 1.8 V
t PD(L-H) (ns)
t PD(H-L) (ns)
20
CL (pF)
6
3
2
V CCA = V CCB = 1.8 V
3
2
V CCA = V CCB = 2.6 V
V CCA = V CCB = 2.6 V
1
1
0
0
0
18
10
10
20
30
40
50
60
0
10
20
30
CL (pF)
CL (pF)
Figure 19.
Figure 20.
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40
50
60
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TYPICAL CHARACTERISTICS (continued)
PROPAGATION DELAY TIME (HIGH TO LOW)
vs
LOAD CAPACITANCE
PROPAGATION DELAY TIME (LOW TO HIGH)
vs
LOAD CAPACITANCE
6
6
Sw itch Type
TA = 85°C
Sw itch Type
TA = 85°C
5
5
V CCA = V CCB = 1.8 V
4
t PD(L-H) (ns)
t PD(H-L) (ns)
4
3
2
V CCA = V CCB = 1.8 V
3
2
V CCA = V CCB = 2.6 V
V CCA = V CCB = 2.6 V
1
1
0
0
0
10
20
30
40
50
60
0
10
20
30
CL (pF)
CL (pF)
Figure 21.
Figure 22.
40
50
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19
TWL1200-Q1
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Typical Application Wiring for TWL1200-Q1 When Connecting to the WL1271
Table 2. WL1271+TWL1200-Q1 Interface
HOST
(MSM)
20
PIN NAME
BALL
NO.
TYPE
TYPE
BALL
NO.
PIN NAME
VCCA
C4
Power (3 V)
Power (1.8 V)
C5
VCCB
WL1271
COB
VCCA
D4
Power (3 V)
Power (1.8 V)
D5
VCCB
SDIO_DATA0_A
B2
I/O ↔
I/O ↔
B6
SDIO_DATA0_B
K4
SDIO_DATA1_A
C2
I/O ↔
I/O ↔
C6
SDIO_DATA1_B
J4
SDIO_DATA2_A
C1
I/O ↔
I/O ↔
C7
SDIO_DATA2_B
J3
SDIO_DATA3_A
B1
I/O ↔
I/O ↔
B7
SDIO_DATA3_B
J5
SDIO_CMD_A
A2
I/O ↔
I/O ↔
A6
SDIO_CMD_B
L3
SDIO_CLK_A
A1
I→
O→
A7
SDIO_CLK_B
M3
WLAN_EN_A
D1
I→
O→
D6
WLAN_EN_B
J2
WLAN_IRQ_A
D2
O←
I←
D7
WLAN_IRQ_B
G4
CLK_REQ_A
E1
O←
I←
E7
CLK_REQ_B
F5
G5
BT_EN_A
E2
I→
BT_UART_RX_A
G1
I→
O→
E6
BT_EN_B
O→
G7
BT_UART_RX_B
BT_UART_CTS_A
F1
G7
I→
O→
F7
BT_UART_CTS_B
E11
BT_UART_TX_A
G2
O←
I←
G6
BT_UART_TX_B
G8
BT_UART_RTS_A
F2
O←
I←
F6
BT_UART_RTS_B
G11
AUDIO_IN_A
F3
I→
I/O ↔
F5
AUDIO_IN_B
F6
AUDIO_CLK_A
A3
I/O ↔
I/O ↔
A5
AUDIO_CLK_B
F8
AUDIO_F-SYN_A
B3
I/O ↔
I/O ↔
B5
AUDIO_F-SYN_B
H11
AUDIO_OUT_A
G3
O←
I←
G5
AUDIO_OUT_B
F7
SLOW_CLK_A
G4
I→
O→
F4
SLOW_CLK_B
K9
AUD_DIR
A4
I→
GND
D3
GND
OE
B4
Active low
E3
GND
E4
GND
E5
GND
TWL1200Q1
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SCES832A – MARCH 2012 – REVISED MARCH 2012
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT FOR
BUFFER-TYPE OUTPUTS
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO/2
VOH − VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 23. Push-Pull Buffered Direction-Control Load Circuit and Voltage Waveform
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PARAMETER MEASUREMENT INFORMATION (continued)
VCCI
VCCO
VCCI
VCCO
DUT
IN
DUT
IN
OUT
OUT
1 MW
15 pF
15 pF
1 MW
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
AN OPEN-DRAIN DRIVER
DATA RATE, PULSE DURATION, PROPAGATION DELAY,
OUTPUT RISE AND FALL TIME MEASUREMENT USING
A PUSH-PULL DRIVER
From Output
Under Test
15 pF
1 MW
LOAD CIRCUIT FOR ENABLE/DISABLE TIME MEASUREMENT −
SWITCH-TYPE SDIOs
tw
VCCI
VCCI/2
Input
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
OE
VCCI
Input
VCCI/2
VCCI/2
Input
0V
tPLH
Output
tPHL
VCCO/2
0.9 y VCCO
0.1 y VCCO
tr
VOH
VCCO/2
VOL
tf
Output
ten
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
J. All parameters and waveforms are not applicable to all devices.
Figure 24. Auto-Direction-Control Load Circuit and Voltage Waveform
22
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SCES832A – MARCH 2012 – REVISED MARCH 2012
APPLICATION CIRCUIT EXAMPLES
VCCB
VCCA
C
C
TWL1200
C4
D4
C5
D5
BT_PCM30_DO
BT_PCM_DO
F3
F5
BT_PCM30_CLK
BT_PCM_CLK
A3
A5
BT_PCM30_SYNC
BT_PCM_SYNC
B3
B5
A4
VCCA
VCCA
VCCB
VCCB
AUDIO_IN(A)
AUDIO_IN(B)
CLK_REQ(A)
CLK_REQ(B)
SDIO_CLK(A)
SDIO_CLK(B)
SDIO_CMD(A)
SDIO_CMD(B)
AUDIO_CLK(A)
AUDIO_CLK(B)
SDIO_DATA0(A)
SDIO_DATA1(A)
AUDIO_F-SYN(A) SDIO_DATA2(A)
AUDIO_F-SYN(B) SDIO_DATA3(A)
AUD_DIR
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
BT_PCM30_DI
BT_PCM_DI
G3
G5
BT_EN30
BT_EN
E2
E6
BT_EN(A)
BT_EN(B)
BT_UART30_RTS
BT_UART_RTS
F1
F7
BT_UART_CTS(A)
BT_UART_CTS(B)
WLAN_EN(A)
WLAN_EN(B)
BT_IRQ30
BT_UART30_CTS
BT_UART_CTS
F2
F6
BT_UART_RTS(A)
BT_UART_RTS(B)
WLAN_IRQ(A)
WLAN_IRQ(B)
BT_UART30_TXD
BT_UART_TXD
G1
G7
BT_UART30_RXD
BT_UART_RXD
G2
G6
B4
AUDIO_OUT(A)
AUDIO_OUT(B)
SLOW_CLK(A)
SLOW_CLK(B)
E1
E7
A1
A7
A2
A6
B2
C2
C1
B1
B6
C6
C7
B7
G4
F4
D1
D6
D2
D7
WLAN_SDIO30_CLK
WLAN_SDIO_CLK
WLAN_SDIO30_CMD
WLAN_SDIO_CMD
WLAN_SDIO30_D0
WLAN_SDIO30_D1
WLAN_SDIO30_D2
WLAN_SDIO30_D3
WLAN_SDIO_D0
WLAN_SDIO_D1
WLAN_SDIO_D2
WLAN_SDIO_D3
CLK32_COMBO
CLK32_COMBO18
WLAN_EN30
WLAN_EN
WLAN_IRQ30
WLAN_IRQ
BT_UART_RX(A)
BT_UART_RX(B)
BT_UART_TX(A)
BT_UART_TX(B)
OE
GND
GND
GND
GND
D3
E3
E4
E5
R
Figure 25. Application Circuit Example, OE Connection With Audio_CLK and Audio_F-SYNC Channels
Established From B Side to A Side
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TWL1200-Q1
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VCCB
C
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VCCA
C
TWL1200
C4
D4
C5
D5
BT_PCM30_DO
BT_PCM_DO
F3
F5
BT_PCM30_CLK
BT_PCM_CLK
A3
A5
BT_PCM30_SYNC
BT_PCM_SYNC
B3
B5
VCCA
R
A4
R
VCCA
VCCA
VCCB
VCCB
AUDIO_IN(A)
AUDIO_IN(B)
CLK_REQ(A)
CLK_REQ(B)
SDIO_CLK(A)
SDIO_CLK(B)
SDIO_CMD(A)
SDIO_CMD(B)
AUDIO_CLK(A)
AUDIO_CLK(B)
SDIO_DATA0(A)
SDIO_DATA1(A)
AUDIO_F-SYN(A) SDIO_DATA2(A)
AUDIO_F-SYN(B) SDIO_DATA3(A)
AUD_DIR
SDIO_DATA0(B)
SDIO_DATA1(B)
SDIO_DATA2(B)
SDIO_DATA3(B)
BT_PCM30_DI
BT_PCM_DI
G3
G5
BT_EN30
BT_EN
E2
E6
BT_EN(A)
BT_EN(B)
BT_UART30_RTS
BT_UART_RTS
F1
F7
BT_UART_CTS(A)
BT_UART_CTS(B)
WLAN_EN(A)
WLAN_EN(B)
BT_UART30_CTS
BT_UART_CTS
F2
F6
BT_UART_RTS(A)
BT_UART_RTS(B)
WLAN_IRQ(A)
WLAN_IRQ(B)
BT_UART30_TXD
BT_UART_TXD
G1
G7
BT_UART30_RXD
BT_UART_RXD
G2
G6
B4
BT_WLAN_LEVEL_EN
AUDIO_OUT(A)
AUDIO_OUT(B)
SLOW_CLK(A)
SLOW_CLK(B)
E1
E7
A1
A7
A2
A6
B2
C2
C1
B1
B6
C6
C7
B7
G4
F4
D1
D6
D2
D7
WLAN_SDIO30_CLK
WLAN_SDIO_CLK
WLAN_SDIO30_CMD
WLAN_SDIO_CMD
WLAN_SDIO30_D0
WLAN_SDIO30_D1
WLAN_SDIO30_D2
WLAN_SDIO30_D3
WLAN_SDIO_D0
WLAN_SDIO_D1
WLAN_SDIO_D2
WLAN_SDIO_D3
CLK32_COMBO
CLK32_COMBO18
WLAN_EN30
WLAN_EN
WLAN_IRQ30
WLAN_IRQ
BT_UART_RX(A)
BT_UART_RX(B)
BT_UART_TX(A)
BT_UART_TX(B)
OE
GND
GND
GND
GND
D3
E3
E4
E5
R
VCCA
Figure 26. Application Circuit Example, With Voltage Divider for AUD_DIR Connection
24
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SCES832A – MARCH 2012 – REVISED MARCH 2012
PRINCIPLES OF OPERATION
Applications
The TWL1200-Q1 device has been designed to bridge the digital-switching compatibility gap between two
voltage nodes to interface successfully the logic threshold levels between a host processor and the Texas
Instruments Wi-Link-6 WLAN/BT/FM products. The device is intended to be used in a point-to-point topology
when interfacing these devices that may or may not be operating at different interface voltages.
Architecture
The BT/UART and PCM/Audio subsystem interfaces consist of a fully-buffered voltage translator design that has
its output transistors to source and sink current optimized for drive strength.
The SDIO lines constitute a semi-buffered auto-direction-sensing based translator architecture (see Figure 27)
that does not require a direction-control signal to control the direction of data flow of the A to B ports (or from B
to A ports).
VCCA
VCCB
R1
One-Shot
T1
One-Shot
T2
R2
Translator
SDIO-DATAx(A)
SDIO-DATAx(B)
Bias
N1
T3
One-Shot
Translator
T4
One-Shot
Figure 27. Architecture of an SDIO Switch-Type Cell
Each of these bidirectional SDIO channels independently determines the direction of data flow without a
direction-control signal. Each I/O pin can be automatically reconfigured as either an input or an output, which is
how this auto-direction feature is realized.
The following two key circuits are employed to facilitate the switch-type voltage-translation function:
1. Integrated pullup resistors to provide dc-bias and drive capabilities
2. An N-channel pass-gate transistor topology (with a high RON of approximately 300 Ω) that ties the A-port to
the B-port
3. Output one-shot (O.S.) edge-rate accelerator circuitry to detect and accelerate rising edges on the A or B
ports
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For bidirectional voltage translation, pullup resistors are included on the device for dc current-sourcing capability.
The VGATE gate bias of the N-channel pass transistor is set at a level that optimizes the switch characteristics for
maximum data rate as well as minimal static supply leakage. Data can flow in either direction without guidance
from a control signal.
The edge-rate acceleration circuitry speeds up the output slew rate by monitoring the input edge for transitions,
helping maintain the data rate through the device.
During a low-to-high rising edge of a signal, the O.S. circuits turn on the PMOS transistors (T1,
associated driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω
acceleration phase to increase the current drive capability of the driver for approximately 30 ns or
input edge, whichever occurs first. This edge-rate acceleration provides high ac drive by bypassing
pullup resistors during the low-to-high transition to speed up the rising-edge signal.
T3) and its
during this
95% of the
the internal
During a high-to-low signal falling-edge, the O.S. circuits turn on the NMOS transistors (T2, T4) and its associated
driver output resistance of the driver is decreased to approximately 50 Ω to 70 Ω during this acceleration phase
to increase the current drive capability of the driver for approximately 30 ns or 95% of the input edge, whichever
occurs first.
To minimize dynamic ICC and the possibility of signal contention, the user should wait for the O.S. circuit to turn
off before applying a signal in the opposite direction. The worst-case duration is equal to the minimum pulseduration number provided in the Timing Requirements section of this data sheet.
Once the O.S. is triggered and switched off, both the A and B ports must go to the same state (that is, both High
or both Low) for the one-shot to trigger again. In a dc state, the output drivers maintain a Low state through the
pass transistor. The output drivers maintain a High through the smart pullup resistors that dynamically change
value based on whether a Low or a High is being passed through the SDIO lines, as follows:
• RPU1 and RPU2 values are 25 kΩ when the output is driving a low.
• RPU1 and RPU2 values are 4 kΩ when the output is driving a high.
• RPU1 and RPU2 values are 70 kΩ when the device is disabled via the OE pin or by pulling the either VCCA or
VCCB to 0 V.
The reason for using these smart pullup resistors is to allow the TWL1200-Q1 to realize a lower static power
consumption (when the I/Os are low), support lower VOL values for the same size pass-gate transistor, and
improved simultaneous switching performance.
Input Driver Requirements
The continuous dc-current sinking capability is determined by the external system-level driver interfaced to the
SDIO pins. Because the high bandwidth of these bidirectional SDIO circuits necessitates a port quickly changing
from an input to an output (and vice-vera), they have a modest dc-current sourcing capability of hundreds of
microamps, as determined by the smart pullup resistor values.
The fall time (tfA, tfB) of a signal depends on the edge rate and output impedance of the external device driving
the SDIO I/Os, as well as the capacitive loading on these lines.
Similarly, the tpd and maximum data rates also depend on the output impedance of the external driver. The
values for tfA, tfB, tpd, and maximum data rates in the data sheet assume that the output impedance of the
external driver is less than 50 Ω.
Output Load Considerations
TI recommends careful PCB layout practices with short PCB trace lengths to avoid excessive capacitive loading
and to ensure that proper O.S. triggering takes place. PCB signal trace-lengths should be kept short enough
such that the round trip delay of any reflection is less than the one-shot duration. This improves signal integrity
by ensuring that any reflection sees a low impedance at the driver. The O.S. circuits have been designed to stay
on for approximately 30 ns. The maximum capacitance of the lumped load that can be driven also depends
directly on the one-shot duration. With very heavy capacitive loads, the one-shot can time-out before the signal is
driven fully to the positive rail. The O.S. duration has been set to best optimize trade-offs between dynamic ICC,
load driving capability, and maximum bit-rate considerations. Both PCB trace length and connectors add to the
capacitance that the TWL1200-Q1 SDIO output sees, so it is recommended that this lumped-load capacitance be
considered and kept below 75 pF to avoid O.S. retriggering, bus contention, output signal oscillations, or other
adverse system-level affects.
26
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PACKAGE OPTION ADDENDUM
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11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
TWL1200IPFBRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
TQFP
PFB
48
1000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-3-260C-168 HR
(4)
-40 to 85
TWL1200Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TWL1200-Q1 :
• Catalog: TWL1200
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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11-Apr-2013
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TWL1200IPFBRQ1
Package Package Pins
Type Drawing
TQFP
PFB
48
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
16.4
Pack Materials-Page 1
9.6
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
9.6
1.5
12.0
16.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TWL1200IPFBRQ1
TQFP
PFB
48
1000
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998
PFB (S-PQFP-G48)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
36
0,08 M
25
37
24
48
13
0,13 NOM
1
12
5,50 TYP
7,20
SQ
6,80
9,20
SQ
8,80
Gage Plane
0,25
0,05 MIN
0°– 7°
1,05
0,95
Seating Plane
0,75
0,45
0,08
1,20 MAX
4073176 / B 10/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
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