Texas Instruments | CD4010B-Q1 CMOS Hex Buffer/Converter (Rev. A) | Datasheet | Texas Instruments CD4010B-Q1 CMOS Hex Buffer/Converter (Rev. A) Datasheet

Texas Instruments CD4010B-Q1 CMOS Hex Buffer/Converter (Rev. A) Datasheet
CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
www.ti.com
CMOS HEX BUFFER/CONVERTER
Check for Samples: CD4010B-Q1
FEATURES
1
•
•
•
•
•
Qualified for Automotive Applications
100% Tested for Quiescent Current at 20 V
Maximum Input Current of 1 µA at 18 V Over
Full Package-Temperature Range:
100 nA at 18 V and 25°C
5-V, 10-V, and 15-V Parametric Ratings
Latch-Up Performance Meets 100 mA per
JESD 78, Class I
D PACKAGE
(TOP VIEW)
APPLICATIONS
•
•
•
•
CMOS to DTL/TTL Hex Converter
CMOS Current "Sink" or "Source" Driver
CMOS High-to-Low Logic-Level Converter
Multiplexer: 1-to-6 or 6-to-1
DESCRIPTION
CD4010B hex buffer/converter may be used as CMOS to TTL or DTL logic-level converters or CMOS
high-sink-current drivers.
The CD4050B is the preferred hex buffer replacement for the CD4010B in all applications except multiplexers.
For applications not requiring high sink current or voltage conversion, the CD4069UB hex inverter is
recommended.
The CD4010B is supplied in 16-lead hermetic dual-in-line ceramic (D) packages.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 125°C
(1)
(2)
SOIC – D
Reel of 2500
ORDERABLE PART NUMBER
CD4010BQDRQ1
TOP-SIDE MARKING
CD4010BQ
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
Figure 1. Schematic Diagram – One of Six Identical Stages
Functional Diagram
2
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CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
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ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VDD
DC supply voltage range, voltages referenced to VSS terminal
Input voltage range, all inputs
DC input current, any one input
PD
Power dissipation per package
Device dissipation per output
transistor
VALUE
UNIT
–0.5 to +20
V
–0.5 to VDD +0.5
V
±10
mA
TA = –40°C to +100°C
500
TA = +100°C to +125°C
Derate linearly at
12 mW/°C to 200 mW
mW
100
mW
°C
TA = full package-temperature range
(all packages types)
TA
Operating temperature range
–40 to +125
Tstg
Storage temperature range
–65 to +150
°C
100
mA
Latch-up performance per JESD 78, Class I
Human-body model (HBM)
ESD
(1)
(2)
Electrostatic discharge rating (2)
500
Machine model (MM)
100
Charged-Device Model (CDM)
1000
V
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Tested in accordance with AEC-Q100.
RECOMMENDED OPERATING CONDITIONS
MIN
VDD
VCC
VI
(1)
Supply voltage range (1)
Input voltage range
MAX
3
18
3
VDD
VCC
VDD
UNIT
V
V
The CD4010B has high-to-low level voltage conversion capability, but not low-to-high level; therefore, it is recommended that
VDD > VI > VCC.
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CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
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STATIC ELECTRICAL CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
IDD Max
TEST CONDITIONS
LIMITS AT INDICATED TEMPERATURES (°C)
VO
VDD
–40
+85
+125
Quiescent device current
0.4
IOL Min
Output low (sink) current
IOH Min
Output high (source) current
VOL Max
VOH Min
VIL Max
VIH Min
IIN Max
4
Input current
UNIT
TYP
MAX
0, 5
5
1
30
30
0.02
1
0, 10
10
2
60
60
0.02
2
0, 15
15
4
120
120
0.02
4
0.04
20
0,20
20
20
600
600
0, 5
4.5
3.1
2.1
1.8
2.6
0, 5
5
3.6
2.4
2.1
3
4
0, 10
10
9.6
6.4
5.6
8
10
1.5
0, 15
15
40
19
16
24
36
4.6
0, 5
5
–0.23
–0.18
–0.15
–0.2
–0.4
2.5
0, 5
5
–0.9
–0.65
–0.58
–0.8
–1.6
9.5
0, 10
10
–0.5
–0.38
–0.33
–0.45
–0.9
13.5
0, 15
15
–1.6
–1.25
–1.1
–1.5
–3
mA
mA
0, 5
5
0.05
0
0.05
0, 10
10
0.05
0
0.05
0, 15
15
0.05
0
0.05
0, 5
5
4.95
4.95
5
0, 10
10
9.95
9.95
10
0, 15
15
14.95
14.95
15
0.5
5
1.5
1
10
3
3
1.5
15
4
4
4.5
5
3.5
9
10
7
7
13.5
15
11
11
0, 18
18
±0.1
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±1
µA
3.4
0.5
Output voltage: High-level
Input high voltage
+25
MIN
0.4
Output voltage: Low-level
Input low voltage
VIN
V
V
1.5
V
3.5
±1
V
±10–5
±0.1
µA
Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Link(s): CD4010B-Q1
CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
www.ti.com
DYNAMIC ELECTRICAL CHARACTERISTICS
TA = 25°C, Input tr/tf = 20 ns, CL = 50 pf, RL = 200 kΩ
TEST CONDITIONS
PARAMETER
tPLH
tPHL
tTLH
Propagation delay time: low-to-high
Propagation time: high-to-low
Transition time: low-to-high
tTHL
Transition time: high-to-low
CIN
Input capacitance
VDD
(V)
VI
(V)
LIMITS ALL PKGS
VCC
(V)
TYP
MAX
5
5
5
100
200
10
10
10
50
100
10
10
5
50
100
15
15
15
35
70
15
15
5
35
70
5
5
5
65
130
10
10
10
35
70
10
10
5
30
70
15
15
15
25
50
15
15
5
20
40
5
5
5
150
350
10
10
10
75
150
15
15
15
55
110
5
5
5
35
90
10
10
10
20
45
15
15
15
15
40
5
7.5
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UNIT
ns
ns
ns
ns
pF
5
CD4010B-Q1
SCHS379A – MARCH 2010 – REVISED JANUARY 2012
www.ti.com
TYPICAL CHARACTERISTICS
6
Figure 2. Minimum and Maximum Voltage Transfer
Characteristics (VDD = 5 V)
Figure 3. Minimum and Maximum Voltage Transfer
Characteristics (VDD = 10 V)
Figure 4. Minimum and Maximum Voltage Transfer
Characteristics (VDD = 15 V)
Figure 5. Typical Voltage Transfer Characteristics as a
Function of Temperature
Figure 6. Typical Output Low (Sink) Current
Characteristics
Figure 7. Minimum Output Low (Sink) Current
Characteristics
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SCHS379A – MARCH 2010 – REVISED JANUARY 2012
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TYPICAL CHARACTERISTICS (continued)
Figure 8. Typical Output High (Source) Current
Characteristics
Figure 9. Minimum Output High (Source) Current
Characteristics
Figure 10. Typical Low-to-High Propagation Delay Time vs
Load Capacitance
Figure 11. Typical High-to-Low Propagation Delay Time vs
Load Capacitance
Figure 12. Typical Low-to-High Transition Time vs Load
Capacitance
Figure 13. Typical High-to-Low Transition Time vs Load
Capacitance
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TYPICAL CHARACTERISTICS (continued)
Figure 14. Typical Dissipation Characteristics
8
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PARAMETER MEASUREMENT INFORMATION
Figure 15. Quiescent Device Current Test Circuit
Figure 16. Noise Immunity Test Circuit
Figure 17. Input Current Test Circuit
Note:
Dimensions in parentheses are in millimeters and are dereived from the basic inch dimensions as indicated. Grid
graduation are in mils (10–3 inch).
Figure 18. Dimensions and Layout
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SCHS379A – MARCH 2010 – REVISED JANUARY 2012
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REVISION HISTORY
Changes from Original (March 2010) to Revision A
•
10
Page
Changed STATIC ELECTRICAL CHARACTERISTICS table to correct typos and misplaced data .................................... 4
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
CD4010BQDRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
16
2500
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-1-260C-UNLIM
(4)
-40 to 125
CD4010BQ
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD4010B-Q1 :
• Catalog: CD4010B
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Military: CD4010B-MIL
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
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