Texas Instruments | CD54HC4094, CD74HC4094, CD74HCT4094 (Rev. E) | Datasheet | Texas Instruments CD54HC4094, CD74HC4094, CD74HCT4094 (Rev. E) Datasheet

Texas Instruments CD54HC4094, CD74HC4094, CD74HCT4094 (Rev. E) Datasheet
CD54HC4094, CD74HC4094,
CD74HCT4094
Data sheet acquired from Harris Semiconductor
SCHS211E
November 1997 − Revised December 2010
High−Speed CMOS Logic
8−Stage Shift and Store Bus Register, Three−State
Features
¥ Buffered Inputs
[ /Title
(CD74H
C4094,
CD74H
CT4094
)
/Sub−
ject
(High
Speed
CMOS
Logic 8−
¥ Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading
¥ Fanout (Over Temperature Range)
− Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
− Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
¥ Wide Operating T emperature Rang e . . . −55oC to 125oC
¥ Balanced Propagation Delay and Transition Times
¥ Signi cant Power Reduction Compared to LSTTL
Logic ICs
¥ HC Types
− 2V to 6V Operation
− High Noise Immunity: NIL = 30%, NIH = 30% of VCC
at VCC = 5V
¥ HCT Types
− 4.5V to 5.5V Operation
− Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
− CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH
Description
The ÕHC4094and CD74HCT4094 are 8−stage serial shift
registers having a storage latch associated with each stage
for strobing data from the serial input to parallel buffered
three−state outputs. The parallel outputs may be connected
directly to common bus lines. Data is shifted on positive
clock transitions. The data in each shift register stage is
transferred to the storage register when the Strobe input is
high. Data in the storage register appears at the outputs
whenever the Output−Enable signal is high.
Two serial outputs are available for cascading a number of
these devices. Data is available at the QS1 serial output
terminal on positive clock edges to allow for high−speed
operation in cascaded system in which the clock rise time is
fast. The same serial information, available at the QS2
terminal on the next negative clock edge, provides a means
for cascading these devices when the clock rise time is slow.
Ordering Information
TEMP. RANGE
(o C)
PACKAGE
CD54HC4094F3A
−55 to 125
16 Ld CERDIP
CD74HC4094E
−55 to 125
16 Ld PDIP
CD74HC4094M
−55 to 125
16 Ld SOIC
CD74HC4094MT
−55 to 125
16 Ld SOIC
CD74HC4094M96G3
−55 to 125
16 Ld SOIC
CD74HC4094NSR
−55 to 125
16 Ld SOP
CD74HC4094PW
−55 to 125
16 Ld TSSOP
CD74HC4094PWR
−55 to 125
16 Ld TSSOP
CD74HC4094PWT
−55 to 125
16 Ld TSSOP
CD74HCT4094E
−55 to 125
16 Ld PDIP
CD74HCT4094M
−55 to 125
16 Ld SOIC
CD74HCT4094MT
−55 to 125
16 Ld SOIC
CD74HCT4094M96
−55 to 125
16 Ld SOIC
PART NUMBER
NOTE: When ordering, use the entire part number. The suf xes 96
and R denote tape and reel. The suf x T denotes a small−quantity
reel of 250.
Pinout
CD54HC4094 (CERDIP)
CD74HC4094 (PDIP, SOIC, SOP, TSSOP)
CD74HCT4094 (PDIP, SOIC)
TOP VIEW
STROBE
1
16 V CC
DATA
2
15 OE
CP
3
14 Q 4
Q0
4
13 Q 5
Q1
5
12 Q 6
Q2
6
11 Q 7
Q3
7
10 QS 2
GND
8
9 QS 1
CAUTION: These devices are sensitive to electrostatic discharge . Users should follow proper IC Handling Procedures .
Copyright
2003, Texas Instruments Incorporated
−1−
CD54HC4094, CD74HC4094, CD74HCT4094
Functional Diagram
DATA
CP
STROBE
2
3
1
8−STAGE
SHIFT
REGISTER
9
QS1
10
QS2
8−BIT
STORAGE
REGISTER
4
Q0
5
Q1
6
15
OE
THREE−
STATE
OUTPUT
Q2
7
14
13
12
11
Q3
Q4
Q5
Q6
Q7
GND = 8
VCC = 16
TRUTH TABLE
INPUTS
PARALLEL OUTPUTS
SERIAL OUTPUTS
CP
OE
STR
D
Q0
Qn
QS1 (NOTE 1)
QS2
↑
L
X
X
Z
Z
QÕ6
NC
↓
L
X
X
Z
Z
NC
Q7
↑
H
L
X
NC
NC
QÕ6
NC
↑
H
H
L
L
Qn −1
QÕ6
NC
↑
H
H
H
H
Qn −1
QÕ6
NC
↓
H
H
H
NC
NC
NC
Q7
H = High Voltage Level, L = Low Voltage Level, X = DonÕt Care, NC = No charge, Z = High Impedance Off−state,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
NOTE:
1. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.
−2−
−3−
OE
STR
CP
DATA
15
1
3
2
Q
CP
CP
FFO
D
LO
OE OE
4
Q0
Q
STR STR
FF1
L1
FF2
5
Q1
L2
FF3
6
Q2
L3
FF4
7
Q3
L4
FF5
14
Q4
L5
FF6
13
Q5
L6
FF7
12
Q6
D
L7
Q
11
Q7
CP
L8
CP
QS2
QS1
10
9
CD54HC4094, CD74HC4094, CD74HCT4094
Logic Diagram
CD54HC4094, CD74HC4094, CD74HCT4094
Absolute Maximum Ratings
Thermal Information
DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . −0.5V to 7V
DC Input Diode Current, IIK
For VI < −0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < −0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > −0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Package Thermal Impedance, θJA (see Note 2):
E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
. 7oC/W
M (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
. 3oC/W
NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6. 4oC/W
PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . .108oC/W
Maximum Junction Temperature (Plastic Package) . . . . . . . . . 150o
Maximum Storage Temperature Range . . . . . . . . . . .−65oC to 150o
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . 300o
SOIC − Lead Tips Only)
Operating Conditions
Temperature Range (TA ) . . . . . . . . . . . . . . . . . . . . .−55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2V
. to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5V
.
to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .400ns (Max)
CAUTION: Stresses above those listed in ÒAbsoluteMaximum RatingsÓmay cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the oper ational sections of this speci cation is not implied.
NOTE:
2. The package thermal impedance is calculated in accordance with JESD 51−7.
DC Electrical Speci cations
TEST
CONDITIONS
PARAMETER
25oC
−40oC TO 85oC −55oC TO 125oC
SYMBOL
VI (V)
IO (mA)
VCC
(V)
VIH
−
−
2
1.5
−
−
1.5
4.5
3.15
−
−
3.15
−
3.15
−
V
6
4.2
−
−
4.2
−
4.2
−
V
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
−
1.5
−
V
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
VIL
VOH
−
VIH or VIL
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
−
2
−
−
0.5
−
0.5
−
0.5
V
4.5
−
−
1.35
−
1.35
−
1.35
V
6
−
−
1.8
−
1.8
−
1.8
V
−0.02
2
1.9
−
−
1.9
−
1.9
−
V
−0.02
4.5
4.4
−
−
4.4
−
4.4
−
V
−0.02
6
5.9
−
−
5.9
−
5.9
−
V
−
−
−
−
−
−
−
−
−
V
−4
4.5
3.98
−
−
3.84
−
3.7
−
V
−5.2
6
5.48
−
−
5.34
−
5.2
−
V
0.02
2
−
−
0.1
−
0.1
−
0.1
V
0.02
4.5
−
−
0.1
−
0.1
−
0.1
V
0.02
6
−
−
0.1
−
0.1
−
0.1
V
−
−
−
−
−
−
−
−
−
V
4
4.5
−
−
0.26
−
0.33
−
0.4
V
5.2
6
−
−
0.26
−
0.33
−
0.4
V
II
VCC or
GND
−
6
−
−
±0.1
−
±1
−
±1
μA
ICC
VCC or
GND
0
6
−
−
8
−
80
−
160
μA
−4−
CD54HC4094, CD74HC4094, CD74HCT4094
DC Electrical Speci cations
(Continued)
TEST
CONDITIONS
PARAMETER
SYMBOL
VI (V)
IO (mA)
High Level Input
Voltage
VIH
−
−
Low Level Input
Voltage
VIL
−
High Level Output
Voltage
CMOS Loads
VOH
VIH or VIL
VCC
(V)
25oC
−40oC TO 85oC −55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
4.5 to
5.5
2
−
−
2
−
2
−
V
−
4.5 to
5.5
−
−
0.8
−
0.8
−
0.8
V
−0.02
4.5
4.4
−
−
4.4
−
4.4
−
V
−4
4.5
3.98
−
−
3.84
−
3.7
−
V
0.02
4.5
−
−
0.1
−
0.1
−
0.1
V
4
4.5
−
−
0.26
−
0.33
−
0.4
V
HCT TYPES
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
VOL
VIH or VIL
Low Level Output
Voltage
TTL Loads
II
VCC and
GND
0
5.5
−
−
±0.1
−
±1
−
±1
μA
ICC
VCC or
GND
0
5.5
−
−
8
−
80
−
160
μA
ΔICC
(Note 3)
VCC
−2.1
−
4.5 to
5.5
−
100
360
−
450
−
490
μA
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE:
3. For dual−supply systems theoretical worst case (VI = 2.4V, V CC = 5.5V) specification is 1.8mA.
HCT Input Loading Table
INPUT
UNIT LOADS
D
0.4
CP, OE
1.5
STR
1.0
NOTE: Unit Load is ΔICC limit speci ed in DC Electrical Table, e.g.,
360μA max at 25oC.
Prerequisite for Switching Speci cations
25oC
CHARACTERISTIC
−40oC TO 85oC
−55o C TO 125oC
SYMBOL
VCC (V)
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
tW
2
80
−
100
−
120
−
ns
4.5
16
−
20
−
24
−
ns
6
14
−
17
−
20
−
ns
2
80
−
100
−
120
−
ns
4.5
16
−
20
−
24
−
ns
6
14
−
17
−
20
−
ns
HC TYPES
CP Pulse Width
STR Pulse Width
tWH
−5−
CD54HC4094, CD74HC4094, CD74HCT4094
Prerequisite for Switching Speci cations
(Continued)
25oC
CHARACTERISTIC
Data Set−up Time
Data Hold Time
STR Set−up Time
STR Hold Time
Maximum CP Frequency
SYMBOL
VCC (V)
tSU
tH
tSU
tH
fCL (MAX)
MIN
−40oC TO 85oC
MAX
MIN
MAX
−55o C TO 125oC
MIN
MAX
UNITS
2
50
−
65
−
75
−
ns
4.5
10
−
13
−
15
−
ns
6
9
−
11
−
13
−
ns
2
3
−
3
−
3
−
ns
4.5
3
−
3
−
3
−
ns
6
3
−
3
−
3
−
ns
2
100
−
125
−
150
−
ns
4.5
20
−
25
−
30
−
ns
6
17
−
21
−
26
−
ns
2
0
−
0
−
0
−
ns
4.5
0
−
0
−
0
−
ns
6
0
−
0
−
0
−
ns
2
6
−
5
−
4
−
MHz
4.5
30
−
24
−
20
−
MHz
6
35
−
28
−
24
−
MHz
HCT TYPES
CP Pulse Width
tW
4.5
16
−
20
−
24
−
ns
STR Pulse Width
tWH
4.5
16
−
20
−
24
−
ns
Data Set−up Time
tSU
4.5
10
−
13
−
15
−
ns
Data Hold Time
STR Set−up Time
STR Hold Time
Maximum CP Frequency
Switching Speci cations
PARAMETER
HC TYPES
Propagation Delay Time
(Figure 1)
tH
4.5
4
−
4
−
4
−
ns
tSU
4.5
20
−
25
−
30
−
ns
tH
4.5
0
−
0
−
0
−
ns
fCL (MAX)
4.5
30
−
24
−
20
−
MHz
Input tr, tf = 6ns
TEST
SYMBOL CONDITIONS
tPLH,
tPHL
CP to Qn
STR to Qn
tPLH,
tPHL
tPLH,
tPHL
tPLH,
tPHL
−40oC TO 85oC −55oC TO 125oC
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
−
−
150
−
190
−
225
ns
4.5
−
−
30
−
38
−
45
ns
CL =15pF
5
−
12
−
−
−
−
−
ns
CL = 50pF
6
−
−
26
−
33
−
38
ns
CL = 50pF
CP to QS1
CP to QS2
25oC
VCC
(V)
CL = 50pF
2
−
−
135
−
170
−
205
ns
4.5
−
−
27
−
34
−
41
ns
CL =15pF
5
−
11
−
−
−
−
−
ns
CL = 50pF
6
−
−
23
−
29
−
35
ns
CL = 50pF
2
−
−
195
−
245
−
295
ns
CL = 50pF
−6−
4.5
−
−
39
−
49
−
59
ns
5
−
16
−
−
−
−
−
ns
6
−
−
33
−
42
−
50
ns
2
−
−
180
−
225
−
270
ns
4.5
−
−
36
−
45
−
54
ns
6
−
−
31
−
38
−
46
ns
CD54HC4094, CD74HC4094, CD74HCT4094
Switching Speci cations
PARAMETER
Output Enable to Qn
Output Disable to Qn
Output Transition Time
Output Disabling Time
Maximum CP Frequency
Input tr, tf = 6ns (Continued)
TEST
SYMBOL CONDITIONS
tPZH, tPZL CL = 50pF
tPHZ, tPLZ CL = 50pF
tTLH , tTHL CL = 50pF
tPHZ, tPLZ CL =15pF
fMAX
CL =15pF
25oC
−40oC TO 85oC −55oC TO 125oC
VCC
(V)
MIN
TYP
MAX
MIN
MAX
MIN
MAX
UNITS
2
−
−
175
−
220
−
265
ns
4.5
−
−
35
−
44
−
53
ns
6
−
−
30
−
37
−
45
ns
2
−
−
125
−
155
−
190
ns
4.5
−
−
25
−
31
−
38
ns
6
−
−
21
−
26
−
32
ns
2
−
−
75
−
95
−
110
ns
4.5
−
−
15
−
19
−
22
ns
6
−
−
13
−
16
−
19
ns
5
−
10
−
−
−
−
−
ns
5
−
60
−
−
−
−
−
MHz
Input Capacitance
CIN
CL = 50pF
−
−
−
10
−
10
−
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL =15pF
5
−
90
−
−
−
−
−
pF
Three−State Output
Capacitance
CO
CL = 50pF
−
−
−
15
−
15
−
15
pF
tPLH,
tPHL
CL = 50pF
4.5
−
−
39
−
−
−
−
ns
CL =15pF
5
−
16
−
−
−
−
−
ns
tPLH,
tPHL
CL = 50pF
4.5
−
−
36
−
−
−
−
ns
CL =15pF
5
−
15
−
−
−
−
−
ns
CP to Qn
tPLH,
tPHL
CL = 50pF
4.5
−
−
43
−
−
−
−
ns
CL =15pF
5
−
18
−
−
−
−
−
ns
STR to Qn
tPLH,
tPHL
CL = 50pF
4.5
−
−
39
−
−
−
−
ns
tPZH, tPZL CL = 50pF
4.5
−
−
35
−
−
−
−
ns
Output Disable to Qn
tPHZ, tPLZ CL = 50pF
4.5
−
−
35
−
−
−
−
ns
Output Transition Time
tTLH , tTHL CL = 50pF
4.5
−
−
15
−
−
−
−
ns
Output Disabling Time
tPHZ, tPLZ CL =15pF
HCT TYPES
Propagation Delay Time
(Figure 1)
CP to QS1
CP to QS2
Output Enable to Qn
5
−
14
−
−
−
−
−
ns
Maximum CP Frequency
fMAX
CL =15pF
5
−
60
−
−
−
−
−
MHz
Input Capacitance
CIN
CL = 50pF
−
−
−
10
−
10
−
10
pF
Power Dissipation Capacitance
(Notes 4, 5)
CPD
CL =15pF
5
−
110
−
−
−
−
−
pF
Three−State Output
Capacitance
CO
CL = 50pF
−
−
−
15
−
15
−
15
pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per register.
5. PD = VCC 2 fi (CPD + CL) where fi = Input Frequency, C L = Output Load Capacitance, VCC = Supply Voltage.
−7−
CD54/74HC4094, CD74HCT4094
Test Circuits and Waveforms
6ns
6ns
90%
VS
10%
CLOCK
tSU
tH
INPUT LEVEL
VS
GND
tW
tW
INPUT LEVEL
SERIAL IN
tPLH
GND
tPHL
VS
Qn, QS1
VOH
VOL
tPHL
VOH
tPLH
VS
VOL
QS2
FIGURE 1. DATA PROPAGATION DELAYS, SET−UP AND HOLD TIMES
INPUT LEVEL
SERIAL IN
GND
tSU
tH
VS
CLOCK
VS
tPLZ
OUTPUT
LOW TO OFF
VOH
OUTPUT
HIGH TO OFF
OUTPUTS
CONNECTED
VOH
VS
VOL
FIGURE 2. STROBE PROPAGATION DELAYS AND SET−UP
AND HOLD TIMES
−8−
90%
10%
tPZL
VS
10%
tPHZ
VOL
tPLH, tPHL
Qn
OE
GND
VS
STROBE
tf = 6ns
INPUT LEVEL
VS
tW
tr = 6ns
tPZH
90%
OUTPUTS
DISCONNECTED
VS
OUTPUTS
CONNECTED
FIGURE 3. ENABLE AND DISABLE TIMES
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CD54HC4094F3A
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
CD54HC4094F3A
CD74HC4094E
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HC4094E
CD74HC4094M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96G3
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094M96G4
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094MT
ACTIVE
SOIC
D
16
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094NSR
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094NSRE4
ACTIVE
SO
NS
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HC4094M
CD74HC4094PW
ACTIVE
TSSOP
PW
16
90
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWR
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWRE4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HC4094PWRG4
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HJ4094
CD74HCT4094E
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4094E
CD74HCT4094EE4
ACTIVE
PDIP
N
16
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-55 to 125
CD74HCT4094E
CD74HCT4094M
ACTIVE
SOIC
D
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
HCT4094M
CD74HCT4094M96
ACTIVE
SOIC
D
16
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-55 to 125
HCT4094M
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
Orderable Device
24-Aug-2018
Status
(1)
CD74HCT4094ME4
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SOIC
D
16
40
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 125
HCT4094M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF CD54HC4094, CD74HC4094 :
• Catalog: CD74HC4094
Addendum-Page 2
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
• Military: CD54HC4094
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Military - QML certified for Military and Defense Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
CD74HC4094M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4094M96
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4094M96G3
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4094M96G4
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
CD74HC4094NSR
SO
NS
16
2000
330.0
16.4
8.2
10.5
2.5
12.0
16.0
Q1
CD74HC4094PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD74HC4094PWR
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD74HC4094PWRG4
TSSOP
PW
16
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
CD74HCT4094M96
SOIC
D
16
2500
330.0
16.8
6.5
10.3
2.1
8.0
16.0
Q1
CD74HCT4094M96
SOIC
D
16
2500
330.0
16.4
6.5
10.3
2.1
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CD74HC4094M96
SOIC
D
16
2500
333.2
345.9
28.6
CD74HC4094M96
SOIC
D
16
2500
364.0
364.0
27.0
CD74HC4094M96G3
SOIC
D
16
2500
364.0
364.0
27.0
CD74HC4094M96G4
SOIC
D
16
2500
333.2
345.9
28.6
CD74HC4094NSR
SO
NS
16
2000
367.0
367.0
38.0
CD74HC4094PWR
TSSOP
PW
16
2000
364.0
364.0
27.0
CD74HC4094PWR
TSSOP
PW
16
2000
367.0
367.0
35.0
CD74HC4094PWRG4
TSSOP
PW
16
2000
367.0
367.0
35.0
CD74HCT4094M96
SOIC
D
16
2500
364.0
364.0
27.0
CD74HCT4094M96
SOIC
D
16
2500
333.2
345.9
28.6
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2018, Texas Instruments Incorporated
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