Texas Instruments | SN74LV125A-Q1, Quadruple Bus Buffer Gates With 3-State Outputs | Datasheet | Texas Instruments SN74LV125A-Q1, Quadruple Bus Buffer Gates With 3-State Outputs Datasheet

Texas Instruments SN74LV125A-Q1, Quadruple Bus Buffer Gates With 3-State Outputs Datasheet
SN74LV125A-Q1
www.ti.com
SCES814 – SEPTEMBER 2010
QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS
Check for Samples: SN74LV125A-Q1
FEATURES
1
•
•
1A
1Y
2OE
2A
2Y
VCC
RGY PACKAGE
(TOP VIEW)
1
14
2
13 4OE
3
12 4A
4
11 4Y
5
10 3OE
9 3A
6
GND
7
8
3Y
•
Qualified for Automotive Applications
2-V to 5.5-V VCC Operation
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
Ioff Supports Partial-Power-Down Mode
Operation
1OE
•
•
•
DESCRIPTION
The SN74LV125A-Q1 quadruple bus buffer gate is designed for 2-V to 5.5-V VCC operation.
This device features independent line drivers with 3-state outputs. Each output is disabled when the associated
output-enable (OE) input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION
TA
–40°C to 125°C
(1)
PACKAGE
QFN – RGY
(1)
Reel of 3000
ORDERABLE PART NUMBER
SN74LV125AQRGYRQ1
TOP-SIDE MARKING
LV125Q
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN74LV125A-Q1
SCES814 – SEPTEMBER 2010
www.ti.com
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
10
1
3OE
1OE
2
9
3
1A
1Y
8
3A
3Y
13
4
4OE
2OE
6
5
2A
11
12
2Y
4A
4Y
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
7
UNIT
V
(2)
VI
Input voltage range
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
V
VO
Output voltage range (2)
–0.5
VCC + 0.5
V
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
47
°C/W
150
°C
(3)
Continuous current through VCC or GND
qJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
2
(4)
RGY package
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-5.
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SN74LV125A-Q1
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SCES814 – SEPTEMBER 2010
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
4.5
5.5
Low-level input voltage
VI
VCC = 2.3 V to 2.7 V
VCC x 0.7
VCC = 3 V to 3.6 V
VCC x 0.7
VCC = 4.5 V to 5.5 V
VCC x 0.7
Output voltage
VCC = 2.3 V to 2.7 V
VCC x 0.3
VCC = 3 V to 3.6 V
VCC x 0.3
VCC = 4.5 V to 5.5 V
VCC x 0.3
0
5.5
High or low state
0
VCC
3-state
0
5.5
VCC = 2 V
IOH
High-level output current
VCC = 2.3 V to 2.7 V
–2
VCC = 3 V to 3.6 V
–8
Δt/Δv
Input transition rise or fall rate
(1)
V
mA
50
VCC = 2.3 V to 2.7 V
2
VCC = 3 V to 3.6 V
8
VCC = 4.5 V to 5.5 V
16
VCC = 2.3 V to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 V to 5.5 V
TA
V
–16
VCC = 2 V
Low-level output current
V
–50
VCC = 4.5 V to 5.5 V
IOL
V
0.5
Input voltage
VO
V
1.5
VCC = 2 V
VIL
UNIT
mA
ns/V
20
Operating free-air temperature
–40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
MIN
2 V to 5.5 V
IOH = –2 mA
2.3 V
IOH = –8 mA
3V
2.48
4.5 V
3.8
IOH = –16 mA
VOL
VCC
IOH = –50 mA
TYP
MAX
2
V
IOL = 50 mA
2 V to 5.5 V
0.1
IOH = 2 mA
2.3 V
0.4
IOH = 8 mA
3V
0.44
4.5 V
0.55
IOL = 16 mA
UNIT
VCC–0.1
V
II
VI = 5.5 V or GND
0 to 5.5 V
±1
mA
IOZ
VO = VCC or GND
5.5 V
±5
mA
ICC
VI = VCC or GND, IO = 0
5.5 V
20
mA
Ioff
VI or VO = 0 to 5.5 V
0
5
mA
Ci
VI = VCC or GND
3.3 V
1.6
5V
1.6
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pF
3
SN74LV125A-Q1
SCES814 – SEPTEMBER 2010
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
LOAD
CAPACITANCE
TA=
-40°C to 125°C
TA =25°C
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
8.7
ten
OE
Y
8.8
tdis
OE
Y
7.3
PARAMETER
MIN
CL = 50 pF
TYP MAX
tsk(o)
UNIT
MIN
MAX
16.5
1
18.5
ns
16.5
1
18.5
ns
18.2
1
20.5
ns
2
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
ten
OE
Y
tdis
OE
Y
PARAMETER
LOAD
CAPACITANCE
TA=
-40°C to 125°C
TA = 25°C
MIN
CL = 50 pF
TYP MAX
MIN
MAX
UNIT
6.1
11.5
1
13
ns
6.2
11.5
1
13
ns
5.5
13.2
1
15
ns
tsk(o)
1.5
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
LOAD
CAPACITANCE
TO
(OUTPUT)
tpd
A
Y
4.3
7.5
10
ns
ten
OE
Y
4.4
7.1
10
ns
tdis
OE
Y
4
8.8
11
ns
MIN
CL = 50 pF
tsk(o)
4
TA=
-40°C to 125°C
TA =25°C
FROM
(INPUT)
PARAMETER
TYP MAX
1
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MIN
UNIT
MAX
ns
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): SN74LV125A-Q1
SN74LV125A-Q1
www.ti.com
SCES814 – SEPTEMBER 2010
NOISE CHARACTERISTICS (1)
VCC = 3.3 V, CL = 50 pF, TA = 25°C
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
MIN
0.4
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–0.8
V
VOH(V)
Quiet output, minimum dynamic VOH
3
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
UNIT
V
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
Outputs enabled
TEST CONDITIONS
VCC
TYP
CL = 50
pF,
3.3 V
15.5
5V
17.6
f = 10
MHz
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UNIT
pF
5
SN74LV125A-Q1
SCES814 – SEPTEMBER 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
RL = 1 kΩ
From Output
Under Test
Test
Point
From Output
Under Test
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% V CC
Timing Input
0V
tw
tsu
VCC
50% V CC
50% V CC
Input
th
VCC
50% V CC
Data Input
50% V CC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% V CC
Input
50% V CC
50% V CC
50% V CC
VOH
50% V CC
VOL
50% V CC
0V
tPLZ
Output
Waveform 1
S1 at V CC
(see Note B)
tPLH
tPHL
Out-of-Phase
Output
VOH
50% V CC
VOL
50% V CC
tPZL
tPHL
tPLH
In-Phase
Output
0V
VCC
Output
Control
≈V CC
50% V CC
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
50% V CC
VOH
0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C L includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. t PZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74LV125AQRGYRQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VQFN
RGY
14
2000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-3-260C-168 HR
(4)
-40 to 125
LV125Q
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV125A-Q1 :
• Catalog: SN74LV125A
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV125AQRGYRQ1
Package Package Pins
Type Drawing
VQFN
RGY
14
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
3.75
B0
(mm)
K0
(mm)
P1
(mm)
3.75
1.15
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV125AQRGYRQ1
VQFN
RGY
14
2000
367.0
367.0
35.0
Pack Materials-Page 2
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