Texas Instruments | SN74AVC2T45-Q1 Dual-Bit Dual-Supply Bus Transceiver | Datasheet | Texas Instruments SN74AVC2T45-Q1 Dual-Bit Dual-Supply Bus Transceiver Datasheet

Texas Instruments SN74AVC2T45-Q1 Dual-Bit Dual-Supply Bus Transceiver Datasheet
SN74AVC2T45-Q1
www.ti.com
SCES813 – JUNE 2010
DUAL-BIT DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
Check for Samples: SN74AVC2T45-Q1
FEATURES
•
•
•
•
1
•
•
•
•
Qualified for Automotive Applications
Control Inputs VIH/VIL Levels Are Referenced to
VCCA Voltage
Fully Configurable Dual-Rail Design Allows
Each Port to Operate Over the Full 1.2-V to
3.6-V Power-Supply Range
I/Os Are 4.6-V Tolerant
Ioff Supports Partial-Power-Down Mode
Operation
Max Data Rates
– 500 Mbps (1.8-V to 3.3-V Translation)
– 320 Mbps (<1.8-V to 3.3-V Translation)
– 320 Mbps (Translate to 2.5 V or 1.8 V)
– 280 Mbps (Translate to 1.5 V)
– 240 Mbps (Translate to 1.2 V)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 8000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
VCCA
A1
A2
GND
1
8
2
7
3
6
4
5
VCCB
B1
B2
DIR
DESCRIPTION
This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is
designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track
VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional
translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.
The SN74AVC2T45 is designed for asynchronous communication between two data buses. The logic levels of
the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data
from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the
A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic
HIGH or LOW level applied to prevent excess ICC and ICCZ.
The SN74AVC2T45 is designed so that the DIR input is powered by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 105°C
(1)
(2)
VSSOP – DCU
Reel of 3000
ORDERABLE PART NUMBER
CAVC2T45TDCURQ1
TOP-SIDE MARKING
SBUI
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN74AVC2T45-Q1
SCES813 – JUNE 2010
www.ti.com
FUNCTION TABLE (1)
(EACH TRANSCEIVER)
(1)
INPUT
DIR
OPERATION
L
B data to A bus
H
A data to B bus
Input circuits of the data I/Os always are active.
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
A1
5
2
7
A2
3
6
VCCA
2
B1
B2
VCCB
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SCES813 – JUNE 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
VI
MIN
MAX
–0.5
4.6
I/O ports (A port)
–0.5
4.6
I/O ports (B port)
–0.5
4.6
Control inputs
–0.5
4.6
A port
–0.5
4.6
B port
–0.5
4.6
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
Supply voltage range
Input voltage range
(2)
UNIT
V
V
VO
Voltage range applied to any output in the high-impedance or
power-off state (2)
VO
Voltage range applied to any output in the high or low state (2)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
227
°C/W
150
°C
(3)
Continuous current through VCCA, VCCB, or GND
qJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
(4)
DCU package
–65
V
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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RECOMMENDED OPERATING CONDITIONS (1) (2) (3) (4) (5)
MIN
MAX
VCCA
Supply voltage
VCCI
1.2
3.6
V
VCCB
Supply voltage
1.2
3.6
V
VIH
High-level
input voltage
Low-level
input voltage
VIL
High-level
input voltage
VIH
Low-level
input voltage
VIL
VI
Input voltage
VO
Output voltage
IOH
Data inputs (4)
Data inputs (4)
DIR
(referenced to VCCA) (5)
DIR
(referenced to VCCA) (5)
2
1.2 V to 1.95 V
VCCI × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
1.2 V to 1.95 V
VCCA × 0.65
1.95 V to 2.7 V
1.6
2.7 V to 3.6 V
2
1.2 V to 1.95 V
VCCA × 0.35
1.95 V to 2.7 V
0.7
2.7 V to 3.6 V
0.8
VCCO
0
3.6
Operating free-air temperature
1.2 V
–3
1.4 V to 1.6 V
–6
1.65 V to 1.95 V
–8
2.3 V to 2.7 V
–9
3 V to 3.6 V
–12
1.2 V
3
1.4 V to 1.6 V
6
1.65 V to 1.95 V
8
2.3 V to 2.7 V
9
3 V to 3.6 V
12
5
–40
V
V
0
Low-level output current
UNIT
V
3-state
TA
4
1.6
2.7 V to 3.6 V
Active state
Input transition rise or fall rate
(4)
(5)
VCCI × 0.65
1.95 V to 2.7 V
3.6
Δt/Δv
(1)
(2)
(3)
1.2 V to 1.95 V
0
High-level output current
IOL
VCCO
105
V
V
V
mA
mA
ns/V
°C
VCCI is the VCC associated with the input port.
VCCO is the VCC associated with the output port.
All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
For VCCI values not specified in the data sheet, VIH min = VCCI × 0.7 V, VIL max = VCCI × 0.3 V.
For VCCI values not specified in the data sheet, VIH min = VCCA × 0.7 V, VIL max = VCCA × 0.3 V.
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ELECTRICAL CHARACTERISTICS (1) (2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 mA
IOH = –3 mA
IOH = –6 mA
VOH
IOH = –8 mA
VI = VIH
IOH = –9 mA
II
Ioff
IOZ
B port
B port
A port
ICCA
TA = 25°C
MIN
TYP
–40°C to 105°C
MAX
MIN MAX
VCCO – 0.2 V
1.4 V
1.4 V
1.05
1.65 V
1.2
2.3 V
2.3 V
1.75
2.3
3V
1.2 V
1.2 V
V
0.2
0.25
1.4 V
1.4 V
0.35
1.65 V
1.65 V
0.45
IOL = 9 mA
2.3 V
2.3 V
0.55
IOL = 12 mA
3V
3V
0.7
1.2 V to 3.6 V
1.2 V to 3.6 V
±0.025
±0.25
±1
0V
0 to 3.6 V
±0.1
±1
±5
0 to 3.6 V
0V
±0.1
±1
±5
VI = VIL
VI = VCCA or GND
VI or VO = 0 to 3.6 V
VO = VCCO or GND,
VI = VCCI or GND
VI = VCCI or GND, IO = 0
UNIT
0.95
1.65 V
1.2 V to 3.6 V
VI = VCCI or GND, IO = 0
ICCA + ICCB
(see Table 1)
1.2 V
3V
VI = VCCI or GND, IO = 0
ICCB
1.2 V to 3.6 V
1.2 V
1.2 V to 3.6 V
IOL = 8 mA
A port
1.2 V to 3.6 V
IOL = 100 mA
IOL = 6 mA
DIR
VCCB
IOH = –12 mA
IOL = 3 mA
VOL
VCCA
0V
3.6 V
±0.5
±2.5
±5
3.6 V
0V
±0.5
±2.5
±5
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
–2
3.6 V
0V
10
1.2 V to 3.6 V
1.2 V to 3.6 V
10
0V
3.6 V
10
3.6 V
0V
–2
1.2 V to 3.6 V
1.2 V to 3.6 V
20
V
mA
mA
mA
mA
mA
mA
CI
Control
inputs
VI = 3.3 V or GND
3.3 V
3.3 V
2.5
pF
Cio
A or B
port
VO = 3.3 V or GND
3.3 V
3.3 V
6
pF
(1)
(2)
VCCO is the VCC associated with the output port.
VCCI is the VCC associated with the input port.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.2 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.8 V
VCCB = 2.5 V
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3.1
2.6
2.4
2.2
2.2
3.1
2.6
2.4
2.2
2.2
3.4
3.1
3
2.9
2.9
3.4
3.1
3
2.9
2.9
5.2
5.2
5.1
5
4.8
5.2
5.2
5.1
5
4.8
5
4
3.8
2.8
3.2
5
4
3.8
2.8
3.2
8.4
7.1
6.8
5.7
6.1
8.4
7.1
6.8
5.7
6.1
8.3
7.8
7.5
7.2
7
8.3
7.8
7.5
7.2
7
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
6
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.8
0.7
5.6
0.5
4.8
0.4
3.9
0.3
3.7
2.8
0.7
5.6
0.5
4.8
0.4
3.9
0.3
3.7
2.7
0.8
5.6
0.7
5.4
0.6
5.1
0.5
4.9
2.7
0.8
5.6
0.7
5.4
0.6
5.1
0.5
4.9
3.9
1.3
8.7
1.3
8
1.1
7.9
1.4
7.8
3.9
1.3
8.7
1.3
8
1.1
7.9
1.4
7.8
4.7
1.1
7.2
1.4
7.1
1.2
7.1
1.7
7.3
4.7
1.1
7.2
1.4
7.1
1.2
7.1
1.7
7.3
7.4
12.6
12.3
12
12
7.4
12.6
12.3
12
12
6.7
14.1
12.6
11.6
11.3
6.7
14.1
12.6
11.6
11.3
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
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SCES813 – JUNE 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.7
0.5
5.4
0.4
4.5
0.2
3.6
0.2
3.3
2.7
0.5
5.4
0.4
4.5
0.2
3.6
0.2
3.3
2.4
0.7
4.9
0.5
4.6
0.5
4.2
0.4
4
2.4
0.7
4.9
0.5
4.6
0.5
4.2
0.4
4
3.7
1.3
8.3
0.7
7.1
1.4
5.5
1.1
5.4
3.7
1.3
8.3
0.7
7.1
1.4
5.5
1.1
5.4
4.4
1.3
6
1.3
6.1
0.8
5.9
1.5
6.1
4.4
1.3
6
1.3
6.1
0.8
5.9
1.5
6.1
6.8
10.7
10.5
9.9
9.9
6.8
10.7
10.5
9.9
9.9
6.4
13.5
11.4
8.9
8.5
6.4
13.5
11.4
8.9
8.5
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.6
0.4
5.1
0.2
4.2
0.2
3.2
0.2
2.8
2.6
0.4
5.1
0.2
4.2
0.2
3.2
0.2
2.8
2.1
0.6
4
0.5
3.6
0.4
3.2
0.3
3
2.1
0.6
4
0.5
3.6
0.4
3.2
0.3
3
2.4
0.7
8.1
0.8
6.6
0.8
5.2
0.5
4.5
2.4
0.7
8.1
0.8
6.6
0.8
5.2
0.5
4.5
3.8
1
4.5
0.6
4.5
0.5
4.4
1.1
4.3
3.8
1
4.5
0.6
4.5
0.5
4.4
1.1
4.3
5.9
8.7
7.9
7.4
7.1
5.9
8.7
7.9
7.4
7.1
5
13
10.6
8.2
7.1
5
13
10.6
8.2
7.1
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
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SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCCA = 3.3 V ± 0.3 V (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
DIR
A
DIR
B
DIR
A
DIR
B
tPLH
tPHL
tPLH
tPHL
tPHZ
tPLZ
tPHZ
tPLZ
(1)
tPZH
(1)
tPZL
(1)
tPZH
(1)
tPZL
(1)
VCCB = 1.2 V
VCCB = 1.5 V
± 0.1 V
VCCB = 1.8 V
± 0.15 V
VCCB = 2.5 V
± 0.2 V
VCCB = 3.3 V
± 0.3 V
TYP
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
2.5
0.3
4.9
0.2
4
0.2
3
0.2
2.6
2.5
0.3
4.9
0.2
4
0.2
3
0.2
2.6
2.1
0.6
3.8
0.4
3.3
0.3
2.8
0.3
2.6
2.1
0.6
3.8
0.4
3.3
0.3
2.8
0.3
2.6
2.9
1.1
8.2
1
6.7
1.3
4.9
1.2
4.2
2.9
1.1
8.2
1
6.7
1.3
4.9
1.2
4.2
3.4
0.5
6.8
0.3
5.8
0.3
4.8
1.1
4.4
3.4
0.5
6.8
0.3
5.8
0.3
4.8
1.1
4.4
5.5
10.4
8.9
7.4
6.8
5.5
10.4
8.9
7.4
6.8
5.4
12.9
10.5
7.7
6.6
5.4
12.9
10.5
7.7
6.6
UNIT
ns
ns
ns
ns
ns
ns
The enable time is a calculated value, derived using the formula shown in the enable times section.
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
CpdA
CpdB
(1)
8
(1)
A-port input,
B-port output
B-port input,
A-port output
(1)
A-port input,
B-port output
B-port input,
A-port output
TEST
CONDITIONS
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
VCCA =
VCCB = 1.2 V
VCCA =
VCCB = 1.5 V
VCCA =
VCCB = 1.8 V
VCCA =
VCCB = 2.5 V
VCCA =
VCCB = 3.3 V
TYP
TYP
TYP
TYP
TYP
3
3
3
3
4
12
13
13
14
15
12
13
13
14
15
3
3
3
3
4
UNIT
pF
CL = 0,
f = 10 MHz,
tr = tf = 1 ns
pF
Power-dissipation capacitance per transceiver
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SCES813 – JUNE 2010
Power-Up Considerations
A proper power-up sequence always should be followed to avoid excessive supply current, bus contention,
oscillations, or other anomalies. To guard against such power-up problems, take the following precautions:
1. Connect ground before any supply voltage is applied.
2. Power up VCCA.
3. VCCB can be ramped up along with or after VCCA.
Table 1. Typical Total Static Power Consumption (ICCA + ICCB)
VCCB
VCCA
0V
1.2 V
1.5 V
1.8 V
2.5 V
3.3 V
0V
0
<0.5
<0.5
<0.5
<0.5
<0.5
1.2 V
<0.5
<1
<1
<1
<1
1
1.5 V
<0.5
<1
<1
<1
<1
1
1.8 V
<0.5
<1
<1
<1
<1
<1
2.5 V
<0.5
1
<1
<1
<1
<1
3.3 V
<0.5
1
<1
<1
<1
<1
UNIT
mA
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TYPICAL CHARACTERISTICS
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.2 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
0
0
10
20
30
40
50
0
60
0
10
20
CL - pF
30
CL - pF
40
50
60
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.5 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 3.3 V
60
0
0
10
CL - pF
10
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20
30
CL - pF
40
50
60
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TYPICAL CHARACTERISTICS (continued)
6
6
5
5
4
4
tPHL - ns
tPLH - ns
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 1.8 V
3
2
3
2
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
1
VCCB = 1.8 V
1
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
0
0
10
20
30
40
50
VCCB = 3.3 V
0
60
0
10
20
CL - pF
30
CL - pF
40
50
60
40
50
60
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 2.5 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
60
0
0
10
CL - pF
20
30
CL - pF
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TYPICAL CHARACTERISTICS (continued)
TYPICAL PROPAGATION DELAY (A to B) vs LOAD CAPACITANCE,
TA = 25°C, VCCA = 3.3 V
6
6
VCCB = 1.2 V
VCCB = 1.2 V
VCCB = 1.5 V
VCCB = 1.5 V
VCCB = 1.8 V
5
VCCB = 1.8 V
5
VCCB = 2.5 V
VCCB = 2.5 V
VCCB = 3.3 V
VCCB = 3.3 V
4
tPHL - ns
tPLH - ns
4
3
3
2
2
1
1
0
0
10
20
30
40
50
60
0
0
10
CL - pF
12
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20
30
CL - pF
40
50
60
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SCES813 – JUNE 2010
PARAMETER MEASUREMENT INFORMATION
2 × VCCO
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCO
GND
RL
tw
LOAD CIRCUIT
VCCI
VCCI/2
Input
VCCO
CL
RL
VTP
1.2 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
15 pF
15 pF
15 pF
15 pF
15 pF
2 kΩ
2 kΩ
2 kΩ
2 kΩ
2 kΩ
0.1 V
0.1 V
0.15 V
0.15 V
0.3 V
VCCI/2
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VCCA
Output
Control
(low-level
enabling)
VCCA/2
VCCA/2
0V
tPLZ
tPZL
VCCI
Input
VCCI/2
VCCI/2
0V
tPLH
Output
tPHL
VOH
VCCO/2
VOL
VCCO/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCCO
Output
Waveform 1
S1 at 2 × VCCO
(see Note B)
VCCO/2
VOL + VTP
VOL
tPHZ
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCCO/2
VOH - VTP
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 Ω, dv/dt ≥ 1 V/ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. VCCI is the VCC associated with the input port.
I. VCCO is the VCC associated with the output port.
Figure 1. Load Circuit and Voltage Waveforms
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APPLICATION INFORMATION
Figure 2 is an example circuit of the SN74AVC2T45 used in a unidirectional logic level-shifting application.
VCC1
VCC2
VCC1
VCC2
1
8
2
7
3
6
4
5
VCC2
VCC1
SYSTEM-1
SYSTEM-2
PIN
NAME
FUNCTION
1
VCCA
VCC1
SYSTEM-1 supply voltage (1.2 V to 3.6 V)
DESCRIPTION
2
A1
OUT1
Output level depends on VCC1 voltage.
3
A2
OUT2
Output level depends on VCC1 voltage.
4
GND
GND
Device GND
5
DIR
DIR
The GND (low-level) determines B-port to A-port direction.
6
B2
IN2
Input threshold value depends on VCC2 voltage.
7
B1
IN1
Input threshold value depends on VCC2 voltage.
8
VCCB
VCC2
SYSTEM-2 supply voltage (1.2 V to 3.6 V)
Figure 2. Unidirectional Logic Level-Shifting Application
14
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APPLICATION INFORMATION
Figure 3 shows the SN74AVC2T45 used in a bidirectional logic level-shifting application. Since the
SN74AVC2T45 does not have an output-enable (OE) pin, the system designer should take precautions to avoid
bus contention between SYSTEM-1 and SYSTEM-2 when changing directions.
VCC1
VCC1
I/O-1
VCC2
VCC2
Pullup/Pulldown
or Bus Hold(1)
Pullup/Pulldown
or Bus Hold(1)
1
8
2
7
3
6
4
5
I/O-2
DIR CTRL
SYSTEM-1
SYSTEM-2
Following is a sequence that illustrates data transmission from SYSTEM-1 to SYSTEM-2 and then from
SYSTEM-2 to SYSTEM-1.
(1)
STATE
DIR CTRL
I/O-1
I/O-2
1
H
Out
In
DESCRIPTION
2
H
Hi-Z
Hi-Z
SYSTEM-2 is getting ready to send data to SYSTEM-1. I/O-1 and I/O-2 are
disabled.
The bus-line state depends on pullup or pulldown. (1)
3
L
Hi-Z
Hi-Z
DIR bit is flipped. I/O-1 and I/O-2 still are disabled.
The bus-line state depends on pullup or pulldown. (1)
4
L
In
Out
SYSTEM-2 data to SYSTEM-1
SYSTEM-1 data to SYSTEM-2
SYSTEM-1 and SYSTEM-2 must use the same conditions, i.e., both pullup or both pulldown.
Figure 3. Bidirectional Logic Level-Shifting Application
Enable Times
Calculate the enable times for the SN74AVC2T45 using the following formulas:
• tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A)
• tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A)
• tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B)
• tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B)
In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit is
switched until an output is expected. For example, if the SN74AVC2T45 initially is transmitting from A to B, then
the DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the B
port has been disabled, an input signal applied to it appears on the corresponding A port after the specified
propagation delay.
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
CAVC2T45TDCURQ1
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VSSOP
DCU
8
3000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-40 to 125
SBUI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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17-Aug-2015
OTHER QUALIFIED VERSIONS OF SN74AVC2T45-Q1 :
• Catalog: SN74AVC2T45
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CAVC2T45TDCURQ1
Package Package Pins
Type Drawing
VSSOP
DCU
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.25
B0
(mm)
K0
(mm)
P1
(mm)
3.35
1.05
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CAVC2T45TDCURQ1
VSSOP
DCU
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
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