Texas Instruments | OCTAL EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS | Datasheet | Texas Instruments OCTAL EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS Datasheet

Texas Instruments OCTAL EDGE TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS Datasheet
SN74LV374AT
www.ti.com
SCES632 – JUNE 2010
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Check for Samples: SN74LV374AT
FEATURES
1
•
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
RGY PACKAGE
(TOP VIEW)
1Q
1D
2D
2Q
3Q
3D
4D
4Q
VCC
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1
20
3
4
19 8Q
18 8D
17 7D
5
6
16 7Q
15 6Q
7
8
14 6D
13 5D
2
12 5Q
9
10
11
CLK
•
•
OE
•
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd of 4.9 ns at 5 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 5 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2.3 V
at VCC = 5 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
GND
•
•
•
•
DESCRIPTION
The SN74LV374AT is an octal edge-triggered D-type flip-flop. This device features 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. The device is particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)
inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN74LV374AT
SCES632 – JUNE 2010
www.ti.com
ORDERING INFORMATION
TA
PACKAGE
QFN – RGY
TOP-SIDE MARKING
SN74LV374ATRGYR
Tube of 25
SN74LV374ATDW
Reel of 2000
SN74LV374ATDWR
SOP – NS
Reel of 2000
SN74LV374ATNSR
74LV374AT
SSOP – DB
Reel of 2000
SN74LV374ATDBR
LV374AT
Tube of 70
SN74LV374ATPW
Reel of 2000
SN74LV374ATPWR
Tube of 250
SN74LV374ATPWT
SOIC – DW
–40°C to 125°C
ORDERABLE PART NUMBER
Reel of 1000
TSSOP – PW
VV374
LV374AT
LV374AT
FUNCTION TABLE
(EACH FLIP-FLOP)
INPUTS
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
L
X
Q0
H
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
CLK
1
11
C1
1D
3
1D
2
1Q
To Seven Other Channels
2
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SN74LV374AT
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SCES632 – JUNE 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
7
VO
Output voltage range (2)
–0.5
VCC + 0.5
IIK
Input clamp current
VI < 0 or VI > VCC
±20
mA
IOK
Output clamp current
VO < 0 or VO > VCC
±50
mA
IO
Continuous output current
VO = 0 to VCC
±35
mA
±70
mA
(3)
Continuous current through VCC or GND
Package thermal impedance
qJA
Tstg
(1)
(2)
(3)
(4)
(5)
DB package (4)
70
DW package (4)
58
NS package (4)
60
PW package (4)
83
RGY package (5)
37
Storage temperature range
–65
150
UNIT
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7
The package thermal impedance is calculated in accordance with JESD 51-5.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VCC = 4.5 V to 5.5 V
VI
Input voltage
MIN
MAX
4.5
5.5
2
UNIT
V
V
0.8
V
V
0
5.5
High or low state
0
VCC
3-state
0
5.5
VO
Output voltage
IOH
High-level output current
VCC = 4.5 V to 5.5 V
–16
IOL
Low-level output current
VCC = 4.5 V to 5.5 V
16
mA
Δt/Δv
Input transition rise or fall rate
VCC = 4.5 V to 5.5 V
20
ns/V
TA
Operating free-air temperature
125
°C
(1)
–40
V
mA
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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3
SN74LV374AT
SCES632 – JUNE 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
VOL
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
4.5
IOH = –50 mA
4.5 V
4.4
IOH = –16 mA
4.5 V
3.8
IOL = 50 mA
4.5 V
IOL = 16 mA
4.5 V
MAX
0
MIN
TA = –40°C
to 125°C
MAX
UNIT
MIN MAX
4.4
4.4
3.8
3.8
V
0.1
0.1
0.1
0.55
0.55
0.55
V
II
VI = 5.5 V or GND
0 to 5.5 V
±0.1
±1
±1
mA
IOZ
VO = VCC or GND
5.5 V
±0.25
±2.5
±2.5
mA
ICC
VI = VCC or GND,
IO = 0
5.5 V
2
20
20
mA
One input at 3.4 V,
Other inputs at VCC or GND
5.5 V
40
50
50
mA
0.5
5
5
mA
ΔICC
(1)
TEST CONDITIONS
(1)
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
0
4
pF
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
TIMING REQUIREMENTS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
LOAD
CAPACITANCE
TA = –40°C
to 85°C
TA = 25°C
MIN
MAX
MIN
TA = –40°C
to 125°C
MAX
MIN
UNIT
MAX
CL = 15 pF
90
80
70
CL = 50 pF
85
75
65
fclock
Clock frequency
MHz
tw
Pulse duration, CLK high or low
6.5
8.5
8.5
ns
tsu
Setup time, data before CLK↑
2.5
2.5
5
ns
th
Hold time, data after CLK↑
2.5
2.5
2.5
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
4
tpd
CLK
Q
LOAD
CAPACITANCE
TA = –40°C
to 85°C
TA = 25°C
MIN
MAX
MIN
UNIT
MIN
TYP
CL = 15 pF
90
140
80
70
CL = 50 pF
85
150
75
65
3
4.9
8.1
1
10.5
1
11
CL = 15 pF
MAX
TA = –40°C
to 125°C
MAX
MHz
ten
OE
Q
3.2
4.6
7.6
1
11.5
1
12
tdis
OE
Q
1.7
3.4
6.8
1
8
1
9
tpd
CLK
Q
4.2
5.9
10.1
1
11.5
1
13
ten
OE
Q
4.5
5.5
9.6
1
12.5
1
13
tdis
OE
Q
2.4
4
8.8
1
12
1
12.5
CL = 50 pF
ns
tsk(o)
1
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1
ns
1
SN74LV374AT
www.ti.com
SCES632 – JUNE 2010
NOISE CHARACTERISTICS (1)
VCC = 5 V, CL = 50 pF, TA = 25°C
TYP
MAX
VOL(P)
Quiet output, maximum dynamic VOL
PARAMETER
1.3
1.6
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.3
–1.65
V
VOH(V)
Quiet output, minimum dynamic VOH
4.6
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
MIN
UNIT
V
2
V
0.8
V
TYP
UNIT
42.5
pF
Characteristics are for surface-mount packages only.
OPERATING CHARACTERISTICS
VCC = 5 V, TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
Outputs enabled
CL = 50 pF,
f = 10 MHz
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5
SN74LV374AT
SCES632 – JUNE 2010
www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
S1
Open
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
Open
VCC
GND
VCC
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3V
1.5 V
Timing Input
0V
tw
3V
1.5 V
Input
1.5 V
th
tsu
3V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3V
1.5 V
Input
1.5 V
0V
tPHL
tPLH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
1.5 V
1.5 V
0V
tPLZ
tPZL
≈VCC
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
tPZH
tPLH
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
3V
Output
Control
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPHL and tPLH are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74LV374ATDWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV374AT
SN74LV374ATNSR
ACTIVE
SO
NS
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
74LV374AT
SN74LV374ATPWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV374AT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV374ATDWR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
DW
20
2000
330.0
24.4
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
10.8
13.3
2.7
12.0
24.0
Q1
SN74LV374ATNSR
SO
NS
20
2000
330.0
24.4
8.4
13.0
2.5
12.0
24.0
Q1
SN74LV374ATPWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
6-May-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV374ATDWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74LV374ATNSR
SO
NS
20
2000
367.0
367.0
45.0
SN74LV374ATPWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
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EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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