Texas Instruments | Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Inverted) | Datasheet | Texas Instruments Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Inverted) Datasheet

Texas Instruments Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Inverted) Datasheet
SN74AUP1T158
www.ti.com
SCES808 – APRIL 2010
LOW POWER, 1.8/2.5/3.3-V INPUT, 3.3-V CMOS OUTPUT, SINGLE 2-INPUT
SCHMITT-TRIGGER BUFFER MULTIPLEXER (INVERTED)
Check for Samples: SN74AUP1T158
FEATURES
1
•
•
•
•
•
•
•
•
Single-Supply Voltage Translator
Output Level Up to Supply VCC CMOS Level
– 1.8 V to 3.3 V (at VCC = 3.3 V)
– 2.5 V to 3.3 V (at VCC = 3.3 V)
– 1.8 V to 2.5 V (at VCC = 2.5 V)
– 3.3 V to 2.5 V (at VCC = 2.5 V
Schmitt-Trigger Inputs Reject Input Noise and
Provide Better Output Signal Integrity
Ioff Supports Partial Power Down (VCC = 0 V)
Very Low Static Power Consumption:
0.1 µA
Very Low Dynamic Power Consumption:
0.9 µA
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Pb-Free Packages Available: SC-70 (DCK)
2 x 2.1 x 0.65 mm (Height 1.1 mm)
•
•
More Gate Options Available at
www.ti.com/littlelogic
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
A
1
6
Y
GND
2
5
VCC
B
3
4
C
DESCRIPTION/ORDERING INFORMATION
The SN74AUP1T158 is a single 2-input multiplexer that selects data from two data inputs (A and B) under
control of a common data select input (C). The state of the common data select input determines the particular
register from which the data comes. The output (Y) presents the selected data in the inverted form.
AUP technology is the industry's lowest-power logic technology designed for use in extending battery-life in
operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V
VCC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external
controllers or processors.
Schmitt-trigger inputs (ΔVT = 210 mV between positive and negative input transitions) offer improved noise
immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger
inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile
applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of
the device. No damage occurs to the device under these conditions.
The SN74AUP1T158 is designed with optimized current-drive capability of 4 mA to reduce line reflections,
overshoot, and undershoot caused by high-drive outputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
SN74AUP1T158
SCES808 – APRIL 2010
www.ti.com
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–40°C to 85°C
(1)
(2)
(3)
SOT (SC-70) – DCK
ORDERABLE PART NUMBER
Reel of 3000
SN74AUP1T158DCKR
Reel of 250
SN74AUP1T158DCKT
TOP-SIDE MARKING (3)
6P_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
The actual top-side marking has one additional character that designates the wafer fab/assembly site.
VCC
C
A
A
Y
B
B
1
6
2
5
3
4
Y
C
GND
Figure 1. 2-to-1 Data Selector With Inverted Output
When C is L, Y = B
When C is H, Y = A
FUNCTION TABLE
INPUTS
(Lower Level Input)
INPUT
(Select)
OUTPUT
(VCC CMOS)
A
B
C
Y
X
L
L
H
X
H
L
L
L
X
H
H
H
X
H
L
Supply VCC = 2.3 V to 2.7 V (2.5 V)
INPUTS
VT+ max = VIH min
VT- min = VIL max
A
OUTPUT
CMOS
B
Y
VIH = 1.1 V
VOH = 1.85 V
VIL = 0.35 V
VOL = 0.45 V
Supply VCC = 3 V to 3.6 V (3.3 V)
INPUTS
VT+ max = VIH min
VT- min = VIL max
A
2
OUTPUT
CMOS
B
Y
VIH = 1.19 V
VOH = 2.55 V
VIL = 0.5 V
VOL = 0.45 V
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Product Folder Link(s): SN74AUP1T158
SN74AUP1T158
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SCES808 – APRIL 2010
LOGIC DIAGRAM (BUFFER MULTIPLEXER)
1
A
6
3
Y
B
C
4
Static-Power Consumption
(µA)
Dynamic-Power Consumption
(pF)
100%
3
80%
80%
2.5
60%
3.3-V
3.3-V
LVC
Logic†
40%
Voltage − V
100%
60%
40%
Logic†
20%
20%
AUP
0%
†
0%
AUP
Switching Characteristics
at 25 MHz†
3.5
2
1.5
1
Input
Output
0.5
0
−0.5
Single, dual, and triple gates
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 2. AUP – The Lowest-Power Family
Figure 3. Excellent Signal Integrity
3.3 V
3.3 V
VIH = 1.19 V
VIL = 0.5 V
VIH = 1.19 V
VIL = 0.5 V
1.8-V
System
3.3-V
System
2.5-V
System
3.3-V
System
2.5 V
2.5 V
VIH = 1.10 V
VIL = 0.35 V
1.8-V
System
VIH = 1.10 V
VIL = 0.35 V
2.5-V
System
3.3-V
System
2.5-V
System
Figure 4. Typical Design Examples
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SN74AUP1T158
SCES808 – APRIL 2010
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3.3 V
1.8-V
System
3.3-V
System
VOH min
VT+ max = VIH min = 1.19 V
VT− min = V IL max = 0.5 V
VOL max
Input Switching Waveform
Output Switching Waveform
Figure 5. Switching Thresholds for 1.8-V to 3.3-V Translation
4
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SN74AUP1T158
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SCES808 – APRIL 2010
ABSOLUTE MAXIMUM RATINGS (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Output voltage range in the high or low state
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
259
°C/W
150
°C
qJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
DCK package
–65
V
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
RECOMMENDED OPERATING CONDITIONS (1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
TA
Operating free-air temperature
(1)
MIN
MAX
2.3
3.6
V
0
3.6
V
VCC
V
0
VCC = 2.3 V
–3.1
VCC = 3 V
–4
VCC = 2.3 V
3.1
VCC = 3 V
4
–40
85
UNIT
mA
mA
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
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SCES808 – APRIL 2010
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ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = –40°C
to 85°C
TA = 25°C
VCC
MIN
TYP
UNIT
MAX
MIN
MAX
VT+
Positive-going input
threshold voltage
2.3 V to 2.7 V
0.6
1.1
0.6
1.1
3 V to 3.6 V
0.75
1.16
0.75
1.19
VT–
Negative-going
input threshold
voltage
2.3 V to 2.7 V
0.35
0.6
0.35
0.6
3 V to 3.6 V
0.5
0.85
0.5
0.85
ΔVT
Hysteresis
(VT+ – VT–)
2.3 V to 2.7 V
0.23
0.6
0.1
0.6
3 V to 3.6 V
0.25
0.56
0.15
0.56
IOH = –20 mA
2.3 V to 3.6 V
IOH = –2.3 mA
VOH
2.3 V
IOH = –3.1 mA
IOH = –2.7 mA
3V
IOH = –4 mA
IOL = 20 mA
1.9
1.85
2.72
2.67
2.6
2.55
3V
IOL = 4 mA
All inputs
1.97
2.3 V
IOL = 3.1 mA
IOL = 2.7 mA
II
VCC – 0.1
2.05
2.3 V to 3.6 V
IOL = 2.3 mA
VOL
VCC – 0.1
VI = 3.6 V or GND
V
V
V
V
0.1
0.1
0.31
0.33
0.44
0.45
0.31
0.33
V
0.44
0.45
0 V to 3.6 V
0.1
0.5
mA
0V
0.1
0.5
mA
Ioff
VI or VO = 0 V to 3.6 V
ΔIoff
VI or VO = 3.6 V
0 V to 0.2 V
0.2
0.5
mA
ICC
VI = 3.6 V or GND, IO = 0
2.3 V to 3.6 V
0.5
0.9
mA
One input at 0.3 V or 1.1 V,
Other inputs at 0 or VCC, IO = 0
2.3 V to 2.7 V
4
One input at 0.45 V or 1.2 V,
Other inputs at 0 or VCC, IO = 0
3 V to 3.6 V
12
ΔICC
mA
Ci
VI = VCC or GND
3.3 V
1.5
pF
Co
VO = VCC or GND
3.3 V
3
pF
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 6)
PARAMETER
tpd
6
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
5 pF
1.8
2.3
2.9
0.5
6.8
10 pF
2.3
2.8
3.4
1
7.9
15 pF
2.6
3.1
3.8
1
8.7
30 pF
3.8
4.4
5.1
1.5
10.8
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UNIT
ns
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1T158
SN74AUP1T158
www.ti.com
SCES808 – APRIL 2010
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 6)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
UNIT
MAX
5 pF
1.8
2.3
3.1
0.5
6
10 pF
2.2
2.8
3.5
1
7.1
15 pF
2.6
3.2
5.2
1
7.9
30 pF
3.7
4.4
5.2
1.5
10
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 6)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
UNIT
MIN
TYP
MAX
MIN
MAX
5 pF
2
2.7
3.5
0.5
5.5
10 pF
2.4
3.1
3.9
1
6.5
15 pF
2.8
3.5
4.3
1
7.4
30 pF
4
4.7
5.5
1.5
9.5
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 1.8 V ± 0.15 V (unless otherwise noted)
(see Figure 6)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
CL
A, B, or C
Y
UNIT
MIN
TYP
MAX
MIN
MAX
1.6
2
2.5
0.5
8
10 pF
2
2.4
2.9
1
8.5
15 pF
2.3
2.8
3.3
1
9.1
30 pF
3.4
3.9
4.4
1.5
9.8
5 pF
tpd
TA = –40°C
to 85°C
TA = 25°C
ns
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 2.5 V ± 0.2 V (unless otherwise noted)
(see Figure 6)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
5 pF
1.6
1.9
2.4
0.5
5.3
10 pF
2
2.3
2.7
1
6.1
15 pF
2.3
2.7
3.1
1
6.8
30 pF
3.4
3.8
4.2
1.5
8.5
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UNIT
ns
7
SN74AUP1T158
SCES808 – APRIL 2010
www.ti.com
SWITCHING CHARACTERISTICS
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, VI = 3.3 V ± 0.3 V (unless otherwise noted)
(see Figure 6)
PARAMETER
tpd
FROM
(INPUT)
A, B, or C
TO
(OUTPUT)
Y
CL
TA = –40°C
to 85°C
TA = 25°C
MIN
TYP
MAX
MIN
MAX
5 pF
1.6
2.1
2.7
0.5
4.7
10 pF
2
2.4
3
1
5.7
15 pF
2.3
2.7
3.3
1
6.2
30 pF
3.4
3.8
4.4
1.5
7.8
UNIT
ns
OPERATING CHARACTERISTICS
TA = 25°C
PARAMETER
Cpd
8
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
4
5
UNIT
pF
Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1T158
SN74AUP1T158
www.ti.com
SCES808 – APRIL 2010
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL
(see Note A)
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VI/2
VCC/2
5, 10, 15, 30 pF
VI/2
VCC/2
1 MΩ
CL
VMI
VMO
LOAD CIRCUIT
VI
VMI
Input
VMI
0V
tPHL
tPLH
VOH
VMO
Output
VMo
VOL
tPHL
tPLH
VOH
Output
VMo
VMo
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A.
B.
C.
D.
CL includes probe and jig capacitance.
All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns.
The outputs are measured one at a time, with one transition per measurement.
tPLH and tPHL are the same as tpd.
Figure 6. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74AUP1T158DCKR
ACTIVE
Package Type Package Pins Package
Drawing
Qty
SC70
DCK
6
3000
Eco Plan
Lead/Ball Finish
(2)
Green (RoHS
& no Sb/Br)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
CU NIPDAU
Level-1-260C-UNLIM
(4)
-40 to 85
(6P5 ~ 6PF)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AUP1T158DCKR
SC70
DCK
6
3000
178.0
9.2
2.4
2.4
1.22
4.0
8.0
Q3
SN74AUP1T158DCKR
SC70
DCK
6
3000
178.0
9.0
2.4
2.5
1.2
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
1-Jun-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1T158DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
SN74AUP1T158DCKR
SC70
DCK
6
3000
180.0
180.0
18.0
Pack Materials-Page 2
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