Texas Instruments | 16-Bit Transparent D-Type Latch With 3-State Outputs (Rev. H) | Datasheet | Texas Instruments 16-Bit Transparent D-Type Latch With 3-State Outputs (Rev. H) Datasheet

Texas Instruments 16-Bit Transparent D-Type Latch With 3-State Outputs (Rev. H) Datasheet
SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H – DECEMBER 1998 – REVISED SEPTEMBER 2008
16-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS
FEATURES
1
• Member of the Texas Instruments Widebus™
Family
• EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
• DOC™ (Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without Speed
Degradation
• Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of ±24 mA at
2.5-V VCC
2
•
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
Ioff Supports Partial-Power-Down Mode
Operation
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Package Options Include Plastic Thin Shrink
Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
•
•
•
•
DESCRIPTION
A Dynamic Output Control (DOC™) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows
typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At
the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a
high-drive standard-output device. For more information, refer to the TI application reports, AVC Logic Family
Technology and Applications, literature number SCEA006, and Dynamic Output Control (DOC™) Circuitry
Technology and Applications, literature number SCEA009.
3.2
TA = 25°C
Process = Nominal
- Output Voltage - V
2.8
2.4
VCC = 3.3 V
2.0
1.6
VCC = 2.5 V
1.2
OH
VCC = 1.8 V
0.8
V
VOL - Output Voltage - V
2.8
TA = 25°C
Process = Nominal
2.4
2.0
1.6
1.2
0.8
VCC = 3.3 V
0.4
0.4
0
17
34
51
68
85 102 119
IOL - Output Current - mA
136
153
170
VCC = 2.5 V
VCC = 1.8 V
-160 -144 -128 -112 -96 -80 -64 -48
IOH - Output Current - mA
-32
-16
0
Figure 1. Output Voltage vs Output Current
This 16-bit transparent D-type latch is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
The SN74AVC16373 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,
and working registers. This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable
(LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at
the levels set up at the D inputs.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, DOC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1998–2008, Texas Instruments Incorporated
SN74AVC16373
SCES156H – DECEMBER 1998 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
DESCRIPTION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines
without need for interface or pullup components. OE does not affect internal operations of the latch. Old data can
be retained or new data can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16373 is characterized for operation from –40°C to 85°C.
GQL/ZQL PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
DGG OR DGV PACKAGE
(TOP VIEW)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1
3
4
5
6
A
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS
(56-Ball GQL/ZQL Package) (1)
(1)
2
2
1
2
3
4
5
6
A
1DIR
NC
NC
NC
NC
1OE
B
1B2
1B1
GND
GND
1A1
1A2
C
1B4
1B3
VCCB
VCCA
1A3
1A4
D
1B6
1B5
GND
GND
1A5
1A6
E
1B8
1B7
1A7
1A8
F
2B1
2B2
2A2
2A1
G
2B3
2B4
GND
GND
2A4
2A3
H
2B5
2B6
VCCB
VCCA
2A6
2A5
J
2B7
2B8
GND
GND
2A8
2A7
K
2DIR
NC
NC
NC
NC
2OE
NC - No internal connection
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SN74AVC16373
www.ti.com ..................................................................................................................................... SCES156H – DECEMBER 1998 – REVISED SEPTEMBER 2008
FUNCTION TABLE
(EACH 8-BIT LATCH)
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
LOGIC SYMBOL(1)
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
(1)
1
1EN
48
C3
24
2EN
25
C4
47
3D
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
4D
13
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1LE
1D1
1
2OE
48
47
2LE
C1
1D
2
1Q1
24
25
C1
2D1
36
To Seven Other Channels
13
1D
2Q1
To Seven Other Channels
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Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
4.6
V
–0.5
4.6
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Tstg
(1)
(2)
(3)
(4)
4
Package thermal impedance (4)
DGG package
70
DGV package
58
GQL/ZQL package
42
Storage temperature range
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
The package thermal impedance is calculated in accordance with JESD 51.
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Recommended Operating Conditions (1)
VCC
Supply voltage
MIN
MAX
Operating
1.4
3.6
Data retention only
1.2
VCC = 1.2 V
VIH
High-level input voltage
0.65 × VCC
VCC = 1.65 V to 1.95 V
0.65 × VCC
VCC = 3 V to 3.6 V
Low-level input voltage
2
GND
VCC = 1.4 V to 1.6 V
0.35 × VCC
VCC = 1.65 V to 1.95 V
0.35 × VCC
VCC = 2.3 V to 2.7 V
Input voltage
VO
Output voltage
IOHS
Static high-level output current (2)
0.8
0
3.6
Active state
0
VCC
3-state
0
3.6
VCC = 1.4 V to 1.6 V
–2
VCC = 1.65 V to 1.95 V
–4
VCC = 2.3 V to 2.7 V
–8
VCC = 3 V to 3.6 V
Static low-level output current (2)
IOLS
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
(2)
V
V
mA
–12
VCC = 1.4 V to 1.6 V
2
VCC = 1.65 V to 1.95 V
4
VCC = 2.3 V to 2.7 V
8
VCC = 3 V to 3.6 V
Δt/Δv
V
0.7
VCC = 3 V to 3.6 V
VI
V
1.7
VCC = 1.2 V
VIL
V
VCC
VCC = 1.4 V to 1.6 V
VCC = 2.3 V to 2.7 V
UNIT
mA
12
VCC = 1.4 V to 3.6 V
–40
5
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH
vs IOH characteristics. Refer to the TI application reports, AVC Logic Family Technology and Applications, literature number SCEA066,
and Dynamic Output Control (DOC™) Circuitry Technology and Applications, literature number SCEA009.
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Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOHS = –100 µA
VOH
1.4 V to 3.6 V
MAX
UNIT
VCC – 0.2
IOHS = –2 mA,
VIH = 0.91 V
1.4 V
IOHS = –4 mA,
VIH = 1.07 V
1.65 V
1.2
IOHS = –8 mA,
VIH = 1.7 V
2.3 V
1.75
IOHS = –12 mA,
VIH = 2 V
3V
2.3
IOLS = 100 µA
VOL
MIN TYP (1)
VCC
1.05
V
1.4 V to 3.6 V
0.2
IOLS = 2 mA,
VIL = 0.49 V
1.4 V
0.4
IOLS = 4 mA,
VIL = 0.57 V
1.65 V
0.45
IOLS = 8 mA,
VIL = 0.7 V
2.3 V
0.55
IOLS = 12 mA,
VIL = 0.8 V
3V
0.7
V
II
VI = VCC or GND
3.6 V
±2.5
µA
Ioff
VI or VO = 3.6 V
0
±10
µA
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
3.6 V
40
µA
Control inputs
IO = 0
2.5 V
VI = VCC or GND
Ci
Co
(1)
Data inputs
VI = VCC or GND
Outputs
VO = VCC or GND
3
3.3 V
3
2.5 V
2.5
3.3 V
2.5
2.5 V
6.5
3.3 V
6.5
pF
pF
Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
VCC = 1.2 V
MIN
tw
Pulse duration, LE high
tsu
Setup time, data before LE↓
th
Hold time, data after LE↓
MAX
VCC = 1.5 V
± 0.1 V
MIN
MAX
VCC = 1.8 V
± 0.15 V
MIN
MAX
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
MAX
MIN
UNIT
MAX
2.2
2
1.8
ns
1.7
1.2
1.1
0.9
0.8
ns
2
1.1
1.1
1.1
1
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2 through Figure 5)
PARAMETER
tpd
6
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
TYP
MIN
MAX
5.8
1.2
7.2
1.4
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
6.8
1
5.7
0.8
3.3
0.7
2.8
8.3
1.1
6.6
0.8
4
0.7
3.2
UNIT
ns
ten
OE
Q
7.4
1.6
8.8
1.6
6.7
1.4
4.3
0.7
3.4
ns
tdis
OE
Q
8.4
2.5
9.4
2.3
7.8
1.3
4.2
1.2
3.9
ns
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www.ti.com ..................................................................................................................................... SCES156H – DECEMBER 1998 – REVISED SEPTEMBER 2008
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation
capacitance
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
40
43
47
20
22
24
f = 10 MHz
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UNIT
pF
7
SN74AVC16373
SCES156H – DECEMBER 1998 – REVISED SEPTEMBER 2008 ..................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION
VCC = 1.2 V AND 1.5 V ± 0.1 V
2 × VCC
S1
2 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 15 pF
(see Note A)
2 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VOL + 0.1 V
VOL
tPHZ
VOH
VCC/2
VOH − 0.1 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 2. Load Circuit and Voltage Waveforms
8
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PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × VCC
S1
1 kΩ
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
1 kΩ
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
VOL
VOL + 0.15 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
Output
Control
(low-level
enabling)
VCC
VCC/2
VCC/2
0V
tPLH
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VOH
VCC/2
tPLZ
VCC
VCC/2
tPZH
tPHL
VCC/2
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2
0V
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
VOL + 0.15 V
VOL
tPHZ
VCC/2
VOH
VOH − 0.15 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 4. Load Circuit and Voltage Waveforms
10
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PARAMETER MEASUREMENT INFORMATION
VCC = 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
GND
CL = 30 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
tw
LOAD CIRCUIT
VCC
VCC
Timing
Input
VCC/2
Input
VCC/2
0V
VCC/2
0V
tsu
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
VCC
VCC/2
0V
tPZL
VCC
Input
VCC/2
VCC/2
0V
tPLH
VCC/2
VCC/2
VCC
VCC/2
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOL + 0.3 V
VOL
tPZH
VOH
Output
tPLZ
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC/2
VOH − 0.3 V
VOH
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 5. Load Circuit and Voltage Waveforms
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Product Folder Link(s): SN74AVC16373
11
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AVC16373DGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AVC16373
SN74AVC16373DGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
CVA373
SN74AVC16373ZQLR
LIFEBUY
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
CVA373
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Jan-2020
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AVC16373DGGR
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
TSSOP
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
SN74AVC16373DGVR
TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
SN74AVC16373ZQLR
BGA MI
CROSTA
R JUNI
OR
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AVC16373DGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74AVC16373DGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74AVC16373ZQLR
BGA MICROSTAR
JUNIOR
ZQL
56
1000
350.0
350.0
43.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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