Texas Instruments | Octal Buffer/Driver With 3-State Outputs (Rev. A) | Datasheet | Texas Instruments Octal Buffer/Driver With 3-State Outputs (Rev. A) Datasheet

Texas Instruments Octal Buffer/Driver With 3-State Outputs (Rev. A) Datasheet
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
D Qualified for Automotive Applications
D ESD Protection Exceeds 1500 V Per
D
D
DW OR PW PACKAGE
(TOP VIEW)
MIL-STD-883, Method 3015; Exceeds 150 V
Using Machine Model (C = 200 pF, R = 0)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V VCC
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
description/ordering information
This octal buffer/driver is designed specifically to
improve the performance and density of 3-state
memory-address drivers, clock drivers, and
bus-oriented receivers and transmitters.
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
VCC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
The SN74AHC244 is organized as two 4-bit
buffers/line drivers with separate output-enable (OE)
inputs. When OE is low, the device passes data from
the A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION{
−40°C to 125°C
ORDERABLE
PART NUMBER
PACKAGE‡
TA
TOP-SIDE
MARKING
SOIC − DW
Tape and reel
SN74AHC244QDWRQ1
AHC244Q1
TSSOP − PW
Tape and reel
SN74AHC244QPWRQ1
AHC244Q1
† For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OE
A
OUTPUT
Y
L
H
H
L
L
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
Copyright  2008, Texas Instruments Incorporated
!"# $ %&'# "$ (&)*%"# +"#',
+&%#$ %! # $('%%"#$ (' #-' #'!$ '."$ $#&!'#$
$#"+"+ /""#0, +&%# (%'$$1 +'$ # '%'$$"*0 %*&+'
#'$#1 "** (""!'#'$,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
logic symbol†
1OE
1A1
1A2
1A3
1A4
1
19
EN
2OE
18
2
4
16
6
14
12
8
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
EN
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1A1
1A2
1A3
1A4
1
2OE
2
18
4
16
6
14
8
12
1Y1
2A1
1Y2
2A2
1Y3
2A3
1Y4
2A4
19
11
9
13
7
15
5
17
3
2Y1
2Y2
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
recommended operating conditions (see Note 3)
VCC
VIH
Supply voltage
VCC = 2 V
VCC = 3 V
High-level input voltage
VI
VO
IOH
MAX
2
5.5
2.1
0.9
Output voltage
0
5.5
V
0
VCC
−50
mA
VCC = 2 V
VCC = 3.3 V ± 0.3 V
∆t/∆v
Low-level output current
Input transition rise or fall rate
V
1.65
V
−4
VCC = 5 V ± 0.5 V
VCC = 2 V
IOL
V
0.5
Input voltage
High-level output current
V
3.85
VCC = 3 V
VCC = 5.5 V
Low-level input voltage
UNIT
1.5
VCC = 5.5 V
VCC = 2 V
VIL
MIN
−8
50
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
4
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
100
8
20
mA
mA
mA
ns/V
TA
Operating free-air temperature
−40
125
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50 mA
VCC
MIN
TA = 25°C
TYP
MAX
MIN
2V
1.9
2
1.9
3V
2.9
3
2.9
4.5 V
4.4
4.5
4.4
IOH = −4 mA
3V
2.58
IOH = −8 mA
4.5 V
3.94
VOH
IOL = 50 mA
MAX
V
2.48
3.8
2V
0.1
0.1
3V
0.1
0.1
4.5 V
0.1
0.1
IOL = 4 mA
3V
0.36
0.5
IOL = 8 mA
4.5 V
0.36
0.5
VOL
II
IOZ
VI = 5.5 V or GND
VO = VCC or GND,
ICC
Ci
VI = VCC or GND,
VI = VCC or GND
Co
VO = VCC or GND
VI (OE) = VIL or VIH
IO = 0
POST OFFICE BOX 655303
UNIT
V
0 V to 5.5 V
±0.1
±1
mA
5.5 V
±0.25
±2.5
mA
4
40
mA
5.5 V
5V
2
5V
3.5
• DALLAS, TEXAS 75265
10
pF
pF
3
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A
Y
CL = 15 pF
tPZH
tPZL
OE
Y
CL = 15 pF
tPHZ
tPLZ
OE
Y
CL = 15 pF
tPLH
tPHL
A
Y
CL = 50 pF
tPZH
tPZL
OE
Y
CL = 50 pF
tPHZ
tPLZ
OE
Y
CL = 50 pF
MIN
TA = 25°C
TYP
MAX
MIN
MAX
5.8
8.4
1
10
5.8
8.4
1
10
6.6
10.6
1
12.5
6.6
10.6
1
12.5
5
9.7
1
11
5
9.7
1
11
8.3
11.9
1
13.5
8.3
11.9
1
13.5
9.1
14.1
1
16
9.1
14.1
1
16
10.3
14
1
16
10.3
14
1
16
UNIT
ns
ns
ns
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
tPLH
tPHL
A
Y
CL = 15 pF
tPZH
tPZL
OE
Y
CL = 15 pF
tPHZ
tPLZ
OE
Y
CL = 15 pF
tPLH
tPHL
A
Y
CL = 50 pF
tPZH
tPZL
OE
Y
CL = 50 pF
tPHZ
tPLZ
OE
Y
CL = 50 pF
TA = 25°C
MIN
TYP
MAX
MIN
MAX
3.9
5.5
1
6.5
3.9
5.5
1
6.5
4.7
7.3
1
8.5
4.7
7.3
1
8.5
5
7.2
1
8.5
5
7.2
1
8.5
5.4
7.5
1
8.5
5.4
7.5
1
8.5
6.2
9.3
1
10.5
6.2
9.3
1
10.5
6.7
9.2
1
10.5
6.7
9.2
1
10.5
MIN
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4)
PARAMETER
VOL(P)
Quiet output, maximum dynamic VOL
0.5
V
VOL(V)
Quiet output, minimum dynamic VOL
−0.2
V
VOH(V)
Quiet output, minimum dynamic VOH
4.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
3.5
V
1.5
NOTE 4: Characteristics are for surface-mount packages only.
4
UNIT
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER
Cpd
TEST CONDITIONS
Power dissipation capacitance
No load,
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
f = 1 MHz
TYP
UNIT
8.6
pF
5
SCLS526A − AUGUST 2003 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
RL = 1 kΩ
From Output
Under Test
Test
Point
VCC
Open
S1
TEST
GND
CL
(see Note A)
CL
(see Note A)
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
Input
50% VCC
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VCC
50% VCC
Input
50% VCC
0V
tPLH
In-Phase
Output
tPHL
50% VCC
tPHL
Out-of-Phase
Output
VOH
50% VCC
VOL
VCC
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
0V
tPZL
50% VCC
tPLZ
≈VCC
50% VCC
tPZH
tPLH
VOH
50% VCC
VOL
50% VCC
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + 0.3 V
VOL
tPHZ
50% VCC
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN74AHC244QDWRQ1
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC244Q1
SN74AHC244QPWRG4Q1
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC244Q1
SN74AHC244QPWRQ1
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
AHC244Q1
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
OTHER QUALIFIED VERSIONS OF SN74AHC244-Q1 :
• Catalog: SN74AHC244
• Enhanced Product: SN74AHC244-EP
• Military: SN54AHC244
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74AHC244QDWRQ1
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74AHC244QPWRG4Q
1
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
SN74AHC244QPWRQ1
TSSOP
PW
20
2000
330.0
16.4
6.95
7.0
1.4
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
2-Oct-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AHC244QDWRQ1
SOIC
DW
20
2000
367.0
367.0
45.0
SN74AHC244QPWRG4Q1
TSSOP
PW
20
2000
367.0
367.0
38.0
SN74AHC244QPWRQ1
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
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