Texas Instruments | Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. C) | Datasheet | Texas Instruments Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. C) Datasheet

Texas Instruments Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset (Rev. C) Datasheet
SN74LVC2G74-Q1
www.ti.com ........................................................................................................................................................ SCES563C – MARCH 2004 – REVISED APRIL 2008
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
FEATURES
1
•
•
•
•
•
•
•
•
•
•
Qualified for Automotive Applications
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 6.9 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
CLK
D
Q
GND
1
8
VCC
2
7
3
6
4
5
PRE
CLR
Q
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION (1)
TA
–40°C to 125°C
(1)
(2)
(3)
PACKAGE (2)
VSSOP – DCU
Reel of 3000
ORDERABLE PART NUMBER
SN74LVC2G74QDCURQ1
TOP-SIDE MARKING (3)
C74_
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
SN74LVC2G74-Q1
SCES563C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com
FUNCTION TABLE
INPUTS
(1)
OUTPUTS
PRE
CLR
CLK
D
Q
Q
L
H
X
X
H
L
H
L
X
X
L
H
L
L
X
X
H (1)
H (1)
H
H
↑
H
H
L
H
H
↑
L
L
H
H
H
L
X
Q0
Q0
This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
PRE
CLK
7
1
C
C
C
5
Q
TG
C
C
C
C
D
2
TG
TG
TG
3
C
CLR
2
C
Q
C
6
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Product Folder Link(s): SN74LVC2G74-Q1
SN74LVC2G74-Q1
www.ti.com ........................................................................................................................................................ SCES563C – MARCH 2004 – REVISED APRIL 2008
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
Supply voltage range
VI
Input voltage range (2)
(2)
MIN
MAX
–0.5
6.5
–0.5
6.5
–0.5
6.5
–0.5
VCC + 0.5
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
IOK
Output clamp current
VO < 0
–50
IO
Continuous output current
±50
Continuous current through VCC or GND
θJA
Package thermal impedance
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
UNIT
V
mA
±100
(4)
–65
227
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G74-Q1
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SN74LVC2G74-Q1
SCES563C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com
Recommended Operating Conditions (1)
VCC
Supply voltage
Operating
Data retention only
High-level input voltage
MAX
1.65
5.5
1.5
VCC = 2.3 V to 2.7 V
1.7
VCC = 3 V to 3.6 V
0.7 × VCC
0.35 × VCC
VCC = 1.65 V to 1.95 V
Low-level input voltage
V
V
2
VCC = 4.5 V to 5.5 V
VIL
UNIT
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIH
MIN
VCC = 2.3 V to 2.7 V
0.7
VCC = 3 V to 3.6 V
0.8
V
0.3 × VCC
VCC = 4.5 V to 5.5 V
VI
Input voltage
0
5.5
V
VO
Output voltage
0
VCC
V
VCC = 1.65 V
–4
VCC = 2.3 V
IOH
High-level output current
–8
–16
VCC = 3 V
VCC = 4.5 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
IOL
Low-level output current
Δt/Δv
Input transition rise or fall rate
8
16
VCC = 3 V
(1)
4
mA
24
VCC = 4.5 V
24
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
20
VCC = 3.3 V ± 0.3 V
10
VCC = 5 V ± 0.5 V
TA
mA
–24
ns/V
5
Operating free-air temperature
-40
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Product Folder Link(s): SN74LVC2G74-Q1
SN74LVC2G74-Q1
www.ti.com ........................................................................................................................................................ SCES563C – MARCH 2004 – REVISED APRIL 2008
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 5.5 V
1.65 V
1.2
IOH = –8 mA
2.3 V
1.85
IOH = –16 mA
3V
2.4
3V
2.3
4.5 V
3.8
IOL = 100 µA
Data or
control inputs
0.1
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.3
IOL = 16 mA
3V
0.4
3V
0.55
4.5 V
0.55
VI or VO = 5.5 V
ICC
VI = 5.5 V or GND,
IO = 0
ΔICC
One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = VCC or GND
(1)
V
0 to 5.5 V
±5
µA
0
±10
µA
1.65 V to 5.5 V
10
µA
3 V to 5.5 V
500
µA
VI = 5.5 V or GND
Ioff
UNIT
V
1.65 V to 5.5 V
IOL = 24 mA
II
TYP (1) MAX
VCC – 0.1
IOH = –4 mA
IOH = –24 mA
VOL
MIN
3.3 V
5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
MIN MAX
fclock
MIN
MAX
80
tw
Pulse duration
tsu
Setup time before CLK↑
th
Hold time, data after CLK↑
VCC = 3.3 V
± 0.3 V
MIN
120
VCC = 5 V
± 0.5 V
MAX
UNIT
MIN MAX
120
140
CLK
6.2
3.5
3.5
3.3
PRE or CLR low
6.2
3.5
3.5
3.3
Data
3.5
2.3
1.9
1.7
PRE or CLR inactive
2.5
2
1.8
1.6
0
0.3
0.5
0.8
MHz
ns
ns
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tpd
VCC = 1.8 V
± 0.15 V
MIN
MAX
80
CLK
PRE or CLR
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
MIN
MIN
MIN MAX
MAX
120
MAX
120
140
MHz
Q
4.8
14.4
2.2
8.1
2.2
6.9
1.4
5.1
Q
6
16
3
9.7
2.6
7.2
1.6
5.4
4.4
14.9
2.3
9.5
1.7
7.9
1.6
6.1
Q or Q
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Product Folder Link(s): SN74LVC2G74-Q1
UNIT
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ns
5
SN74LVC2G74-Q1
SCES563C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
6
Power dissipation capacitance
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TEST CONDITIONS
f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
TYP
TYP
TYP
TYP
35
35
37
40
UNIT
pF
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G74-Q1
SN74LVC2G74-Q1
www.ti.com ........................................................................................................................................................ SCES563C – MARCH 2004 – REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
TEST
GND
CL
(see Note A)
S1
Open
VLOAD
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
RL
GND
LOAD CIRCUIT
INPUTS
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
VI
tr/tf
VCC
VCC
3V
VCC
£2 ns
£2 ns
£2.5 ns
£2.5 ns
VM
VLOAD
CL
RL
VD
VCC/2
VCC/2
1.5 V
VCC/2
2 × VCC
2 × VCC
6V
2 × VCC
30 pF
30 pF
50 pF
50 pF
1 kW
500 W
500 W
500 W
0.15 V
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tW
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VOH
VM
VOL
tPHL
VM
VM
0V
tPLZ
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VM
Output
VI
Output
Control
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
VOL + VD
VOL
tPHZ
VM
VOH – VD
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CLVC2G74QDCURG4Q1
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
SN74LVC2G74QDCURQ1
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
C74R
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC2G74-Q1 :
• Catalog: SN74LVC2G74
• Enhanced Product: SN74LVC2G74-EP
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74LVC2G74QDCURQ1 VSSOP
DCU
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.25
B0
(mm)
K0
(mm)
P1
(mm)
3.35
1.05
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVC2G74QDCURQ1
VSSOP
DCU
8
3000
202.0
201.0
28.0
Pack Materials-Page 2
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