Texas Instruments | 12 Bit Asynchronous Binary Counters | Datasheet | Texas Instruments 12 Bit Asynchronous Binary Counters Datasheet

Texas Instruments 12 Bit Asynchronous Binary Counters Datasheet
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
FEATURES
1
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly
– Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
2-V to 5.5-V VCC Operation
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
High On-Off Output-Voltage Ratio
Low Crosstalk Between Switches
Individual Switch Controls
Extremely Low Input Current
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
xxx
SN74LV4040A . . . PW PACKAGE
(TOP VIEW)
QL
QF
QE
QG
QD
QC
QB
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
QK
QJ
QH
QI
CLR
CLK
QA
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The SN74LV4040A device is a 12 bit asynchronous binary counter with the outputs of all stages available
externally. A high level at the clear (CLR) input asynchronously clears the counter and resets all outputs low. The
count is advanced on a high-to-low transition at the clock (CLK) input. Applications include time-delay circuits,
counter controls, and frequency-dividing circuits.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the devices when they are powered down.
ORDERING INFORMATION (1)
PACKAGE (2)
TA
–55°C to 125°C
(1)
(2)
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
SN74LV4040AMPWREP
TOP-SIDE MARKING
LW040A
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
FUNCTION TABLE
(each buffer)
INPUTS
FUNCTION
CLK
CLR
↑
L
No change
↓
L
Advance to next stage
X
H
All outputs L
LOGIC DIAGRAM (POSITIVE LOGIC)
11
CLR
R
CLK
10
R
T
R
T
9
T
R
T
R
T
2
4
QF
T
5
T
QI
QE
R
T
14
3
QD
R
12
QH
T
QC
R
13
QG
6
QB
R
T
R
T
7
QA
R
R
T
15
QJ
1
QK
QL
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–20
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
VO = 0 to VCC
±25
mA
–0.5 VCC + 0.5
V
Continuous current through VCC or GND
±50
mA
θJA
Package thermal impedance (4)
108
°C/W
Tstg
Storage temperature range
150
°C
(1)
(2)
(3)
(4)
2
–65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 5.5 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LV4040A-EP
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 2 V
VIH
High-level input voltage
MIN
MAX
2
5.5
Low-level input voltage
VI
Input voltage
VO
Output voltage
VCC = 2.3 to 2.7 V
VCC × 0.7
VCC = 3 V to 3.6 V
VCC × 0.7
VCC = 4.5 to 5.5 V
VCC × 0.7
VCC = 2.3 to 2.7 V
VCC × 0.3
VCC = 3 V to 3.6 V
VCC × 0.3
VCC × 0.3
5.5
V
0
VCC
V
–50
VCC = 2.3 to 2.7 V
–2
VCC = 3 V to 3.6 V
–6
VCC = 4.5 to 5.5 V
–12
VCC = 2 V
IOL
Δt/Δv
Input transition rise or fall rate
TA
(1)
mA
μA
50
VCC = 2.3 to 2.7 V
Low-level output current
V
0
VCC = 2 V
High-level output current
V
0.5
VCC = 4.5 to 5.5 V
IOH
V
1.5
VCC = 2 V
VIL
UNIT
2
VCC = 3 V to 3.6 V
6
VCC = 4.5 to 5.5 V
12
VCC = 2.3 to 2.7 V
200
VCC = 3 V to 3.6 V
100
VCC = 4.5 to 5.5 V
20
Operating free-air temperature
–55
mA
ns/V
°C
125
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VOH
TEST CONDITIONS
IOH = –2 mA
2.3 V
IOH = –6 mA
3V
2.48
4.5 V
3.8
TYP
MAX
2
V
2 V to 5.5 V
IOL = 2 mA
2.3 V
0.4
IOL = 6 mA
3V
0.44
4.5 V
0.55
VI = 5.5 V or GND
ICC
VI = VCC or GND, IO = 0
Ioff
VI or VO = 0 to 5.5 V
Ci
VI = VCC or GND
UNIT
VCC – 0.1
IOL = 50 μA
IOL = 12 mA
II
MIN
2 V to 5.5 V
IOH = –12 mA
VOL
VCC
IOH = –50 μA
0.1
V
0 to 5.5 V
±1
μA
5.5 V
20
μA
0
5
μA
3.3 V
1.9
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Product Folder Link(s): SN74LV4040A-EP
pF
3
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
Timing Requirements
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time
CLK high or low
MAX
MIN
7
7
CLR high
6.5
6.5
CLR inactive before CLK↓
6.5
6.5
MAX
UNIT
ns
ns
Timing Requirements
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time
MAX
MIN
CLK high or low
5
5
CLR high
5
5
CLR inactive before CLK↓
5
5
MAX
UNIT
ns
ns
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
tw
Pulse duration
tsu
Setup time
MAX
MIN
CLK high or low
5
5
CLR high
5
5
CLR inactive before CLK↓
5
5
MAX
UNIT
ns
ns
Switching Characteristics
over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
CL = 50 pF
TA = 25°C
MIN
40
TYP
MAX
95
MAX
35
1
28
10.5
24.1
1
28
1
CL = 50 pF
tPHL
CLR
Any Q
CL = 50 pF
11.7
24.5
Δtpd
Qn
Qn+1
CL = 50 pF
1.7
11.1
UNIT
MHz
24.1
QA
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MIN
10.5
CLK
tPHL
4
LOAD
CAPACITANCE
ns
28
ns
10.8
ns
Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LV4040A-EP
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
LOAD
CAPACITANCE
CL = 50 pF
TYP
55
130
MIN
MAX
MAX
50
UNIT
MHz
7.5
15.4
1
17.5
7.5
15.4
1
17.5
CL = 50 pF
9
16.3
1
18.5
ns
CL = 50 pF
1.2
5.4
6.6
ns
CLK
QA
CL = 50 pF
tPHL
CLR
Any Q
Δtpd
Qn
Qn+1
tPHL
TA = 25°C
MIN
ns
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
fmax
tPLH
LOAD
CAPACITANCE
CL = 50 pF
TA = 25°C
MIN
TYP
95
185
MAX
80
9.3
1
10.5
5.3
9.3
1
10.5
1
QA
CL = 50 pF
tPHL
CLR
Any Q
CL = 50 pF
6.8
10.6
Δtpd
Qn
Qn+1
CL = 50 pF
0.8
4.0
UNIT
MHz
5.3
CLK
tPHL
MIN
MAX
ns
12
ns
5.5
ns
Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
(1)
PARAMETER
MIN
TYP
MAX
UNIT
VOL(P)
Quiet output, maximum dynamic VOL
0.5
0.8
V
VOL(V)
Quiet output, minimum dynamic VOL
–0.5
–0.8
V
VIH(D)
High-level dynamic input voltage
VIL(D)
Low-level dynamic input voltage
(1)
2.31
V
0.99
V
Characteristics are for surface-mount packages only.
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 10 MHz
VCC
TYP
3.3 V
11.9
5V
13.1
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LV4040A-EP
UNIT
pF
5
SN74LV4040A-EP
12 BIT ASYNCHRONOUS BINARY COUNTERS
www.ti.com
SGDS030 – SEPTEMBER 2007
PARAMETER MEASUREMENT INFORMATION
VCC
Test
Point
From Output
Under Test
RL = 1 k W
From Output
Under Test
S1
Open
GND
CL
(see Note A)
CL
(see Note A)
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
VCC
50% VCC
Timing Input
tw
tsu
VCC
50% VCC
Input
50% VCC
0V
th
VCC
50% VCC
Data Input
50% VCC
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC
50% VCC
Input
50% VCC
0V
tPHL
tPLH
VOH
In-Phase
Output
50% VCC
Output
Waveform 1
S1 at VCC
(see Note B)
50% VCC
VOH
50% VCC
VOL
50% VCC
tPZL
tPLZ
»VCC
50% VCC
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
50% VCC
0V
tPZH
tPLH
tPHL
Out-of-Phase
Output
50% VCC
VOL
VCC
Output
Control
50% VCC
VOH - 0.3 V
VOH
»0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 1 Mhz, ZO = 50 W, tr £ 3 ns, tf £ 3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LV4040A-EP
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN74LV4040AMPWREP
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
LW040A
V62/07630-01XE
ACTIVE
TSSOP
PW
16
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
LW040A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4040A-EP :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: SN74LV4040A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LV4040AMPWREP
Package Package Pins
Type Drawing
TSSOP
PW
16
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
12.4
Pack Materials-Page 1
6.9
B0
(mm)
K0
(mm)
P1
(mm)
5.6
1.6
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LV4040AMPWREP
TSSOP
PW
16
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
SCALE 2.500
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
NOTE 3
4.55
8
9
B
0.30
0.19
0.1
C A B
16X
4.5
4.3
NOTE 4
1.2 MAX
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
1
16
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
1
16X (0.45)
16
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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