Texas Instruments | SN74LVTH32374 (Rev. D) | Datasheet | Texas Instruments SN74LVTH32374 (Rev. D) Datasheet

Texas Instruments SN74LVTH32374 (Rev. D) Datasheet
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
FEATURES
1
• Member of the Texas Instruments
Widebus+™ Family
• State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
• Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
• Ioff and Power-Up 3-State Support Hot Insertion
2
•
•
•
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input and Output Voltages With
3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Supports Unregulated Battery Operation Down
to 2.7 V
abc
GKE OR ZKE PACKAGE
(TOP VIEW)
TERMINAL ASSIGNMENTS
1
2
3
4
5
6
A
1Q2
1Q1
1OE
1CLK
1D1
1D2
A
B
1Q4
1Q3
GND
GND
1D3
1D4
B
C
1Q6
1Q5
1VCC
1VCC
1D5
1D6
D
1Q8
1Q7
GND
GND
1D7
1D8
E
2Q2
2Q1
GND
GND
2D1
2D2
F
2Q4
2Q3
1VCC
1VCC
2D3
2D4
G
2Q6
2Q5
GND
GND
2D5
2D6
H
2Q7
2Q8
2OE
2CLK
2D8
2D7
G
J
3Q2
3Q1
3OE
3CLK
3D1
3D2
H
K
3Q4
3Q3
GND
GND
3D3
3D4
J
L
3Q6
3Q5
2VCC
2VCC
3D5
3D6
K
M
3Q8
3Q7
GND
GND
3D7
3D8
L
N
4Q2
4Q1
GND
GND
4D1
4D2
P
4Q4
4Q3
2VCC
2VCC
4D3
4D4
R
4Q6
4Q5
GND
GND
4D5
4D6
T
4Q7
4Q8
4OE
4CLK
4D8
4D7
1
2
3
4
5
6
C
D
E
F
M
N
P
R
T
DESCRIPTION/ORDERING INFORMATION
The SN74LVTH32374 is a 32-bit edge-triggered D-type flip-flop designed for low-voltage (3.3-V) VCC operation,
but with the capability to provide a TTL interface to a 5-V system environment. This device is particularly suitable
for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
ORDERING INFORMATION
TA
–40°C to 85°C
(1)
(2)
PACKAGE
LFBGA – GKE
LFBGA – ZKE (Pb-free)
(1) (2)
Reel of 1000
ORDERABLE PART NUMBER
SN74LVTH32374GKER
SN74LVTH32374ZKER
TOP-SIDE MARKING
HV374
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2000–2007, Texas Instruments Incorporated
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
www.ti.com
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors
with the bus-hold circuitry is not recommended.
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
2
OE
CLK
D
OUTPUT
Q
L
↑
H
H
L
↑
L
L
L
H or L
X
Q0
H
X
X
Z
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVTH32374
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1CLK
A3
2OE
A4
2CLK
C1
1D1
A5
A2
1D
H3
H4
C1
1Q1
2D1
E5
To Seven Other Channels
3OE
3CLK
4OE
J4
4CLK
C1
3D1
2Q1
To Seven Other Channels
J3
J5
E2
1D
J2
1D
T3
T4
C1
3Q1
4D1
N5
N2
1D
To Seven Other Channels
4Q1
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
(2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off state
VO
Voltage range applied to any output int he high state (2)
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
IIK
Input clamp current
VI < 0
IOK
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (4)
GKE/ZKE package
40
°C/W
Tstg
Storage temperature range
150
°C
(1)
(2)
(3)
(4)
–65
V
128
mA
64
mA
–50
mA
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVTH32374
3
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
Recommended Operating Conditions (1)
MIN
MAX
2.7
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
5.5
V
IOH
High-level output current
–32
mA
IOL
Low-level output current
64
mA
Δt/Δv
Input transition rise or fall rate
Δt/ΔVCC
Power-up ramp rate
200
TA
Operating free-air temperature
–40
(1)
4
2
V
0.8
Outputs enabled
V
10
V
ns/V
μs/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVTH32374
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
VCC = 2.7 V,
II = –18 mA
VCC = 2.7 V to 3.6 V,
IOH = –100 μA
VCC = 2.7 V,
IOH = –8 mA
VCC = 3 V,
IOH = –32 mA
VCC = 2.7 V
VOL
VCC = 3 V
Control inputs
II
Data inputs
Ioff
TYP (1)
MAX
UNIT
–1.2
V
VCC – 0.2
2.4
V
2
IOL = 100 μA
0.2
IOL = 24 mA
0.5
IOL = 16 mA
0.4
IOL = 32 mA
0.5
IOL = 64 mA
0.55
VCC = 3.6 V,
VI = 5.5 V
10
VCC = 3.6 V,
VI = VCC or GND
±1
VCC = 0 or 3.6 V
VCC = 0,
1
VI = 0
μA
μA
75
VI = 2 V
(2)
V
–5
±100
VI = 0.8 V
Data inputs
VCC = 3.6 V,
VI = VCC
VI or VO = 0 to 4.5 V
VCC = 3 V
II(hold)
MIN
–75
500
VI = 0 to 3.6 V
μA
–750
5
μA
–5
μA
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V, OE = don't care
±100
μA
IOZPD
VCC = 1.5 V to 0 V, VO = 0.5 V to 3 V, OE = don't care
±100
μA
ICC
VCC = 3.6 V, IO = 0,
VI = VCC or GND
IOZH
VCC = 3.6 V,
VO = 3 V
IOZL
VCC = 3.6 V,
VO = 0.5 V
IOZPU
Outputs high
0.38
Outputs low
10
Outputs disabled
mA
0.38
ΔICC (3)
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
Ci
VI = 3 V or 0
4
pF
Co
VO = 3 V or 0
9
pF
(1)
(2)
(3)
0.2
mA
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
MIN
MAX
VCC = 2.7 V
MIN
160
UNIT
MAX
fclock
Clock frequency
160
tw
Pulse duration, CLK high or low
3
3
ns
tsu
Setup time, data before CLK↑
High or low
1.8
2
ns
th
Hold time, data after CLK↑
High or low
0.8
0.1
ns
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Product Folder Link(s): SN74LVTH32374
MHz
5
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
VCC = 3.3 V
± 0.3 V
MIN
VCC = 2.7 V
TYP (1)
MAX
MIN
UNIT
MAX
fmax
160
1.9
3
4.5
5.2
2.1
2.9
4
4.2
1.5
2.8
4.5
5.4
1.5
2.8
4.4
5
2.4
3.5
5
5.4
2
3.2
4.6
4.8
tPZH
tPZL
tPHZ
tPLZ
6
TO
(OUTPUT)
tPLH
tPHL
(1)
FROM
(INPUT)
A
Q
OE
Q
OE
Q
160
tsk(LH)
0.5
tsk(HL)
0.5
MHz
ns
ns
ns
ns
All typical values are at VCC = 3.3 V, TA = 25°C.
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVTH32374
SN74LVTH32374
3.3-V ABT 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
www.ti.com
SCBS752D – SEPTEMBER 2000 – REVISED AUGUST 2007
PARAMETER MEASUREMENT INFORMATION
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
Timing Input
LOAD CIRCUIT
1.5 V
0V
tw
tsu
2.7 V
Input
1.5 V
1.5 V
th
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
1.5 V
VOL
tPHL
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
1.5 V
0V
tPZL
tPLZ
3V
1.5 V
tPZH
VOH
Output
Output
Waveform 1
S1 at 6 V
(see Note B)
tPLH
1.5 V
2.7 V
Output
Control
VOL + 0.3 V
VOL
tPHZ
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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Copyright © 2000–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVTH32374
7
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74LVTH32374ZKER
NRND
Package Type Package Pins Package
Drawing
Qty
LFBGA
ZKE
96
1000
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
-40 to 85
HV374
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVTH32374 :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
• Enhanced Product: SN74LVTH32374-EP
NOTE: Qualified Version Definitions:
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LVTH32374ZKER
Package Package Pins
Type Drawing
LFBGA
ZKE
96
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.7
B0
(mm)
K0
(mm)
P1
(mm)
13.7
2.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Aug-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVTH32374ZKER
LFBGA
ZKE
96
1000
336.6
336.6
41.3
Pack Materials-Page 2
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