Texas Instruments | Low-Power Ultra-Configurable Multiple-Function Gate With 3-State Outputs (Rev. C) | Datasheet | Texas Instruments Low-Power Ultra-Configurable Multiple-Function Gate With 3-State Outputs (Rev. C) Datasheet

Texas Instruments Low-Power Ultra-Configurable Multiple-Function Gate With 3-State Outputs (Rev. C) Datasheet
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FEATURES
1
• Available in the Texas Instruments
NanoFree™ Package
• Low Static-Power Consumption
(ICC = 0.9 µA Max)
• Low Dynamic-Power Consumption
(Cpd = 5 pF Typ at 3.3 V)
• Low Input Capacitance (CI = 1.5 pF)
• Low Noise – Overshoot and Undershoot
<10% of VCC
• Input-Disable Feature Allows Floating Input
Conditions
• Ioff Supports Partial-Power-Down Mode
Operation
• Includes Schmitt-Trigger Inputs
•
•
•
2
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
tpd = 7.4 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
•
•
•
•
DCT PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
DCU PACKAGE
(TOP VIEW)
OE
1
8
VCC
A
2
7
Y
B
3
6
D
GND
4
5
C
OE
A
B
GND
1
2
3
8
7
6
4
5
GND
B
A
OE
VCC
Y
D
C
4 5
3 6
2 7
1 8
C
D
Y
VCC
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
xxxxxx
80%
80%
60%
60%
40%
3.3-V
Logic†
40%
3.3-V
LVC
Logic†
AUP
0%
3.5
3
2.5
Input
2
1.5
1
Output
0.5
20%
20%
0%
Switching Characteristics
at 25 MHz†
Dynamic-Power Consumption
(pF)
100%
Voltage − V
Static-Power Consumption
(µA)
100%
AUP
† Single, dual, and triple gates
Figure 1. AUP - The Lowest-Power Family
0
−0.5
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Figure 2. Excellent Signal Integrity
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
DESCRIPTION/ORDERING INFORMATION
The SN74AUP1G99 features configurable multiple functions with a 3-state output. This device has the
input-disable feature, which allows floating input signals. The inputs and output are disabled when the
output-enable (OE) input is high. When OE is low, the output state is determined by 16 patterns of 4-bit input.
The user can choose the logic functions, such as MUX, AND, OR, NAND, NOR, XOR, XNOR, inverter, and
buffer. All inputs can be connected to VCC or GND.
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching noise immunity at the input.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
PACKAGE (1) (2)
TA
–40°C to 85°C
(1)
(2)
(3)
2
ORDERABLE PART NUMBER
TOP-SIDE MARKING (3)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
Tape and reel
SN74AUP1G99YZPR
_ _ HY_
SSOP – DCT
Tape and reel
SN74AUP1G99DCTR
H99_ _ _
VSSOP – DCU
Tape and reel
SN74AUP1G99DCUR
H99_
Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION TABLE
INPUTS
(1)
OE
D
C
B
A
OUTPUT
Y
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
H
L
L
L
L
L
H
H
H
L
L
H
L
L
L
L
L
H
L
H
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
L
L
L
H
L
H
L
L
H
L
L
H
L
H
L
H
L
H
L
H
H
L
L
H
H
L
L
H
L
H
H
L
H
H
L
H
H
H
L
L
L
H
H
H
H
L
H
X (1)
X (1)
X (1)
X (1)
Z
Floating inputs allowed.
LOGIC DIAGRAM (POSITIVE LOGIC)
OE
A
B
1
2
3
7
C
D
5
Y
6
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
FUNCTION SELECTION TABLE
PRIMARY FUNCTION
COMPLEMENTARY FUNCTION
PAGE
3-state buffer
4
3-state inverter
4
3-state 2-to-1 data selector MUX
5
3-state 2-to-1 data selector MUX, inverted out
5
3-state 2-input AND
3-state 2-input NOR, both inputs inverted
5
3-state 2-input AND, 1 input inverted
3-state 2-input NOR, 1 input inverted
5
3-state 2-input AND, both inputs inverted
3-state 2-input NOR
5
3-state 2-input NAND
3-state 2-input OR, both inputs inverted
6
3-state 2-input NAND, 1 input inverted
3-state 2-input OR, 1 input inverted
6
3-state 2-input NAND, both inputs inverted
3-state 2-input OR
6
3-state 2-input XOR
6
3-state 2-input XNOR
3-state 2-input XOR, 1 input inverted
7
3-STATE BUFFER FUNCTIONS AVAILABLE
INPUT
FUNCTION
3-state buffer
OE
L
Y
A
B
C
D
Input
X
L
L
X
Input
H
L
L
H
Input
L
H
L
Input
H
H
X
L
Input
X
L
H
Input
L
L
X
Input
3-STATE INVERTER FUNCTIONS AVAILABLE
INPUT
FUNCTION
3-state inverter
4
OE
L
Y
A
B
C
D
Input
X
L
H
X
Input
H
H
L
H
Input
H
H
L
Input
L
H
X
L
Input
X
H
H
Input
H
H
X
Input
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
3-STATE MUX FUNCTIONS AVAILABLE
A/B
A/B
Input 1
Input 1
Y
Input 2
Y
Input 2
FUNCTION
OE
A
B
C
D
3-state 2-to-1, data selector MUX
Input 1
Input 2
Input 1 or Input 2
L
3-state 2-to-1, data selector MUX
Input 2
Input 1
Input 2 or Input 1
L
Input 1
Input 2
Input 1 or Input 2
H
Input 2
Input 1
Input 2 or Input 1
H
L
3-state 2-to-1, data selector MUX, inverted out
3-state 2-to-1, data selector MUX, inverted out
3-STATE AND/NOR FUNCTIONS AVAILABLE
Input 1
Input 1
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND
3-state NOR, both inputs inverted
2
3-state AND
3-state NOR, both inputs inverted
Input 1
Y
Input 2
Y
Input 2
OE
L
Input 1
A
B
C
D
L
Input 1
Input 2
L
L
Input 2
Input 1
L
D
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND, with A inverted
3-state NOR, with B inverted
2
3-state AND, with A inverted
3-state NOR, with B inverted
Input 1
OE
L
Input 1
Y
Input 2
A
B
C
Input 2
L
Input 1
L
H
Input 1
Input 2
H
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND, with B inverted
3-state NOR, with A inverted
2
3-state AND, with B inverted
3-state NOR, with A inverted
Input 1
OE
L
Input 1
Y
Input 2
A
B
C
D
Input 1
L
Input 2
L
H
Input 2
Input 1
H
A
B
C
D
Input 1
H
Input 2
H
Input 2
H
Input 1
H
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state AND, both inverted inputs
3-state NOR
2
3-state AND, both inverted inputs
3-state NOR
OE
L
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
3-STATE NAND/OR FUNCTIONS AVAILABLE
Input 1
Input 1
Y
Input 2
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state NAND
3-state OR, with both inputs inverted
2
3-state NAND
3-state OR, with both inputs inverted
Input 1
OE
L
Input 1
Y
Input 2
A
B
C
D
L
Input 1
Input 2
H
L
Input 2
Input 1
H
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state NAND, with A inverted
3-state OR, with B inverted
2
3-state NAND, with A inverted
3-state OR, with B inverted
Input 1
OE
L
A
B
C
D
Input 2
L
Input 1
H
H
Input 1
Input 2
L
Input 1
Y
Input 2
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state NAND, with B inverted
3-state OR, with A inverted
2
3-state NAND, with B inverted
3-state OR, with A inverted
Input 1
OE
L
A
B
C
D
Input 1
L
Input 2
H
H
Input 2
Input 1
L
Input 1
Y
Input 2
Y
Input 2
NO. OF INPUTS
AND/NAND FUNCTION
OR/NOR FUNCTION
2
3-state NAND, with both inputs inverted
3-state OR
2
3-state NAND, with both inputs inverted
3-state OR
OE
L
A
B
C
D
Input 1
H
Input 2
L
Input 2
H
Input 1
L
3-STATE XOR/XNOR FUNCTIONS AVAILABLE
Input 1
Y
Input 2
FUNCTION
3-state XOR
6
OE
L
A
B
C
D
Input 1
X
L
Input 2
Input 2
X
L
Input 1
X
Input 1
H
Input 2
X
Input 2
H
Input 1
L
H
Input 1
Input 2
L
H
Input 2
Input 1
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Product Folder Link(s): SN74AUP1G99
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
3-STATE XOR/XNOR FUNCTIONS AVAILABLE (continued)
Input 1
Y
Input 2
FUNCTION
OE
A
B
C
D
3-state XOR, with A inverted
L
H
L
Input 1
Input 2
Input 1
Y
Input 2
FUNCTION
OE
A
B
C
D
3-state XOR, with B inverted
L
H
L
Input 1
Input 2
Input 1
Y
Input 2
FUNCTION
3-state XNOR
3-state XNOR
OE
L
A
B
C
D
H
L
Input 1
Input 2
H
L
Input 2
Input 1
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
UNIT
V
(2)
VI
Input voltage range
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5 VCC + 0.5
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
±50
mA
θJA
Tstg
(1)
(2)
(3)
Package thermal impedance (3)
DCT package
220
DCU package
227
YZP package
102
Storage temperature range
–65
150
V
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Recommended Operating Conditions (1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
MIN
MAX
0.8
3.6
V
0
3.6
V
Active state
0
VCC
3-state
0
3.6
VCC = 0.8 V
–20
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
VCC = 3 V
IOL
Low-level output current
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
8
V
µA
mA
–4
VCC = 0.8 V
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
VCC = 3 V
Δt/Δv
UNIT
µA
mA
4
VCC = 0.8 V to 3.6 V
–40
200
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
ΔVT
Hysteresis
(VT+ – VT–)
0.6
0.3
0.6
0.3
1.1 V
0.53
0.9
0.53
0.9
1.4 V
0.74
1.11
0.74
1.11
1.65 V
0.91
1.29
0.91
1.29
2.3 V
1.37
1.77
1.37
1.77
3V
1.88
2.29
1.88
2.29
0.8 V
0.1
0.6
0.1
0.6
1.1 V
0.26
0.65
0.26
0.65
1.4 V
0.39
0.75
0.39
0.75
1.65 V
0.47
0.84
0.47
0.84
2.3 V
0.69
1.04
0.69
1.04
3V
0.88
1.24
0.88
1.24
0.8 V
0.07
0.5
0.07
0.5
1.1 V
0.08
0.46
0.08
0.46
1.4 V
0.18
0.56
0.18
0.56
1.65 V
0.27
0.66
0.27
0.66
2.3 V
0.53
0.92
0.53
0.92
0.79
1.31
0.79
1.31
VCC – 0.1
IOH = –1.1 mA
1.1 V
0.75 × VCC
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.11
1.03
IOH = –1.9 mA
1.65 V
1.32
1.3
2.05
1.97
1.9
1.85
2.72
2.67
IOH = –4 mA
2.3 V
3V
IOL = 20 µA
0.8 V to 3.6 V
IOL = 1.1 mA
IOL = 1.7 mA
IOL = 1.9 mA
IOL = 2.3 mA
IOL = 3.1 mA
IOL = 2.7 mA
IOL = 4 mA
II
MAX
VCC – 0.1
IOH = –2.7 mA
VI = GND to 3.6 V
UNIT
MIN
0.8 V to 3.6 V
IOH = –3.1 mA
All
inputs
MAX
IOH = –20 µA
IOH = –2.3 mA
VOL
TYP
0.8 V
3V
VOH
TA = –40°C
to 85°C
TA = 25°C
2.6
V
V
V
V
2.55
0.1
0.1
1.1 V
0.3 × VCC
0.3 × VCC
1.4 V
0.31
0.37
1.65 V
0.31
0.35
0.31
0.33
0.44
0.45
0.31
0.33
0.44
0.45
0 V to 3.6 V
0.1
0.5
µA
2.3 V
3V
V
Ioff
VI or VO = 0 V to 3.6 V
0V
0.2
0.6
µA
ΔIoff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
0.2
0.6
µA
IOZ
VO = VCC or GND
3.6 V
0.1
0.5
µA
ICC
VI = GND or (VCC to 3.6 V),
OE = GND, IO = 0
0.8 V to 3.6 V
0.5
0.9
µA
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LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
Data
inputs
ΔICC
VI = VCC – 0.6 V, (1) IO = 0
MAX
MIN
VI = GND to 3.6 V, OE = VCC (2)
VI = VCC or GND
Co
VO = VCC or GND
UNIT
MAX
40
50
110
CI
(1)
(2)
TYP
3.3 V
OE
All
inputs
TA = –40°C
to 85°C
TA = 25°C
VCC
0.8 V to 3.6 V
µA
120
0
0V
1.5
3.6 V
1.5
3.6 V
3
nA
pF
pF
One input at VCC – 0.6 V, other input at VCC or GND
To show ICC is very low when the input-disable feature is enabled.
Switching Characteristics
over recommended operating free-air temperature range, CL = 5 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
1.2 V ± 0.1 V
0.5
1.5 V ± 0.1 V
A, B, C, or D
Y
MIN
MAX
9.9
20.1
0.5
26.6
1.4
6.6
11.9
0.5
16.8
1.8 V ± 0.15 V
1.8
5.3
8.9
1
13
2.5 V ± 0.2 V
2.1
3.9
5.8
1.3
8.9
3.3 V ± 0.3 V
1.9
3.3
4.8
1.2
7.4
32
0.8 V
ten
OE
Y
10
OE
Y
1.2 V ± 0.1 V
0.6
11.1
21.7
0.5
25.2
1.5 V ± 0.1 V
2.3
7.4
12.6
1.4
16.4
1.8 V ± 0.15 V
2
5.7
9.4
1.1
12.8
2.5 V ± 0.2 V
2.1
4.1
6.2
1.2
8.5
3.3 V ± 0.3 V
1.9
3.4
5
1.1
6.7
8.2
ns
9.8
1.2 V ± 0.1 V
1.4
4.5
7.7
1.5
1.5 V ± 0.1 V
1.7
3.2
4.8
1.7
6
1.8 V ± 0.15 V
1.5
3
4.7
1.3
6.1
2.5 V ± 0.2 V
0.9
1.9
3
0.7
4.2
3.3 V ± 0.3 V
0.8
2.5
4.4
0.7
4.5
Submit Documentation Feedback
ns
35
0.8 V
tdis
UNIT
MAX
0.8 V
tpd
TA = –40°C
to 85°C
TA = 25°C
VCC
ns
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 10 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
MAX
MIN
MAX
1.2 V ± 0.1 V
0.4
10.7
1.5 V ± 0.1 V
21.1
0.7
29.8
2
7.2
12.6
1.1
18.5
1.8 V ± 0.15 V
2.3
5.8
9.5
1.5
14.5
2.5 V ± 0.2 V
2.5
4.4
6.3
1.7
10.5
3.3 V ± 0.3 V
2.3
3.7
5.2
1.5
8.4
0.8 V
tpd
A, B, C, or D
Y
OE
Y
OE
Y
1.2 V ± 0.1 V
1.4
12.1
22.8
0.8
29.3
1.5 V ± 0.1 V
2.8
8
13.3
2
18.7
1.8 V ± 0.15 V
2.5
6.2
10
1.6
14.8
2.5 V ± 0.2 V
2.5
4.5
6.7
1.6
9.9
3.3 V ± 0.3 V
2.3
3.8
5.4
1.5
8.2
2
5.6
9.3
2
10
1.5 V ± 0.1 V
2.5
4.1
5.8
2.4
7.6
1.8 V ± 0.15 V
2.9
4.2
5.7
2.7
7.9
2.5 V ± 0.2 V
1.1
2.7
4.4
1.1
5.5
3.3 V ± 0.3 V
1.9
3.5
5.2
1.9
5.8
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Product Folder Link(s): SN74AUP1G99
ns
0
1.2 V ± 0.1 V
Copyright © 2004–2007, Texas Instruments Incorporated
ns
0
0.8 V
tdis
UNIT
36
0.8 V
ten
TA = –40°C
to 85°C
TA = 25°C
VCC
ns
11
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP
1.2 V ± 0.1 V
0.9
1.5 V ± 0.1 V
A, B, C, or D
Y
MIN
MAX
11.4
22
0.5
30.8
2.5
7.8
13.2
1.6
19.2
1.8 V ± 0.15 V
2.7
6.3
10
1.9
15.1
2.5 V ± 0.2 V
2.8
4.7
6.6
2
10.8
3.3 V ± 0.3 V
2.6
4
5.5
1.8
8.8
38
0.8 V
ten
OE
Y
12
OE
Y
1.2 V ± 0.1 V
1.8
13
24.2
1.3
30.6
1.5 V ± 0.1 V
3.2
8.6
14.1
2.4
19.5
1.8 V ± 0.15 V
2.9
6.7
10.6
2
15.4
2.5 V ± 0.2 V
2.8
4.9
7
1.9
10.3
3.3 V ± 0.3 V
2.6
4.1
5.7
1.8
8.6
10.7
ns
13
1.2 V ± 0.1 V
2.7
6.3
9.9
2.8
1.5 ± 0.1 V
3.2
4.6
6.1
3.1
8
1.8 V ± 0.15 V
3.2
4.8
6.6
3
8.8
2.5 V ± 0.2 V
2.2
3.4
4.7
2
6
3.3 V ± 0.3 V
2.4
4.4
6.5
2.3
7.2
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ns
44
0.8 V
tdis
UNIT
MAX
0.8 V
tpd
TA = –40°C
to 85°C
TA = 25°C
VCC
ns
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
0.8 V
tpd
A, B, C, or D
Y
OE
Y
OE
Y
MAX
MIN
MAX
UNIT
48
3.1
14
24.9
2.6
36.1
1.5 V ± 0.1 V
4.2
9.6
15.1
3.3
23.1
1.8 V ± 0.15 V
4.1
7.9
11.7
3.3
18
2.5 V ± 0.2 V
4.1
5.9
7.9
3.1
12.7
3.3 V ± 0.3 V
3.7
5.1
6.7
2.8
10.4
ns
50
1.2 V ± 0.1 V
4.4
16
27.6
3.9
36.8
1.5 V ± 0.1 V
5.3
10.7
16.2
4.3
23.6
1.8 V ± 0.15 V
4.6
8.5
12.4
3.6
18.6
2.5 V ± 0.2 V
4.2
6.3
8.5
3.2
12.6
3.3 V ± 0.3 V
3.8
5.4
7.1
2.9
10.2
0.8 V
tdis
TYP
1.2 V ± 0.1 V
0.8 V
ten
TA = –40°C
to 85°C
TA - 25°C
VCC
ns
19
1.2 V ± 0.1 V
6
10.1
14.2
6
14.6
1.5 V ± 0.1 V
5.1
7.4
10.6
5
10.1
1.8 V ± 0.15 V
5.5
8.6
11.6
5.5
12.1
2.5 V ± 0.2 V
3.3
5.9
8.3
3.3
8.9
3.3 V ± 0.3 V
6
8.7
10.9
5.9
11.8
ns
Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
Outputs enabled
Cpd
Power dissipation capacitance
f = 10 MHz
Outputs disabled
VCC
TYP
0.8 V
4
1.2 ± 0.1 V
4
1.5 ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
5
3.3 V ± 0.3 V
5
0.8 V
0
1.2 ± 0.1 V
0
1.5 ± 0.1 V
0
1.8 V ± 0.15 V
0
2.5 V ± 0.2 V
0
3.3 V ± 0.3 V
0
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
UNIT
pF
13
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
Output
VCC/2
VM
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for propagation delays
tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
14
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
SN74AUP1G99
LOW-POWER ULTRA-CONFIGURABLE MULTIPLE-FUNCTION GATE
WITH 3-STATE OUTPUTS
www.ti.com
SCES594C – JULY 2004 – REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPZL
tPLZ
VCC
VCC/2
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VCC/2
VOL + V∆
VOL
tPHZ
VCC/2
VOH - V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
Submit Documentation Feedback
Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74AUP1G99
15
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74AUP1G99DCTR
ACTIVE
SM8
DCT
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H99
(R, Z)
SN74AUP1G99DCTT
ACTIVE
SM8
DCT
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
H99
(R, Z)
SN74AUP1G99DCUR
ACTIVE
VSSOP
DCU
8
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(H99Q, H99R)
SN74AUP1G99DCUT
ACTIVE
VSSOP
DCU
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU | CU SN
Level-1-260C-UNLIM
-40 to 85
(H99Q, H99R)
SN74AUP1G99YZPR
ACTIVE
DSBGA
YZP
8
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
HYN
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2019
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AUP1G99DCTR
Package Package Pins
Type Drawing
SM8
DCT
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
13.0
3.35
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
4.5
1.55
4.0
12.0
Q3
SN74AUP1G99DCTT
SM8
DCT
8
250
180.0
13.0
3.35
4.5
1.55
4.0
12.0
Q3
SN74AUP1G99DCUR
VSSOP
DCU
8
3000
180.0
8.4
2.25
3.35
1.05
4.0
8.0
Q3
SN74AUP1G99DCUR
VSSOP
DCU
8
3000
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
SN74AUP1G99DCUT
VSSOP
DCU
8
250
178.0
9.5
2.25
3.35
1.05
4.0
8.0
Q3
SN74AUP1G99YZPR
DSBGA
YZP
8
3000
178.0
9.2
1.02
2.02
0.63
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
25-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G99DCTR
SM8
DCT
8
3000
182.0
182.0
20.0
SN74AUP1G99DCTT
SM8
DCT
8
250
182.0
182.0
20.0
SN74AUP1G99DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74AUP1G99DCUR
VSSOP
DCU
8
3000
202.0
201.0
28.0
SN74AUP1G99DCUT
VSSOP
DCU
8
250
202.0
201.0
28.0
SN74AUP1G99YZPR
DSBGA
YZP
8
3000
220.0
220.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
0,65
8
0,13 M
5
0,15 NOM
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
ÇÇÇÇÇ
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
1
0,25
4
0° – 8°
3,15
2,75
0,60
0,20
1,30 MAX
Seating Plane
0,10
0,10
0,00
NOTES: A.
B.
C.
D.
4188781/C 09/02
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion
Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
YZP0008
DSBGA - 0.5 mm max height
SCALE 8.000
DIE SIZE BALL GRID ARRAY
B
A
E
BALL A1
CORNER
D
C
0.5 MAX
SEATING PLANE
0.19
0.15
0.05 C
BALL TYP
0.5 TYP
D
C
SYMM
1.5
TYP
0.5
TYP
8X
0.015
D: Max = 1.918 mm, Min =1.858 mm
B
0.25
0.21
C A B
E: Max = 0.918 mm, Min =0.858 mm
A
1
2
SYMM
4223082/A 07/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
www.ti.com
EXAMPLE BOARD LAYOUT
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.23)
2
1
A
(0.5) TYP
B
SYMM
C
D
SYMM
LAND PATTERN EXAMPLE
SCALE:40X
SOLDER MASK
OPENING
0.05 MAX
( 0.23)
SOLDER MASK
OPENING
0.05 MIN
( 0.23)
METAL
METAL UNDER
SOLDER MASK
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4223082/A 07/2016
NOTES: (continued)
3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).
www.ti.com
EXAMPLE STENCIL DESIGN
YZP0008
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY
(0.5) TYP
8X ( 0.25)
(R0.05) TYP
1
2
A
(0.5)
TYP
B
SYMM
C
METAL
TYP
D
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SCALE:40X
4223082/A 07/2016
NOTES: (continued)
4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated
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