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Texas Instruments SN74LVCC4245A-EP Datasheet
SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
FEATURES
•
•
•
•
•
•
•
•
•
•
(1)
PW PACKAGE
(TOP VIEW)
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Bidirectional Voltage Translator
4.5 V to 5.5 V on A Port and 2.7 V to 5.5 V on
B Port
Control Inputs VIH/VIL Levels Are Referenced
to VCCA Voltage
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
VCCA
DIR
A1
A2
A3
A4
A5
A6
A7
A8
GND
GND
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
VCCB
NC
OE
B1
B2
B3
B4
B5
B6
B7
B8
GND
NC − No internal connection
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The SN74LVCC4245A is an 8-bit (octal) noninverting bus transceiver that uses two separate power-supply rails.
The A port (VCCA) is dedicated to accepting a 5-V supply level, and the configurable B port, which is designed to
track VCCB, accepts voltages from 3 V to 5 V. This allows for translation from a 3.3-V to a 5-V environment and
vice versa.
The SN74LVCC4245A is designed for asynchronous communication between data buses. The device transmits
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses
effectively are isolated. The control circuitry (DIR, OE) is powered by VCCA.
ORDERING INFORMATION (1)
TA
–55 °C to 125 °C
(1)
(2)
PACKAGE (2)
TSSOP – PW
Reel of 2000
ORDERABLE PART NUMBER
CLVCC4245AMPWREP
TOP-SIDE MARKING
LG245A-EP
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
FUNCTION TABLE
(EACH TRANSCEIVER)
INPUTS
OPERATION
OE
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
LOGIC DIAGRAM (POSITIVE LOGIC)
DIR
2
22
OE
A1
3
21
B1
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCCA
VCCB
VI
MIN
MAX
–0.5
6
I/O ports (A port)
–0.5
VCCA + 0.5
I/O ports (B port)
–0.5
VCCB + 0.5
Except I/O ports
–0.5
VCCA + 0.5
A port
–0.5
VCCA + 0.5
B port
–0.5
VCCB + 0.5
Supply voltage range
Input voltage
range (2)
V
V
VO
Output voltage range (2)
IIK
Input clamp current
VI < 0 V
–50
mA
IOK
Output clamp current
VO < 0 V
–50
mA
IO
Continuous output current
±50
mA
±100
Continuous current through VCCA, VCCB, or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
2
UNIT
–65
V
mA
88
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
This value is limited to 6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS830 – MARCH 2007
Recommended Operating Conditions
(1)
VCCA
VCCA
VCCB
VIHA
Supply voltage
4.5 V
High-level input voltage
5.5 V
VIHB
4.5 V
High-level input voltage
5.5 V
VILA
4.5 V
Low-level input voltage
5.5 V
VILB
4.5 V
Low-level input voltage
5.5 V
VIH
High-level input voltage (control pins) (referenced to VCCA)
4.5 V
5.5 V
VIL
VCCB
Low-level input voltage (control pins) (referenced to VCCA)
4.5 V
5.5 V
MIN
NOM
MAX
4.5
5
5.5
2.7
3.3
5.5
2.7 V
2
3.6 V
2
5.5 V
2
2.7 V
2
3.6 V
2
5.5 V
3.85
V
V
V
2.7 V
0.8
3.6 V
0.8
5.5 V
0.8
2.7 V
0.8
3.6 V
0.8
5.5 V
UNIT
V
V
1.65
2.7 V
2
3.6 V
2
5.5 V
2
V
2.7 V
0.8
3.6 V
0.8
5.5 V
0.8
V
VIA
Input voltage
0
VCCA
V
VIB
Input voltage
0
VCCB
V
VOA
Output voltage
0
VCCA
V
VOB
Output voltage
0
VCCB
V
IOHA
High-level output current
4.5 V
3V
–24
mA
IOHB
High-level output current
4.5 V
2.7 V to 4.5 V
–24
mA
IOLA
Low-level output current
4.5 V
3V
24
mA
IOLB
Low-level output current
4.5 V
2.7 V to 4.5 V
24
mA
TA
Operating free-air temperature
125
°C
(1)
–55
All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. See the TI application
report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOHA
VCCA
4.5 V
IOH = –24 mA
IOH = –100 µA
4.5 V
IOH = –12 mA
4.5 V
VOHB
IOH = –24 mA
4.5 V
IOL = 100 µA
VOLA
4.5 V
IOL = 24 mA
3V
MIN
TYP
4.4
4.49
3.76
4.25
2.99
3V
2.9
2.7 V
2.2
2.5
3V
2.46
2.85
2.7 V
2.1
2.3
3V
2.25
2.65
4.5 V
3.76
4.25
3V
MAX
V
0.1
0.21
0.44
0.44
4.5 V
3V
IOL = 12 mA
4.5 V
2.7 V
0.11
2.7 V
0.22
0.5
IOL = 24 mA
4.5 V
3V
0.21
0.44
4.5 V
0.18
0.44
3.6 V
±0.1
±1
5.5 V
±0.1
±1
5.5 V
3.6 V
±0.5
±5
5.5 V
Open
8
80
3.6 V
8
80
5.5 V
8
80
3.6 V
5
50
5.5 V
8
80
II
Control inputs
VI = VCCA or GND
IOZ (1)
A or B port
VO = VCCA/B or GND,
ICCA
B to A
5.5 V
VI = VIL or VIH
An = VCC or GND
UNIT
V
IOL = 100 µA
VOLB
V
0.1
V
µA
µA
µA
IO (A port) = 0,
Bn = VCCB or GND
5.5 V
A to B
An = VCCA or GND,
IO (B port) = 0
5.5 V
A port
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
OE at GND and DIR at VCCA
5.5 V
5.5 V
1.35
1.5
OE
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
DIR at VCCA or GND
5.5 V
5.5 V
1
1.5
DIR
VI = VCCA – 2.1 V, Other inputs at VCCA or GND,
OE at VCCA or GND
5.5 V
3.6 V
1
1.5
∆ICCB (2)
B port
VI = VCCB – 0.6 V, Other inputs at VCCB or GND,
OE at GND and DIR at GND
5.5 V
3.6 V
0.35
0.5
Ci
Control inputs
VI = VCCA or GND
Open
Open
5
pF
Cio
A or B port
VO = VCCA/B or GND
5V
3.3 V
11
pF
ICCB
∆ICCA (2)
(1)
(2)
4
VCCB
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or the
associated VCC.
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µA
mA
mA
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
SCAS830 – MARCH 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1 through
Figure 4)
PARAMETER
tPHL
tPLH
tPHL
tPLH
tPZL
tPZH
tPZL
tPZH
tPLZ
tPHZ
tPLZ
tPHZ
FROM
(INPUT)
TO
(OUTPUT)
A
B
B
A
OE
A
OE
B
OE
A
OE
B
VCCA = 5 V ± 0.5 V,
VCCB = 5 V ± 0.5 V
VCCA = 5 V ± 0.5 V,
VCCB = 2.7 V to 3.6 V
UNIT
MIN
MAX
MIN
MAX
1
7.1
1
7
1
6
1
7
1
6.8
1
6.2
1
6.1
1
5.3
1
9
1
9
1
8.3
1
8
1
8.2
1
10
1
8.1
1
10.2
1
5.5
1
5.9
1
5.7
1
5.9
1
6.4
1
6.4
1
7.8
1
8.9
ns
ns
ns
ns
ns
ns
Operating Characteristics
VCCA = 5 V, VCCB = 3.3 V, TA = 25 °C
PARAMETER
Cpd
Power dissipation capacitance per transceiver
TEST CONDITIONS
Outputs enabled
Outputs disabled
CL = 0,
f = 10 MHz
TYP
20
6.5
UNIT
pF
Power-Up Considerations (1)
TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up
sequence should always be followed to avoid excessive supply current, bus contention, oscillations, or other
anomalies caused by improperly biased device pins. Take the following precautions to guard against such
power-up problems:
1. Connect ground before any supply voltage is applied.
2. Power up the control side of the device (VCCA for all four of these devices).
3. Tie OE to VCCA with a pullup resistor so that it ramps with VCCA.
4. Depending on the direction of the data path, DIR can be high or low. If DIR high is needed (A data to B
bus), ramp it with VCCA. Otherwise, keep DIR low.
(1)
See the TI application report, Texas Instruments Voltage-Level-Translation Devices, literature number SCEA021.
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
PARAMETER MEASUREMENT INFORMATION FOR A TO B
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V
6V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
tPLZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
PARAMETER MEASUREMENT INFORMATION FOR A TO B
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
3.5 V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
tPLZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
PARAMETER MEASUREMENT INFORMATION FOR B TO A
VCCA = 4.5 V to 5.5 V and VCCB = 2.7 V to 3.6 V
2 × VCCA
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCCA
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
0V
Output
Waveform 1
S1 at 2 × VCCA
(see Note B)
VCCA
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
tPLZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
8
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SN74LVCC4245A-EP
OCTAL DUAL-SUPPLY BUS TRANSCEIVER
WITH CONFIGURABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
www.ti.com
SCAS830 – MARCH 2007
PARAMETER MEASUREMENT INFORMATION FOR B TO A
VCCA = 4.5 V to 5.5 V and VCCB = 3.6 V to 5.5 V
7V
500 Ω
From Output
Under Test
S1
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
GND
LOAD CIRCUIT
tw
3V
1.5 V
Input
1.5 V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V
1.5 V
0V
tPLH
1.5 V
1.5 V
VOL
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
NONINVERTING OUTPUTS
1.5 V
tPLZ
tPZH
tPHL
VOH
Output
1.5 V
tPZL
3V
Input
3V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH - 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CLVCC4245AMPWREP
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
LG245A-EP
CLVCC4245AMPWREPG4
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
LG245A-EP
V62/06658-01XE
ACTIVE
TSSOP
PW
24
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
LG245A-EP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
31-May-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVCC4245A-EP :
• Catalog: SN74LVCC4245A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CLVCC4245AMPWREP
Package Package Pins
Type Drawing
TSSOP
PW
24
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2000
330.0
16.4
Pack Materials-Page 1
6.95
B0
(mm)
K0
(mm)
P1
(mm)
8.3
1.6
8.0
W
Pin1
(mm) Quadrant
16.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVCC4245AMPWREP
TSSOP
PW
24
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0024A
TSSOP - 1.2 mm max height
SCALE 2.000
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
TYP
6.2
A
0.1 C
PIN 1 INDEX AREA
22X 0.65
24
1
2X
7.15
7.9
7.7
NOTE 3
12
13
B
0.30
0.19
0.1
C A B
24X
4.5
4.3
NOTE 4
1.2 MAX
0.25
GAGE PLANE
0.15
0.05
(0.15) TYP
SEE DETAIL A
0 -8
0.75
0.50
DETAIL A
A 20
TYPICAL
4220208/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
24X (1.5)
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
13
12
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
NON-SOLDER MASK
DEFINED
(PREFERRED)
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
15.000
4220208/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0024A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
24X (1.5)
SYMM
(R0.05) TYP
1
24
24X (0.45)
22X (0.65)
SYMM
12
13
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220208/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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