Texas Instruments | SN74AUP1G17-EP | Datasheet | Texas Instruments SN74AUP1G17-EP Datasheet

Texas Instruments SN74AUP1G17-EP Datasheet
SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Low Static-Power Consumption
(ICC = 0.9 µA Max)
Low Dynamic-Power Consumption
(Cpd = 4.4 pF Typ at 3.3 V)
Low Input Capacitance (CI = 1.5 pF)
Low Noise – Overshoot and Undershoot
<10% of VCC
Ioff Supports Partial-Power-Down Mode
Operation
Includes Schmitt-Trigger Inputs
Wide Operating VCC Range of 0.8 V to 3.6 V
Optimized for 3.3-V Operation
3.6-V I/O Tolerant to Support Mixed-Mode
Signal Operation
•
•
•
•
•
tpd = 5.1 ns Max at 3.3 V
Suitable for Point-to-Point Applications
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Performance Tested Per JESD 22
– 2000-V Human-Body Model
(A114-B, Class II)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
ESD Protection Exceeds 5000 V With
Human-Body Model
DCK PACKAGE
(TOP VIEW)
NC
1
A
2
GND
3
5
VCC
4
Y
See mechanical drawings for dimensions.
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range
of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see
Figures 1 and 2).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated
SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
xxxxxx
80%
80%
60%
60%
3.3-V
Logic†
40%
Switching Characteristics
at 25 MHz†
Dynamic-Power Consumption
(pF)
100%
3.3-V
LVC
Logic†
40%
3.5
3
AUP
0%
0
−0.5
†
AUP
0%
Input
2
1.5
1
Output
0.5
20%
20%
2.5
Voltage − V
Static-Power Consumption
(µA)
100%
0
5
10
15
20 25 30
Time − ns
35
40
45
† AUP1G08 data at C = 15 pF
L
Single, dual, and triple gates
Figure 1. AUP - The Lowest-Power Family
Figure 2. Excellent Signal Integrity
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device functions as an independent gate with Schmitt-trigger inputs, which allows for slow input transition
and better switching noise immunity at the input.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–55°C to 125°C
(1)
(2)
2
PACKAGE (1)
SOT (SC-70) – DCK
ORDERABLE PART NUMBER
Reel of 3000
SN74AUP1G17MDCKREP
TOP-SIDE MARKING (2)
BZU
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCK: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to
designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
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SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
FUNCTION TABLE
INPUTS
A
OUTPUT
Y
H
H
L
L
LOGIC DIAGRAM (POSITIVE LOGIC)
2
4
A
Y
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
MAX
Supply voltage range
–0.5
4.6
UNIT
V
range (2)
VI
Input voltage
–0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state (2)
–0.5
4.6
V
VO
Output voltage range in the high or low state (2)
–0.5 VCC + 0.5
V
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±20
mA
Continuous current through VCC or GND
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
(1)
(2)
(3)
DCK package
–65
±50
mA
227
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VI
Input voltage
VO
Output voltage
IOH
High-level output current
MIN
MAX
0.8
3.6
V
0
3.6
V
0
VCC
V
VCC = 0.8 V
–20
µA
VCC = 1.1 V
–1.1
VCC = 1.4 V
–1.7
VCC = 1.65 V
–1.9
VCC = 2.3 V
–3.1
VCC = 3 V
IOL
Low-level output current
20
VCC = 1.1 V
1.1
VCC = 1.4 V
1.7
VCC = 1.65 V
1.9
VCC = 2.3 V
3.1
(1)
Operating free-air temperature
mA
–4
VCC = 0.8 V
VCC = 3 V
TA
UNIT
µA
mA
4
–55
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA = –55°C
to 125°C
VCC
MIN
VT+
Positive-going
input threshold
voltage
VT–
Negative-going
input threshold
voltage
∆VT
Hysteresis
(VT+ – VT–)
0.3
1.1 V
0.53
0.9
1.4 V
0.74
1.11
1.65 V
0.91
1.29
2.3 V
1.37
1.77
3V
1.88
2.29
0.8 V
0.1
0.6
1.1 V
0.26
0.65
1.4 V
0.39
0.75
1.65 V
0.47
0.84
2.3 V
0.69
1.04
3V
0.88
1.24
0.8 V
0.07
0.5
1.1 V
0.08
0.46
1.4 V
0.18
0.56
1.65 V
0.27
0.66
2.3 V
0.53
0.92
0.79
1.31
IOH = –20 µA
0.8 V to 3.6 V
VCC – 0.2
IOH = –1.1 mA
1.1 V
0.7 × VCC
IOH = –1.7 mA
1.4 V
1.03
IOH = –1.9 mA
1.65 V
IOH = –2.3 mA
IOH = –3.1 mA
IOH = –2.7 mA
IOH = –4 mA
VOL
V
2.67
2.55
1.1 V
0.3 × VCC
1.4 V
0.37
IOL = 1.9 mA
1.65 V
0.35
VI = GND to 3.6 V
V
1.85
IOL = 1.7 mA
IOL = 4 mA
V
V
IOL = 1.1 mA
IOL = 2.7 mA
4
3V
1.3
1.97
0.8 V to 3.6 V
IOL = 3.1 mA
II
2.3 V
0.6
IOL = 20 µA
IOL = 2.3 mA
All
inputs
UNIT
MAX
0.8 V
3V
VOH
TYP
0.1
0.33
2.3 V
V
0.45
0.33
3V
0.475
0 V to 3.6 V
0.5
µA
Ioff
VI or VO = 0 V to 3.6 V
0V
5.0
µA
∆Ioff
VI or VO = 0 V to 3.6 V
0 V to 0.2 V
5.0
µA
ICC
VI = GND or (VCC to 3.6 V),
IO = 0
0.8 V to 3.6 V
0.9
µA
∆ICC
VI = VCC – 0.6 V, IO = 0
50
µA
Ci
VI = VCC or GND
Co
VO = GND
3.3 V
0V
1.5
3.6 V
1.5
0V
2.5
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pF
pF
SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 3 and Figure 4)
PARAMETER
FROM
(INPUT)
tpd
A
TO
(OUTPUT)
Y
TA = –55°C
to 125°C
VCC
UNIT
MIN
MAX
1.2 V ± 0.1 V
7.5
28
1.5 V ± 0.1 V
5.6
20
1.8 V ± 0.15 V
4.8
17
2.5 V ± 0.2 V
4
13
3.3 V ± 0.3 V
3.6
11
ns
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
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VCC
TYP
0.8 V
4
1.2 ± 0.1 V
4
1.5 ± 0.1 V
4
1.8 V ± 0.15 V
4
2.5 V ± 0.2 V
4.2
3.3 V ± 0.3 V
4.4
UNIT
pF
5
SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
(Propagation Delays, Setup and Hold Times, and Pulse Width)
From Output
Under Test
CL
(see Note A)
1 MΩ
LOAD CIRCUIT
CL
VM
VI
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
5, 10, 15, 30 pF
VCC/2
VCC
tw
VCC
Input
VCC/2
VCC/2
VI
VM
Input
0V
VM
VOLTAGE WAVEFORMS
PULSE DURATION
0V
tPHL
tPLH
VOH
VM
Output
VM
VOL
tPHL
VCC
Timing Input
0V
tPLH
tsu
VOH
Output
VCC/2
VM
th
VCC
VM
VOL
Data Input
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, for propagation delays
tr/tf = 3 ns, for setup and hold times and pulse width tr/tf = 1.2 ns.
C. The outputs are measured one at a time, with one transition per measurement.
D. tPLH and tPHL are the same as tpd.
E. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
6
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SN74AUP1G17-EP
LOW-POWER SINGLE SCHMITT-TRIGGER BUFFER
www.ti.com
SCES684 – JANUARY 2007
PARAMETER MEASUREMENT INFORMATION
(Enable and Disable Times)
2 × VCC
S1
5 kΩ
From Output
Under Test
GND
CL
(see Note A)
5 kΩ
TEST
S1
tPLZ/tPZL
tPHZ/tPZH
2 × VCC
GND
LOAD CIRCUIT
CL
VM
VI
V∆
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.1 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.15 V
5, 10, 15, 30 pF
VCC/2
VCC
0.3 V
VCC
Output
Control
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
VCC/2
VCC/2
0V
tPZL
tPLZ
VCC
VCC/2
VOL + V∆
tPZH
Output
Waveform 2
S1 at GND
(see Note B)
VOL
tPHZ
VCC/2
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr/tf = 3 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 4. Load Circuit and Voltage Waveforms
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
SN74AUP1G17MDCKREP
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
BZU
V62/07623-01XE
ACTIVE
SC70
DCK
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-55 to 125
BZU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74AUP1G17-EP :
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
• Catalog: SN74AUP1G17
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74AUP1G17MDCKRE
P
Package Package Pins
Type Drawing
SC70
DCK
5
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
3000
180.0
8.4
Pack Materials-Page 1
2.41
B0
(mm)
K0
(mm)
P1
(mm)
2.41
1.2
4.0
W
Pin1
(mm) Quadrant
8.0
Q3
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74AUP1G17MDCKREP
SC70
DCK
5
3000
202.0
201.0
28.0
Pack Materials-Page 2
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TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2017, Texas Instruments Incorporated
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