Texas Instruments | SN54LVTH16541, SN74LVTH16541 (Rev. E) | Datasheet | Texas Instruments SN54LVTH16541, SN74LVTH16541 (Rev. E) Datasheet

Texas Instruments SN54LVTH16541, SN74LVTH16541 (Rev. E) Datasheet
SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
•
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•
•
•
•
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•
•
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Members of the Texas Instruments Widebus™
Family
State-of-the-Art Advanced BiCMOS
Technology (ABT) Design for 3.3-V Operation
and Low Static-Power Dissipation
Support Mixed-Mode Signal Operation
(5-V Input and Output Voltages With
3.3-V VCC)
Support Unregulated Battery Operation Down
to 2.7 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Ioff and Power-Up 3-State Support Hot
Insertion
Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 500 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package Using
25-mil Center-to-Center Spacings
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
SN54LVTH16541 . . . WD PACKAGE
SN74LVTH16541 . . . DGG OR DL PACKAGE
(TOP VIEW)
1OE1
1Y1
1Y2
GND
1Y3
1Y4
VCC
1Y5
1Y6
GND
1Y7
1Y8
2Y1
2Y2
GND
2Y3
2Y4
VCC
2Y5
2Y6
GND
2Y7
2Y8
2OE1
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE2
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE2
DESCRIPTION/ORDERING INFORMATION
These 16-bit buffers/drivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the
capability to provide a TTL interface to a 5-V system environment.
These devices are noninverting 16-bit buffers composed of two 8-bit sections with separate output-enable
signals. For either 8-bit buffer section, the two output-enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must
be low for the corresponding Y outputs to be active. If either output-enable input is high, the outputs of that 8-bit
buffer section are in the high-impedance state.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the devices when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1997–2006, Texas Instruments Incorporated
SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The SN54LVTH16541 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LVTH16541 is characterized for operation from –40°C to 85°C.
ORDERING INFORMATION
PACKAGE (1)
TA
ORDERABLE PART NUMBER
Reel of 1000
SN74LVTH16541DLR
SSOP – DL
–40°C to 85°C
(1)
SN74LVTH16541DL
Tube of 25
TSSOP – DGG
LVTH16541
SN74LVTH16541DLG4
74LVTH16541DGGRE4
Reel of 2000
SN74LVTH16541DGGR
LVTH16541
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
FUNCTION TABLE
(each 8-bit section)
INPUTS
2
TOP-SIDE MARKING
74LVTH16541DLRG4
OE1
OE2
A
OUTPUT
Y
L
L
L
L
L
L
H
H
H
X
X
Z
X
H
X
Z
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SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
(1)
LOGIC SYMBOL
1OE1
1OE2
2OE1
2OE2
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
(1)
1
&
48
EN1
24
&
EN2
25
47
1
2
1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
1
35
14
33
16
32
17
30
19
29
20
27
22
26
23
1Y2
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
13
2
1Y1
2Y1
2Y2
2Y3
2Y4
2Y5
2Y6
2Y7
2Y8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE1
1OE2
1A1
1
2OE1
48
47
2OE2
2
1Y1
2A1
24
25
36
To Seven Other Channels
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13
2Y1
To Seven Other Channels
3
SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
4.6
V
VI
Input voltage range (2)
–0.5
7
V
–0.5
7
V
–0.5
VCC + 0.5
V
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high state (2)
state (2)
SN54LVTH16541
96
SN74LVTH16541
128
SN54LVTH16541
48
SN74LVTH16541
64
UNIT
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
DGG package
89
DL package
94
–65
150
mA
mA
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions (1)
SN54LVTH16541
MAX
MIN
MAX
2.7
3.6
2.7
3.6
UNIT
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
0.8
0.8
V
VI
Input voltage
5.5
5.5
V
IOH
High-level output current
–24
–32
mA
IOL
Low-level output current
48
64
mA
∆t/∆v
Input transition rise or fall rate
10
10
ns/V
2
Outputs enabled
∆t/∆VCC Power-up ramp rate
200
TA
–55
(1)
4
SN74LVTH16541
MIN
Operating free-air temperature
2
V
µs/V
200
125
–40
V
85
°C
All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
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SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
VCC = 2.7 V,
VOH
VCC = 3 V
VCC = 2.7 V
VOL
VCC = 3 V
MIN
TYP (1)
II = –18 mA
VCC = 2.7 V to 3.6 V, IOH = –100 µA
VCC = 2.7 V,
SN54LVTH16541
IOH = –8 mA
IOH = –24 mA
SN74LVTH16541B
MAX
MIN TYP (1) MAX
–1.2
–1.2
VCC – 0.2
VCC – 0.2
2.4
2.4
IOH = –32 mA
II
Data
inputs
2
IOL = 100 µA
0.2
0.2
IOL = 24 mA
0.5
0.5
IOL = 16 mA
0.4
0.4
IOL = 32 mA
0.5
0.5
IOL = 48 mA
0.55
Ioff
VI = 5.5 V
10
10
VCC = 3.6 V,
VI = VCC or GND
±1
±1
1
1
VCC = 0,
II(hold)
Data
inputs
VCC = 3 V
VI = VCC
VI = 0
–5
VI = 2 V
VCC = 3.6 V, (2)
VI = 0 to 3.6 V
IOZH
VCC = 3.6 V,
VO = 3 V
IOZL
VCC = 3.6 V,
VO = 0.5 V
µA
–5
±100
VI or VO = 0 to 4.5 V
VI = 0.8 V
V
0.55
VCC = 0 or 3.6 V,
VCC = 3.6 V
V
V
2
IOL = 64 mA
Control
inputs
UNIT
75
75
–75
–75
µA
µA
500
–750
5
5
µA
–5
–5
µA
IOZPU
VCC = 0 to 1.5 V, VO = 0.5 V to 3 V,
OE = don't care
±100 (3)
±100
µA
IOZPD
VCC = 1.5 V to 0, VO = 0.5 V to 3 V,
OE = don't care
±100 (3)
±100
µA
Outputs high
0.19
0.19
ICC
VCC = 3.6 V,
IO = 0,
VI = VCC or GND
Outputs low
Outputs disabled
5
5
0.19
0.19
0.2
0.2
mA
∆ICC (4)
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
CI
VI = 3 V or 0
4
4
pF
Co
VO = 3 V or 0
9
9
pF
(1)
(2)
(3)
(4)
mA
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to
another.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
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SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
SN54LVTH16541
PARAMETER
VCC = 3.3 V
± 0.3 V
SN74LVTH16541
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
3.7
4
1
2.4
3.5
3.8
1
3.7
4
1
2
3.5
3.8
1.1
4.8
5.7
1.2
2.7
4.6
5.5
1.1
4.8
5.4
1.2
2.8
4.6
5.2
2.1
6.2
6.5
2.2
4.1
5.9
6.2
1.9
5.7
6
2.2
3.8
5.4
5.5
tsk(LH)
0.5
0.5
tsk(HL)
0.5
0.5
tPZH
tPZL
tPHZ
tPLZ
Y
OE
Y
OE
Y
All typical values are at VCC = 3.3 V, TA = 25°C.
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MAX
MIN TYP (1) MAX
1
A
MIN
VCC = 2.7 V
MAX
tPHL
6
TO
(OUTPUT)
MIN
tPLH
(1)
FROM
(INPUT)
UNIT
MIN MAX
ns
ns
ns
ns
SN54LVTH16541,, SN74LVTH16541
3.3-V ABT 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS691E – MAY 1997 – REVISED NOVEMBER 2006
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
6V
Open
S1
500 Ω
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6V
GND
2.7 V
LOAD CIRCUIT
1.5 V
Timing Input
0V
tw
tsu
th
2.7 V
1.5 V
Input
1.5 V
2.7 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
2.7 V
Input
1.5 V
1.5 V
0V
tPLH
tPHL
VOH
1.5 V
Output
1.5 V
VOL
tPHL
Output
Waveform 1
S1 at 6 V
(see Note B)
1.5 V
1.5 V
1.5 V
VOL
tPZL
tPLZ
3V
1.5 V
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
1.5 V
0V
tPZH
tPLH
VOH
Output
2.7 V
Output
Control
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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7
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
74LVTH16541DGGRE4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVTH16541DGGRG4
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
74LVTH16541DLRG4
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16541DGGR
ACTIVE
TSSOP
DGG
48
2000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16541DL
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16541DLG4
ACTIVE
SSOP
DL
48
25
Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
SN74LVTH16541DLR
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74LVTH16541DGGR
TSSOP
DGG
48
2000
330.0
24.4
8.6
15.8
1.8
12.0
24.0
Q1
SN74LVTH16541DLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVTH16541DGGR
TSSOP
DGG
48
2000
346.0
346.0
41.0
SN74LVTH16541DLR
SSOP
DL
48
1000
346.0
346.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
0.0135 (0,343)
0.008 (0,203)
48
0.005 (0,13) M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
1
0°–ā8°
24
0.040 (1,02)
A
0.020 (0,51)
Seating Plane
0.110 (2,79) MAX
0.004 (0,10)
0.008 (0,20) MIN
PINS **
28
48
56
A MAX
0.380
(9,65)
0.630
(16,00)
0.730
(18,54)
A MIN
0.370
(9,40)
0.620
(15,75)
0.720
(18,29)
DIM
4040048 / E 12/01
NOTES: A.
B.
C.
D.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
Falls within JEDEC MO-118
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Amplifiers
Data Converters
DSP
Clocks and Timers
Interface
Logic
Power Mgmt
Microcontrollers
RFID
RF/IF and ZigBee® Solutions
amplifier.ti.com
dataconverter.ti.com
dsp.ti.com
www.ti.com/clocks
interface.ti.com
logic.ti.com
power.ti.com
microcontroller.ti.com
www.ti-rfid.com
www.ti.com/lprf
Applications
Audio
Automotive
Broadband
Digital Control
Medical
Military
Optical Networking
Security
Telephony
Video & Imaging
Wireless
www.ti.com/audio
www.ti.com/automotive
www.ti.com/broadband
www.ti.com/digitalcontrol
www.ti.com/medical
www.ti.com/military
www.ti.com/opticalnetwork
www.ti.com/security
www.ti.com/telephony
www.ti.com/video
www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2008, Texas Instruments Incorporated
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