Texas Instruments | SN74LVC16373A-EP | Datasheet | Texas Instruments SN74LVC16373A-EP Datasheet

Texas Instruments SN74LVC16373A-EP Datasheet
SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
FEATURES
•
•
•
•
•
•
•
•
•
•
DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V
at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
1OE
1Q1
1Q2
GND
1Q3
1Q4
VCC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
DESCRIPTION/
ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V VCC operation.
The SN74LVC16373A is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. The device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1LE
1D1
1D2
GND
1D3
1D4
VCC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2LE
A buffered output-enable (OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance
state. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly. The
high-impedance state and increased drive provide
the capability to drive bus lines without interface or
pullup components.
ORDERING INFORMATION
PACKAGE (1)
TA
–55°C to 125°C
(1)
SSOP – DL
ORDERABLE PART NUMBER
Tape and reel
CLVC16373AMDLREP
TOP-SIDE MARKING
LVC16373AMEP
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OE
LE
D
OUTPUT
Q
L
H
H
H
L
H
L
L
L
L
X
Q0
H
X
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1LE
1
2OE
48
2LE
C1
1D1
47
1D
2
24
25
C1
1Q1
2D1
36
To Seven Other Channels
2
1D
To Seven Other Channels
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13
2Q1
SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal
Tstg
Storage temperature range (5)
(1)
(2)
(3)
(4)
(5)
impedance (4)
–65
V
63
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
Recommended Operating Conditions (1)
VCC
Supply voltage
Operating
Data retention only
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VI
Input voltage
0.65 × VCC
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VO
V
1.5
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
0.8
0
5.5
High or low state
0
VCC
High-impedance state
0
5.5
VCC = 1.65 V
–4
VCC = 2.3 V
–8
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
8
VCC = 2.7 V
12
VCC = 3 V
24
–55
V
V
mA
mA
10
ns/V
125
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Submit Documentation Feedback
3
SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
IOH = –100 µA
VOH
1.65 V to 3.6 V
1.2
IOH = –8 mA
2.3 V
1.7
2.7 V
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 8 mA
2.3 V
0.7
IOL = 12 mA
2.7 V
0.4
3V
0.55
V
V
3.6 V
±5
µA
Ioff
VI or VO = 5.5 V
0
±10
µA
IOZ
VO = 0 to 5.5 V
3.6 V
±10
µA
ICC
∆ICC
(1)
(2)
VI = 0 to 5.5 V
UNIT
VCC – 0.2
1.65 V
IOL = 24 mA
II
TYP (1) MAX
IOH = –4 mA
IOH = –12 mA
VOL
MIN
VI = VCC or GND
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
20
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
20
2.7 V to 3.6 V
500
µA
µA
Ci
VI = VCC or GND
3.3 V
5
pF
Co
VO = VCC or GND
3.3 V
6.5
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 2.5 V
± 0.2 V
MIN
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MAX
MIN
MAX
MIN
UNIT
MAX
tw
Pulse duration, LE high
3.3
3.3
3.3
ns
tsu
Setup time, data before LE↓
1.7
1.7
1.7
ns
th
Hold time, data after LE↓
1.6
1.6
1.6
ns
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
PARAMETER
tpd
4
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
VCC = 2.5 V
± 0.2 V
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
MIN
MAX
MIN
MAX
MIN
MAX
1
5.2
1
4.9
1.6
4.2
1
5.2
1
5.3
1.3
4.6
UNIT
ns
ten
OE
Q
1
7.7
1
6.2
1.3
5.3
ns
tdis
OE
Q
1
5.2
1
6.3
2.1
5.9
ns
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SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance
per latch
Outputs enabled
Outputs disabled
f = 10 MHz
Submit Documentation Feedback
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
32
35
39
4
4
6
UNIT
pF
5
SN74LVC16373A-EP
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCAS825 – JUNE 2006
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
CL
(see Note A)
Open
GND
RL
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUTS
VCC
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
2.7 V
2.7 V
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
1.5 V
1.5 V
2 × VCC
6V
6V
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
0.15 V
0.3 V
0.3 V
VI
Timing Input
VM
0V
tw
tsu
VI
Input
VM
VM
th
VI
Data Input
VM
VM
0V
0V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VM
Input
VM
0V
tPLH
VM
VM
VOL
tPHL
VM
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPLH
tPLZ
VLOAD/2
VM
tPZH
VOH
Output
VM
tPZL
tPHL
VOH
Output
VI
Output
Control
VM
VOL
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOL + V∆
VOL
tPHZ
VM
VOH − V∆
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package
Type
Package
Drawing
Pins Package Eco Plan (2)
Qty
CLVC16373AMDLREP
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
V62/06649-01XE
ACTIVE
SSOP
DL
48
1000 Green (RoHS &
no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
Lead/Ball Finish
MSL Peak Temp (3)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC16373A-EP :
• Catalog: SN74LVC16373A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CLVC16373AMDLREP
Package Package Pins
Type Drawing
SSOP
DL
48
SPQ
Reel
Reel
Diameter Width
(mm) W1 (mm)
1000
330.0
32.4
Pack Materials-Page 1
A0 (mm)
B0 (mm)
K0 (mm)
P1
(mm)
W
Pin1
(mm) Quadrant
11.35
16.2
3.1
16.0
32.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Aug-2008
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CLVC16373AMDLREP
SSOP
DL
48
1000
346.0
346.0
49.0
Pack Materials-Page 2
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