Texas Instruments | SN54ABT16245A, SN74ABT16245A (Rev. G) | Datasheet | Texas Instruments SN54ABT16245A, SN74ABT16245A (Rev. G) Datasheet

Texas Instruments SN54ABT16245A, SN74ABT16245A (Rev. G) Datasheet
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
FEATURES
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•
Members of the Texas Instruments
Widebus™ Family
State-of-the-Art EPIC-IIB™ BiCMOS Design
Significantly Reduces Power Dissipation
Typical VOLP (Output Ground Bounce) <1 V at
VCC = 5 V, TA = 25°C
High-Impedance State During Power Up and
Power Down
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (–32-mA IOH, 64-mA IOL)
Latch-Up Performance Exceeds 500 mA Per
JESD 70
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Includes Plastic Thin Very
Small-Outline (DGV), Shrink Small-Outline
(DL), and Thin Shrink Small-Outline (DGG)
Packages and 380-mil Fine-Pitch Ceramic
(WD) Flat Package Using 25-mil
Center-to-Center Spacings
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
SN54ABT16245A . . . WD PACKAGE
SN74ABT16245A . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
1DIR
1B1
1B2
GND
1B3
1B4
VCC
1B5
1B6
GND
1B7
1B8
2B1
2B2
GND
2B3
2B4
VCC
2B5
2B6
GND
2B7
2B8
2DIR
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE
1A1
1A2
GND
1A3
1A4
VCC
1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
VCC
2A5
2A6
GND
2A7
2A8
2OE
DESCRIPTION
The 'ABT16245A devices are 16-bit noninverting 3-state transceivers designed for synchronous two-way
communication between data buses. The control-function implementation minimizes external timing
requirements.
These devices can be used as two 8-bit transceviers or one 16-bit transceiver. They allow data transmission from
the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impendance state above 2.1 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16245A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74ABT16245A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC-IIB are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1994–2006, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are
tested unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
FUNCTION TABLE
(EACH 8-BIT SECTION)
INPUTS
OE
OPERATION
DIR
L
L
B data to A bus
L
H
A data to B bus
H
X
Isolation
LOGIC SYMBOL(1)
48
1OE
1DIR
1
G3
3 EN1 [BA]
3 EN2 [AB]
25
2OE
2DIR
24
G6
6 EN4 [BA]
6 EN5 [AB]
1A1
47
2
1
1B1
2
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
46
3
44
5
43
6
41
8
40
9
38
11
37
12
36
13
4
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
5
2A2
2A3
2A4
2A5
2A6
2A7
2A8
(1)
2
35
14
33
16
32
17
30
19
29
20
27
22
26
23
2B2
2B3
2B4
2B5
2B6
2B7
2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
LOGIC DIAGRAM (POSITIVE LOGIC)
1DIR
1
2DIR
48
1A1
25
1OE
47
2A1
2
24
2OE
36
13
1B1
2B1
To Seven Other Channels
To Seven Other Channels
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
7
V
VI
Input voltage range (except I/O ports) (2)
–0.5
7
V
VO
Voltage range applied to any output in the high or power-off state
–0.5
5.5
V
IO
Current into any output in the low state
IIK
IOK
SN54ABT16245A
96
SN74ABT16245A
128
Input clamp current
VI < 0
–18
mA
Output clamp current
VO < 0
–50
mA
θJA
Package thermal impedance (3)
Tstg
Storage temperature range
DGG package
89
DGV package
93
DL package
(1)
(2)
(3)
UNIT
mA
°C/W
94
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
The package thermal impedance is calculated in accordance with JESD 51.
3
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
Recommended Operating Conditions (1)
SN54ABT16245A SN74ABT16245A
VCC
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
MIN
MAX
MIN
MAX
4.5
5.5
4.5
5.5
2
0.8
0
Outputs enabled
∆t/∆VCC Power-up ramp rate
200
TA
–55
(1)
4
Operating free-air temperature
2
VCC
V
V
0.8
0
UNIT
V
VCC
V
–24
–32
mA
48
64
mA
10
10
ns/V
µs/V
200
125
–40
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
°C
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
VOH
TEST CONDITIONS
SN54ABT16245A SN74ABT16245A
MAX
MIN
MIN
II = –18 mA
VCC = 4.5 V,
IOH = –3 mA
2.5
2.5
2.5
VCC = 5 V,
IOH = –3 mA
3
3
3
IOH = –24 mA
2
2
IOH = –32 mA
2 (2)
VCC = 4.5 V
–1.2
MAX
VCC = 4.5 V,
VCC = 4.5 V
VOL
TA = 25°C
MIN TYP (1)
–1.2
0.55
IOL = 64 mA
0.55 (2)
VCC = 0 to 5.5 V, VI = VCC or GND
A or B
port
V
V
0.55
0.55
100
Control
inputs
UNIT
2
IOL = 48 mA
Vhys
–1.2
MAX
V
mV
±1
±1
±1
VCC = 2.1 V to 5.5 V, VI = VCC or GND
±20 (2)
±100
±20
IOZPU
VCC = 0 to 2.1 V, VO = 0.5 V to 2.7 V, OE = X
±50 (3)
±50 (3)
±50
µA
IOZPD
VCC = 2.1 V to 0, VO = 0.5 V to 2.7 V, OE = X
±50 (3)
±50 (3)
±50
µA
10
10 (5)
µA
–10
–10 (5)
µA
±100
µA
50
µA
–180
mA
II
µA
(4)
VCC = 2.1 V to 5.5 V, VO = 2.7 V, OE ≥ 2 V
10 (5)
IOZL (4)
VCC = 2.1 V to 5.5 V, VO = 0.5 V, OE ≥ 2 V
–10 (5)
Ioff
VCC = 0,
VI or VO ≤ 5.5 V
ICEX
VCC = 5.5 V,
VO = 5.5 V
Outputs high
(6)
VCC = 5.5 V,
VO = 2.5 V
IOZH
IO
A or B
port
ICC
VCC = 5.5 V, IO = 0,
VI = VCC or GND
±100
50
–50
–100
–180
50
–50
–180
–50
Outputs high
2
2
2
Outputs low
32
32
32
Outputs disabled
2
2
2
Outputs enabled
2
1.5
2
Outputs disabled
0.05
1
0.05
1.5
1.5
1.5
mA
Data
inputs
VCC = 5.5 V,
One inputs at 3.4 V,
Other inputs at
VCC or GND
Control
inputs
VCC = 5.5 V, One input at 3.4 V,
Other inputs at VCC or GND
Ci
Control
inputs
VI = 2.5 V or 0.5 V
3
pF
Co
A or B
port
VO = 2.5 V or 0.5 V
6
pF
∆ICC (7)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
mA
All typical values are at VCC = 5 V.
On products compliant to MIL-PRF-38535, this parameter does not apply.
On products compliant to MIL-PRF-38535, this parameter is not production tested.
The parameters IOZH and IOZL include the input leakage current.
This limit may vary among suppliers.
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
5
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
Switching Characteristics
over recommended operating ranges of supply voltage and operating free-air temperature, CL = 50 pF
(unless otherwise noted) (see Figure 1 )
SN54ABT16245A
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
OE
B or A
OE
B or A
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
0.5
2.2
3.4
0.5
4
0.5
2.3
3.8
0.5
4.6
0.8
3.6
5.2
0.8
5.5
0.9
3.7
6.1
0.1
7.3
1.3
4.4
5.8
1.3
6.3
1.4
3.3
4.7
1.4
5.5
UNIT
ns
ns
ns
Switching Characteristics
over recommended operating ranges of supply voltage and operating free-air temperature, CL = 50 pF
(unless otherwise noted) (see Figure 1 )
SN74ABT16245A
PARAMETER
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
6
FROM
(INPUT)
TO
(OUTPUT)
A or B
B or A
OE
B or A
OE
B or A
VCC = 5 V,
TA = 25°C
MIN
MAX
MIN
TYP
MAX
1
2.2
3.4
1
3.9
1
2.3
3.7
1
4.2
1
3.6
5.2
1
6.3
1
3.7
5.4
1
6.4
2
4.4
5.8
2
6.3
1.5
3.3
4.7
1.5
5.2
UNIT
ns
ns
ns
SN54ABT16245A, SN74ABT16245A
16-BIT BUS TRANSCEIVERS
WITH 3-STATE OUTPUTS
www.ti.com
SCBS300G – MARCH 1994 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
7V
Open
GND
CL = 50 pF
(see Note A)
500 Ω
TEST
S1
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open
7V
Open
3V
LOAD CIRCUIT
Timing Input
1.5 V
0V
tw
tsu
3V
th
3V
Input
1.5 V
1.5 V
1.5 V
Data Input
1.5 V
0V
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
3V
1.5 V
Input
1.5 V
0V
tPLH
tPHL
1.5 V
1.5 V
VOL
tPHL
1.5 V
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
tPLZ
3.5 V
1.5 V
Output
Waveform 2
S1 at Open
(see Note B)
VOL + 0.3 V
VOL
tPHZ
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 7 V
(see Note B)
tPLH
VOH
Output
1.5 V
tPZL
VOH
Output
3V
Output
Control
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
5962-9317501MXA
ACTIVE
CFP
WD
48
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9317501MX
A
SNJ54ABT16245A
WD
74ABT16245ADGGRG4
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16245A
SN74ABT16245ADGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16245A
SN74ABT16245ADGVR
ACTIVE
TVSOP
DGV
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
AH245A
SN74ABT16245ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16245A
SN74ABT16245ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ABT16245A
SNJ54ABT16245AWD
ACTIVE
CFP
WD
48
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-9317501MX
A
SNJ54ABT16245A
WD
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
24-Aug-2018
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54ABT16245A, SN74ABT16245A :
• Catalog: SN74ABT16245A
• Enhanced Product: SN74ABT16245A-EP, SN74ABT16245A-EP
• Military: SN54ABT16245A
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Enhanced Product - Supports Defense, Aerospace and Medical Applications
• Military - QML certified for Military and Defense Applications
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
8.6
13.0
1.8
12.0
24.0
Q1
SN74ABT16245ADGGR
TSSOP
DGG
48
2000
330.0
24.4
SN74ABT16245ADGVR
TVSOP
DGV
48
2000
330.0
16.4
7.1
10.2
1.6
12.0
16.0
Q1
SN74ABT16245ADLR
SSOP
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ABT16245ADGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74ABT16245ADGVR
TVSOP
DGV
48
2000
367.0
367.0
38.0
SN74ABT16245ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,40
0,23
0,13
24
13
0,07 M
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–8°
1
0,75
0,50
12
A
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,08
14
16
20
24
38
48
56
A MAX
3,70
3,70
5,10
5,10
7,90
9,80
11,40
A MIN
3,50
3,50
4,90
4,90
7,70
9,60
11,20
DIM
4073251/E 08/00
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
MECHANICAL DATA
MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997
WD (R-GDFP-F**)
CERAMIC DUAL FLATPACK
48 LEADS SHOWN
0.120 (3,05)
0.075 (1,91)
0.009 (0,23)
0.004 (0,10)
1.130 (28,70)
0.870 (22,10)
0.370 (9,40)
0.250 (6,35)
0.390 (9,91)
0.370 (9,40)
0.370 (9,40)
0.250 (6,35)
48
1
0.025 (0,635)
A
0.014 (0,36)
0.008 (0,20)
25
24
NO. OF
LEADS**
48
56
A MAX
0.640
(16,26)
0.740
(18,80)
A MIN
0.610
(15,49)
0.710
(18,03)
4040176 / D 10/97
NOTES: A.
B.
C.
D.
E.
All linear dimensions are in inches (millimeters).
This drawing is subject to change without notice.
This package can be hermetically sealed with a ceramic lid using glass frit.
Index point is provided on cap for terminal identification only
Falls within MIL STD 1835: GDFP1-F48 and JEDEC MO -146AA
GDFP1-F56 and JEDEC MO -146AB
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• DALLAS, TEXAS 75265
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