Texas Instruments | Two 1-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, FB Path, & (Rev. C) | Datasheet | Texas Instruments Two 1-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, FB Path, & (Rev. C) Datasheet

Texas Instruments Two 1-Bit LVTTL-to-GTLP Adj-Edge-Rate Bus Xcvrs w/ Split LVTTL Port, FB Path, & (Rev. C) Datasheet
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SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
FEATURES
•
•
•
•
•
•
•
•
•
•
•
TI-OPC™ Circuitry Limits Ringing on
Unevenly Loaded Backplanes
OEC™ Circuitry Improves Signal Integrity and
Reduces Electromagnetic Interference
Bidirectional Interface Between GTLP Signal
Levels and LVTTL Logic Levels
Split LVTTL Port Provides a Feedback Path
for Control and Diagnostics Monitoring
LVTTL Interfaces Are 5-V Tolerant
High-Drive GTLP Outputs (100 mA)
LVTTL Outputs (–24 mA/24 mA)
Variable Edge-Rate Control (ERC) Input
Selects GTLP Rise and Fall Times for Optimal
Data-Transfer Rate and Signal Integrity in
Distributed Loads
Ioff, Power-Up 3-State, and BIAS VCC Support
Live Insertion
Polarity Control Selects True or
Complementary Outputs
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
SCES349C – JUNE 2001 – REVISED JANUARY 2006
•
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DGV, DW, OR PW PACKAGE
(TOP VIEW)
1Y
1T/C
2Y
GND
1OEAB
VCC
1A
GND
2A
2OEAB
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
1OEBY
2T/C
2OEBY
GND
1B
ERC
2B
GND
VREF
BIAS VCC
DESCRIPTION/ORDERING INFORMATION
The SN74GTLP1395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and
GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require
individual output-enable and true/complement controls. The device allows for transparent and inverted
transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback
path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating
at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with
the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than
standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced
input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC
and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane
models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load
impedance down to 11 Ω.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLP1395 is given only at the preferred higher noise margin GTLP, but the user
has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and
VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application
reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL
Applications, literature number SCEA017.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels,
but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input
reference voltage.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TI-OPC, OEC are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2001–2006, Texas Instruments Incorporated
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power
down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output
connections, preventing disturbance of active data on the backplane during card insertion or removal, and
permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated
backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal
integrity, which allows adequate noise margin to be maintained at higher frequencies.
High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC
input voltage between low and high adjusts the B-port output rise and fall times. This allows the designer to
optimize system data-transfer rate and signal integrity to the backplane load.
When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.5 V, the output-enable (OE) input should be tied to VCC
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the
driver.
ORDERING INFORMATION
PACKAGE (1)
TA
SOIC – DW
–40°C to 85°C
(1)
ORDERABLE PART NUMBER
Tube
SN74GTLP1395DW
Tape and reel
SN74GTLP1395DWR
GTLP1395
TSSOP – PW
Tape and reel
SN74GTLP1395PWR
GP395
TVSOP – DGV
Tape and reel
SN74GTLP1395DGVR
GP395
VFBGA – GQN
Tape and reel
SN74GTLP1395GQNR
GP395
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
GQN PACKAGE
(TOP VIEW)
1
A
B
2
3
TERMINAL ASSIGNMENTS
1
4
2
3
4
A
1T/C
1Y
1OEBY
2T/C
B
GND
GND
2Y
2OEBY
C
VCC
1OEAB
ERC
1B
C
D
GND
GND
1A
2B
D
E
2OEAB
2A
BIAS VCC
VREF
E
2
TOP-SIDE MARKING
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
FUNCTIONAL DESCRIPTION
The output-enable (1OEAB, 1OEBY) and polarity-control (1T/C) inputs control 1A, 1B, and 1Y. 2OEAB, 2OEBY,
and 2T/C control 2A, 2B, and 2Y.
OEAB controls the activity of the B port. When OEAB is low, the B-port output is active. When OEAB is high, the
B-port output is disabled.
A separate LVTTL A input and Y output provide a feedback path for control and diagnostics monitoring. OEBY
controls the Y output. When OEBY is low, the Y output is active. When OEBY is high, the Y output is disabled.
T/C selects polarity of data transmission in both directions. When T/C is high, data transmission is true, and A
data goes to the B bus and B data goes to the Y bus. When T/C is low, data transmission is complementary, and
inverted A data goes to the B bus and inverted B data goes to the Y bus.
FUNCTION TABLES
abc
OUTPUT CONTROL
INPUTS
T/C
OEAB
OEBY
OUTPUT
MODE
Isolation
X
H
H
Z
H
L
H
A data to B bus
H
H
L
B data to Y bus
H
L
L
A data to B bus, B data to Y bus
L
L
H
Inverted A data to B bus
L
H
L
Inverted B data to Y bus
L
L
L
Inverted A data to B bus,
Inverted B data to Y bus
True transparent
True transparent
with feedback path
Inverted transparent
Inverted transparent
with feedback path
OUTPUT EDGE-RATE CONTROL (ERC)
INPUT
ERC
LOGIC LEVEL
OUTPUT
B-PORT
EDGE RATE
H
Slow
L
Fast
3
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C – JUNE 2001 – REVISED JANUARY 2006
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
VREF
ERC
1OEAB
1T/C
1A
1OEBY
1Y
2OEAB
2T/C
2A
2OEBY
2Y
12
15
5
2
7
1B
20
1
10
19
9
18
3
Pin numbers shown are for the DGV, DW, and PW packages.
4
16
14
2B
www.ti.com
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
Absolute Maximum Ratings
SCES349C – JUNE 2001 – REVISED JANUARY 2006
(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX
VCC
BIAS VCC
Supply voltage range
VI
Input voltage range (2)
VO
Voltage range applied to any output
in the high-impedance or power-off state (2)
IO
Current into any output in the low state
IO
Current into any output in the high state (3)
–0.5
4.6
A inputs, ERC, and control inputs
–0.5
7
B port and VREF
–0.5
4.6
Y outputs
–0.5
7
B port
–0.5
4.6
Y outputs
48
B port
200
48
Continuous current through each VCC or GND
UNIT
V
V
V
mA
mA
±100
mA
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
DGV package
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
92
DW package
58
GQN package
78
PW package
(1)
(2)
(3)
(4)
°C/W
83
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This current flows only when the output is in the high state and VO > VCC.
The package thermal impedance is calculated in accordance with JESD 51-7.
5
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
Recommended Operating Conditions (1) (2) (3) (4)
VCC
BIAS VCC
Supply voltage
VTT
Termination voltage
VREF
Reference voltage
VI
Input voltage
VIH
High-level input voltage
VIL
Low-level input voltage
IIK
Input clamp current
IOH
High-level output current
Low-level output current
IOL
Δt/Δv
Input transition rise or fall rate
Δt/ΔVCC
Power-up ramp rate
TA
Operating free-air temperature
(1)
(2)
(3)
(4)
6
MIN
NOM
MAX
UNIT
3.15
3.3
3.45
V
GTL
1.14
1.2
1.26
GTLP
1.35
1.5
1.65
GTL
0.74
0.8
0.87
GTLP
0.87
1
1.1
B port
VTT
Except B port
B port
Except B port
VCC
5.5
V
V
V
VREF + 0.05
V
2
V
VREF – 0.05
B port
Except B port
0.8
V
–18
mA
Y outputs
–24
mA
Y outputs
24
B port
100
Outputs enabled
10
20
–40
mA
ns/V
μs/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Proper connection sequence for use of the B-port I/O precharge feature is GND and BIAS VCC = 3.3 V first, I/O second, and VCC = 3.3 V
last, because the BIAS VCC precharge circuitry is disabled when any VCC pin is connected. The control and VREF inputs can be
connected anytime, but normally are connected during the I/O stage. If B-port precharge is not required, any connection sequence is
acceptable, but generally, GND is connected first.
VTT and RTT can be adjusted to accommodate backplane impedances if the dc recommended IOL ratings are not exceeded.
VREF can be adjusted to optimize noise margins, but normally it is two-thirds VTT. TI-OPC is enabled in the A-to-B direction and is
activated when VTT > 0.7 V above VREF. If operated in the A-to-B direction, VREF should be set to within 0.6 V of VTT to minimize current
drain.
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
Electrical Characteristics
over recommended operating free-air temperature range for GTLP (unless otherwise noted)
PARAMETER
VIK
VOH
Y outputs
MIN TYP (1)
TEST CONDITIONS
VCC = 3.15 V,
II = –18 mA
VCC = 3.15 V to 3.45 V,
IOH = –100 μA
VCC – 0.2
IOH = –12 mA
2.4
IOH = –24 mA
2
VCC = 3.15 V
VCC = 3.15 V to 3.45 V,
Y outputs
VCC = 3.15 V
VOL
VCC = 3.15 V
B port
II (2)
IOZ (2)
ICC
UNIT
–1.2
V
V
IOL = 100 μA
0.2
IOL = 12 mA
0.4
IOL = 24 mA
0.5
IOL = 10 mA
0.2
IOL = 64 mA
0.4
IOL = 100 mA
0.55
A-port and
control inputs
VCC = 3.45 V,
VI = 0 to 5.5 V
±10
Y outputs
VCC = 3.45 V,
VO = 0 to 5.5 V
±10
B port
VCC = 3.45 V, VREF within 0.6 V of VTT,
VO = 0 to 2.3 V
±10
Y outputs or B port
VCC = 3.45 V, IO = 0,
VI (A-port or control inputs) = VCC or GND,
VI (B port) = VTT or GND
Outputs high
A-port inputs
Control inputs
V
μA
μA
20
Outputs low
20
Outputs disabled
20
VCC = 3.45 V, One A-port or control input at VCC – 0.6 V,
Other A-port or control inputs at VCC or GND
ΔICC (3)
CI
MAX
1.5
VI = 3.15 V or 0
4
4.5
3.5
5
mA
mA
pF
Co
Y outputs
VO = 3.15 V or 0
5
5.5
pF
Cio
B port
VO = 1.5 V or 0
7
10.5
pF
(1)
(2)
(3)
All typical values are at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
Hot-Insertion Specifications for A Inputs and Y Outputs
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VCC = 0,
VI or VO = 0 to 5.5 V
10
μA
IOZPU
VCC = 0 to 1.5 V,
VO = 0.5 V to 3 V,
OEBY = 0
±30
μA
IOZPD
VCC = 1.5 V to 0,
VO = 0.5 V to 3 V,
OEBY = 0
±30
μA
Ioff
Live-Insertion Specifications for B Port
over recommended operating free-air temperature range
PARAMETER
Ioff
TEST CONDITIONS
VCC = 0,
MIN MAX
BIAS VCC = 0,
VI or VO = 0 to 1.5 V
UNIT
10
μA
μA
IOZPU
VCC = 0 to 1.5 V,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V,
OEAB = 0
±30
IOZPD
VCC = 1.5 V to 0,
BIAS VCC = 0,
VO = 0.5 V to 1.5 V,
OEAB = 0
±30
μA
ICC
(BIAS VCC)
VCC = 0 to 3.15 V
5
mA
10
μA
VCC = 3.15 V to 3.45 V
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0 to 1.5 V
VO
VCC = 0,
BIAS VCC = 3.3 V,
IO = 0
IO
VCC = 0,
BIAS VCC = 3.15 V to 3.45 V,
VO (B port) = 0.6 V
0.95
–1
1.05
V
μA
7
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, VTT = 1.5 V and VREF = 1 V for GTLP
(see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
ten
tdis
ten
tdis
EDGE RATE (1)
A
B
Slow
A
B
Fast
A
Y
Slow
A
Y
Fast
T/C
B
Slow
T/C
B
Fast
OEAB
B
Slow
OEAB
B
Fast
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
tPLH
tPLH
tPHL
ten
tdis
8
TO
(OUTPUT)
tr
tPHL
(1)
(2)
FROM
(INPUT)
B
Y
T/C
Y
OEBY
Y
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25°C.
MIN TYP (2) MAX
3.3
6.3
1.9
6
2.5
5.3
1.6
4.9
3.4
9.7
3.3
9.2
2.9
8.7
2.9
8.1
3.7
6.7
1.8
6.2
1.5
5.6
1.7
5.5
3.8
6.4
1.9
6.1
2.8
5.3
1.5
5
Slow
2.4
Fast
1.3
Slow
3
Fast
2.7
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
5.3
1.4
4.5
1
4.5
1.1
4
1
4.5
1
4.7
ns
ns
ns
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
Skew Characteristics
(1)
over recommended ranges of supply voltage and operating free-air temperature, VREF = 1 V,
standard lumped loads (CL = 30 pF for B port and CL = 50 pF for Y port) (unless otherwise noted) (see Figure 1)
PARAMETER
tsk(LH) (3)
tsk(HL) (3)
tsk(LH) (3)
tsk(HL) (3)
tsk(LH) (3)
tsk(HL)
(3)
tsk(t) (3)
tsk(prLH) (4)
tsk(prHL) (4)
tsk(prLH) (4)
tsk(prHL)
(4)
tsk(prLH) (4)
tsk(prHL) (4)
(1)
(2)
(3)
(4)
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE (2)
A
B
Slow
A
B
Fast
B
Y
A
B
B
Y
MIN
MAX
0.3
0.4
0.3
0.3
0.4
0.2
Slow
1.8
Fast
1.5
UNIT
ns
ns
ns
ns
1
A
B
Slow
A
B
Fast
B
Y
0.7
2
0.5
1.7
1.2
1.6
ns
ns
ns
Actual skew values between GTLP outputs could vary on the backplane due to the loading and impedance seen by the device.
Slow (ERC = L) and Fast (ERC = H)
tsk(LH)/tsk(HL) and tsk(t) – Output-to-output skew is defined as the absolute value of the difference between the actual propagation delay for
all outputs with the same packaged device. The specifications are given for specific worst-case VCC and temperature and apply to any
outputs switching in the same direction either high to low [tsk(HL)] or low to high [tsk(LH)] or in opposite directions, both low to high and
high to low [tsk(t)].
tsk(prLH)/tsk(prHL) – The magnitude of the difference in propagation delay times between corresponding terminals of two logic devices
when both logic devices operate with the same supply voltages and at the same temperature, and have identical package types,
identical specified loads, and identical logic functions. Furthermore, these values are provided by SPICE simulations.
9
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
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SCES349C – JUNE 2001 – REVISED JANUARY 2006
PARAMETER MEASUREMENT INFORMATION
500 Ω
From Output
Under Test
S1
1.5 V
6V
Open
CL = 50 pF
(see Note A)
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
500 Ω
S1
Open
6V
GND
LOAD CIRCUIT FOR Y OUTPUTS
1.5 V
Input
12.5 Ω
From Output
Under Test
CL = 30 pF
(see Note A)
GND
Test
Point
LOAD CIRCUIT FOR B OUTPUTS
3V
1.5 V
0V
tPLH
tPHL
1V
Output
1V
VOH
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(A input to B port)
1V
0V
tPLH
VOH
Output
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
(B port to Y output)
tPLZ
3V
1.5 V
tPZH
1.5 V
1.5 V
0V
Output
Waveform 1
S1 at 6 V
(see Note B)
tPHL
1.5 V
1.5 V
tPZL
1.5 V
1V
Input
3V
Output
Control
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
1.5 V
VOH − 0.3 V
VOH
≈0 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
(A input)
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≈ 10 MHz, ZO = 50 Ω, tr ≈ 2 ns, tf ≈ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
10
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
DISTRIBUTED-LOAD BACKPLANE SWITCHING CHARACTERISTICS
The preceding switching characteristics table shows the switching characteristics of the device into a lumped
load (Figure 1). However, the designer's backplane application probably is a distributed load. The physical
representation is shown in Figure 2. This backplane, or distributed load, can be approximated closely to a
resistor inductance capacitance (RLC) circuit, as shown in Figure 3. This device has been designed for optimum
performance in this RLC circuit. The following switching characteristics table shows the switching characteristics
of the device into the RLC load, to help the designer better understand the performance of the GTLP device in
the backplane. See www.ti.com/sc/gtlp for more information.
1.5 V
1.5 V
0.25”
Conn.
1”
1”
ZO = 50 Ω
1”
Conn.
1”
Conn.
0.25”
22 Ω
22 Ω
1.5 V
11 Ω
From Output
Under Test
Conn.
1”
LL = 14 nH
Test
Point
CL = 18 pF
1”
Rcvr
Rcvr
Rcvr
Slot 2
Slot 19
Slot 20
Drvr
Slot 1
Figure 2. High-Drive Test Backplane
Figure 3. High-Drive RLC Network
Switching Characteristics
over recommended operating conditions for the bus transceiver function (unless otherwise noted) (see Figure 3)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
(1)
(2)
FROM
(INPUT)
TO
(OUTPUT)
EDGE RATE (1)
A
B
Slow
A
B
Fast
A
Y
Slow
A
Y
Fast
tr
Rise time, B outputs (20% to 80%)
tf
Fall time, B outputs (80% to 20%)
TYP (2)
4.3
4.2
3.8
3.4
6.1
5.9
5.6
5.4
Slow
1.5
Fast
1
Slow
2.6
Fast
2
UNIT
ns
ns
ns
ns
ns
ns
Slow (ERC = H) and Fast (ERC = L)
All typical values are at VCC = 3.3 V, TA = 25°C. All values are derived from TI SPICE models.
11
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C – JUNE 2001 – REVISED JANUARY 2006
www.ti.com
APPLICATION INFORMATION
Operational Description
The GTLP1395 is designed specifically for use with the TI 1394 backplane-layer controller family to transmit the
1394 backplane serial bus across parallel backplanes. But, it is a versatile two 1-bit device that also can provide
multiple 1-bit clocks or an ATM read and write clock in multislot parallel backplane applications.
The 1394-1995 is an IEEE designation for a high-performance serial bus. This serial bus defines both a
backplane (e.g., GTLP, VME, FB+, CPCI, etc.) physical layer and a point-to-point cable-connected virtual bus.
The backplane version operates at 25, 50, or 100 Mbps, whereas the cable version supports data rates of 100,
200, and 400 Mbps. Both versions are compatible at the link layer and above. The interface standard defines the
transmission method, media in the cable version, and protocol. The primary application of the cable version is the
interconnection of digital A/V equipment and integration of I/O connectivity at the back panel of personal
computers using a low-cost, scalable, high-speed serial interface. The primary application of the backplane
version is to provide a robust control interface to each daughter card. The 1394 standard also provides new
services such as real-time I/O and live connect/disconnect capability for external devices.
Electrical
The 1394 standard is a transaction-based packet technology for cable- or backplane-based environments. Both
chassis and peripheral devices can use this technology. The 1394 serial bus is organized as if it were memory
space interconnected between devices, or as if devices resided in slots on the main backplane. Device
addressing is 64 bits wide, partitioned as 10 bits for bus ID, 6 bits for node ID, and 48 bits for memory
addresses. The result is the capability to address up to 1023 buses, each having up to 63 nodes and each with
281 terabytes of memory. Memory-based addressing, rather than channel addressing, views resources as
registers or memory that can be accessed with processor-to-memory transactions. Each bus entity is termed a
unit, to be individually addressed, reset, and identified. Multiple nodes can reside physically in a single module,
and multiple ports can reside in a single node.
Some key features of the 1394 topology are multimaster capabilities, live connect/disconnect (hot plugging)
capability, genderless cabling connectors on interconnect cabling, and dynamic node address allocation as
nodes are added to the bus. A maximum of 63 nodes can be connected to one network.
The cable-based physical interface uses dc-level line states for signaling during initialization and arbitration. Both
environments use dominant mode addresses for arbitration. The backplane environment does not have the
initialization requirements of the cable environment because it is a physical bus and does not contain repeaters.
Due to the differences, a backplane-to-cable bridge is required to connect these two environments.
The signals transmitted on both the cable and backplane environments are NRZ with data-strobe (DS) encoding.
DS encoding allows only one of the two signal lines to change each data bit period, essentially doubling the jitter
tolerance with very little additional circuitry overhead in the hardware.
12
www.ti.com
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
SCES349C – JUNE 2001 – REVISED JANUARY 2006
APPLICATION INFORMATION
Protocol
Both asynchronous and isochronous data transfers are supported. The asynchronous format transfers data and
transaction layer information to an explicit address. The isochronous format broadcasts data based on channel
numbers rather than specific addressing. Isochronous packets are issued on the average of each 125 μs in
support of time-sensitive applications. Providing both asynchronous and isochronous formats on the same
interface allows both non-real-time and real-time critical applications on the same bus. The cable environment's
tree topology is resolved during a sequence of events, triggered each time a new node is added or removed from
the network. This sequence starts with a bus reset phase, where previous information about a topology is
cleared. The tree ID sequence determines the actual tree structure, and a root node is dynamically assigned, or
it is possible to force a particular node to become the root. After the tree is formed, a self-ID phase allows each
node on the network to identify itself to all other nodes. During the self-ID process, each node is assigned an
address. After all the information has been gathered on each node, the bus goes into an idle state, waiting for
the beginning of the standard arbitration process.
The backplane physical layer shares some commonality with the cable physical layer. Common functions
include: bus-state determination, bus-access protocols, encoding and decoding functions, and synchronization of
received data to a local clock.
Backplane Features
•
•
•
•
•
25-, 50-, and 100-Mbps data rates for backplane environments
Live connection/disconnection possible without data loss or interruption
Configuration ROM and status registers supporting plug and play
Multidrop or point-to-point topologies supported
Specified bandwidth assignments for real-time applications
Applicability and Typical Application for IEEE 1394 Backplane
The 1394 backplane serial bus (BPSB) plays a supportive role in backplane systems, specifically GTLP,
FutureBus+, VME64, and proprietary backplane bus systems. This supportive role can be grouped into three
categories:
• Diagnostics
– Alternate control path to the parallel backplane bus
– Test, maintenance, and troubleshooting
– Software debug and support interface
• System enhancement
– Fault tolerance
– Live insertion
– CSR access
– Auxiliary 2-bit bus with a 64-bit address space to the parallel backplane bus
• Peripheral monitoring
– Monitoring of peripherals (disk drives, fans, power supplies, etc.) in conjunction with another externally
wired monitor bus, such as defined by the Intelligent Platform Management Interface (IPMI)
The 1394 backplane physical layer (PHY) and the SN74GTLP1395 provide a cost-effective way to add
high-speed 1394 connections to every daughter card in almost any backplane. More information on the
backplane PHY devices and how to implement the 1394 standard in backplane and cable applications can be
found at www.ti.com/sc/1394.
13
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
APPLICATION INFORMATION
SN74GTLP1395 Interface With the TSB14AA1 1394 Backplane PHY
•
•
•
•
•
•
•
•
•
1A, 1B, and 1Y are used for the PHY data signals.
2A, 2B, and 2Y are used for the PHY strobe signals.
PHY N_OEB_D or OCDOE connects to 1OEAB and 2OEAB, which control the PHY transmit signals.
1OEBY and 2OEBY are connected to GND because the transceiver must always be able to receive signals
from the backplane and relay them to the PHY.
1T/C and 2T/C are connected to GND for inverted signals.
VCC is nominal 3.3 V.
BIAS VCC is connected to nominal 3.3 V to support live insertion.
VREF is normally 2/3 of VTT.
ERC is normally connected to VCC for slow edge-rate operation because frequencies of only 50 MHz (S100)
and 25 MHz (S50) are required.
Logical Representation
VCC
TSB14AA1
3.3-V VCC
D0-D1
TDOE
SN74GTLP1395
1 kΩ
1OEAB
Tdata 1A
2
1B
BPdata
Rdata 1Y
Host
Interface
CTL0-CTL1
1394
LinkLayer
LREQ
Controller
SCLK
2
1394
Backplane
PhysicalLayer
Controller
OCDOE
2OEAB
Tstrb 2A
2B
BPstrb
Rstrb 2Y
14
GND
1OEBY
1T/C
GND
GND
2OEBY
2T/C
GND
SN74GTLP1395
TWO 1-BIT LVTTL-TO-GTLP ADJUSTABLE-EDGE-RATE BUS TRANSCEIVERS
WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND SELECTABLE POLARITY
www.ti.com
SCES349C – JUNE 2001 – REVISED JANUARY 2006
APPLICATION INFORMATION
Physical Representation
64-Bit Data Bus
32- to 64-Bit Address Bus
GTLP1395 Transceiver
1394 Backplane PHY
1394 Link-Layer Controller
Host Microprocessor
Terminators
Backplane Trace
Connectors
VME/FB+/CPCI or
GTLP Transceivers
STRB
2A
Module
Module
Module
Node
Node
Node
PHY
PHY
PHY
2Y
1A
1Y
VTT
RTT
DATA
VTT
2B
STRB
1B
RTT
DATA
15
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74GTLP1395DWR
ACTIVE
SOIC
DW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GTLP1395
SN74GTLP1395PW
ACTIVE
TSSOP
PW
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GP395
SN74GTLP1395PWR
ACTIVE
TSSOP
PW
20
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
GP395
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
SN74GTLP1395DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.3
2.7
12.0
24.0
Q1
SN74GTLP1395PWR
TSSOP
PW
20
2000
330.0
16.4
6.95
7.1
1.6
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74GTLP1395DWR
SOIC
DW
20
2000
367.0
367.0
45.0
SN74GTLP1395PWR
TSSOP
PW
20
2000
367.0
367.0
38.0
Pack Materials-Page 2
PACKAGE OUTLINE
DW0020A
SOIC - 2.65 mm max height
SCALE 1.200
SOIC
C
10.63
TYP
9.97
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
20
1
13.0
12.6
NOTE 3
18X 1.27
2X
11.43
10
11
B
7.6
7.4
NOTE 4
20X
0.51
0.31
0.25
C A B
2.65 MAX
0.33
TYP
0.10
SEE DETAIL A
0.25
GAGE PLANE
0 -8
0.3
0.1
1.27
0.40
DETAIL A
TYPICAL
4220724/A 05/2016
NOTES:
1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.
www.ti.com
EXAMPLE BOARD LAYOUT
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
(R0.05)
TYP
10
11
(9.3)
LAND PATTERN EXAMPLE
SCALE:6X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4220724/A 05/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DW0020A
SOIC - 2.65 mm max height
SOIC
20X (2)
SYMM
1
20
20X (0.6)
18X (1.27)
SYMM
11
10
(9.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:6X
4220724/A 05/2016
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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