Texas Instruments | SN74ALVC16244A (Rev. O) | Datasheet | Texas Instruments SN74ALVC16244A (Rev. O) Datasheet

Texas Instruments SN74ALVC16244A (Rev. O) Datasheet
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
FEATURES
•
•
•
•
•
•
DGG OR DL PACKAGE
(TOP VIEW)
Member of the Texas Instruments Widebus™
Family
Operates From 1.65 V to 3.6 V
Max tpd of 3 ns at 3.3 V
±24-mA Output Drive at 3.3 V
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
1OE
1Y1
1Y2
GND
1Y3
1Y4
VCC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
VCC
4Y1
4Y2
GND
4Y3
4Y4
4OE
DESCRIPTION/ORDERING INFORMATION
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V VCC operation.
The SN74ALVC16244A is designed specifically to
improve the performance and density of 3-state
memory-address drivers, clock
drivers,
and
bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two
8-bit buffers, or one 16-bit buffer. It provides true
outputs and symmetrical active-low output-enable
(OE) inputs.
To ensure the high-impedance state during power up
or power down, OE should be tied to VCC through a
pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the
driver.
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
VCC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
VCC
4A1
4A2
GND
4A3
4A4
3OE
ORDERING INFORMATION
PACKAGE (1)
TA
FBGA – GRD
FBGA – ZRD (Pb-free)
SSOP – DL
–40°C to 85°C
TSSOP – DGG
VFBGA – GQL
VFBGA – ZQL (Pb-free)
(1)
ORDERABLE PART NUMBER
Tape and reel
SN74ALVC16244AGRDR
SN74ALVC16244AZRDR
Tube
SN74ALVC16244ADL
Tape and reel
SN74ALVC16244ADLR
Tape and reel
Tape and reel
SN74ALVC16244ADGGR
SN74ALVC16244ADGGRE4
SN74ALVC16244AGQLR
SN74ALVC16244AZQLR
TOP-SIDE MARKING
VC244A
ALVC16244A
ALVC16244A
VC244A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1993–2005, Texas Instruments Incorporated
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
TERMINAL ASSIGNMENTS (1)
(56-Ball GQL/ZQL Package)
GQL OR ZQL PACKAGE
(TOP VIEW)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
J
K
1
2
3
4
5
6
A
1OE
NC
NC
NC
NC
2OE
B
1Y2
1Y1
GND
GND
1A1
1A2
C
1Y4
1Y3
VCC
VCC
1A3
1A4
D
2Y2
2Y1
GND
GND
2A1
2A2
E
2Y4
2Y3
2A3
2A4
F
3Y1
3Y2
3A2
3A1
G
3Y3
3Y4
GND
GND
3A4
3A3
H
4Y1
4Y2
VCC
VCC
4A2
4A1
J
4Y3
4Y4
GND
GND
4A4
4A3
K
4OE
NC
NC
NC
NC
3OE
ABC
(1)
ABC
NC – No internal connection
GRD OR ZRD PACKAGE
(TOP VIEW)
1
2
3
4
5
6
TERMINAL ASSIGNMENTS (1)
(54-Ball GRD/ZRD Package)
A
B
C
D
E
F
G
1
2
3
4
5
6
A
1Y1
NC
1OE
2OE
NC
1A1
B
1Y3
1Y2
NC
NC
1A2
1A3
C
2Y1
1Y4
VCC
VCC
1A4
2A1
D
2Y3
2Y2
GND
GND
2A2
2A3
E
3Y1
2Y4
GND
GND
2A4
3A1
F
3Y3
3Y2
GND
GND
3A2
3A3
G
4Y1
3Y4
VCC
VCC
3A4
4A1
H
4Y3
4Y2
NC
NC
4A2
4A3
J
4Y4
NC
4OE
3OE
NC
4A4
H
J
(1)
NC – No internal connection
xxxxx
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
2
OUTPUT
Y
OE
A
L
H
H
L
L
L
H
X
Z
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
3OE
47
2
46
3
44
5
43
6
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
48
4OE
41
8
40
9
38
11
37
12
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
25
36
13
35
14
33
16
32
17
3Y1
3Y2
3Y3
3Y4
24
30
19
29
20
27
22
26
23
4Y1
4Y2
4Y3
4Y4
Pin numbers shown are for the DGG and DL packages.
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
VCC
VI
Supply voltage range
Input voltage
range (2)
Control
Inputs (3)
Data Inputs
MIN
MAX
–0.5
4.6
UNIT
V
–0.5
VCC + 0.5
V
-0.5
4.6
–0.5
VCC + 0.5
VO
Output voltage range (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
±50
mA
±100
mA
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
DGG package
70
DL package
63
GQL/ZQL package
42
GRD/ZRD package
(1)
(2)
(3)
(4)
V
°C/W
36
–65
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51-7.
3
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
Recommended Operating Conditions (1)
VCC
Supply voltage
VCC = 1.65 V to 1.95 V
VIH
High-level input voltage
MIN
MAX
1.65
3.6
Low-level input voltage
VCC = 2.3 V to 2.7 V
1.7
VCC = 2.7 V to 3.6 V
2
V
0.35 × VCC
VCC = 2.3 V to 2.7 V
0.7
VCC = 2.7 V to 3.6 V
VI
Input voltage
VO
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
(1)
V
0.65 × VCC
VCC = 1.65 V to 1.95 V
VIL
UNIT
V
0.8
Control Inputs
0
VCC
Data Inputs
0
3.6
0
VCC
VCC = 1.65 V
–4
VCC = 2.3 V
–12
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 1.65 V
4
VCC = 2.3 V
12
VCC = 2.7 V
12
VCC = 3 V
24
–40
V
V
mA
mA
10
ns/V
85
°C
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
1.65 V to 3.6 V
MIN TYP (1)
1.65 V
IOH = –6 mA
2.3 V
2
2.3 V
1.7
2.7 V
2.2
IOH = –12 mA
MAX
1.2
V
3V
2.4
IOH = –24 mA
3V
2
IOL = 100 µA
1.65 V to 3.6 V
0.2
IOL = 4 mA
1.65 V
0.45
IOL = 6 mA
2.3 V
0.4
2.3 V
0.7
2.7 V
0.4
3V
0.55
IOL = 12 mA
IOL = 24 mA
UNIT
VCC – 0.2
IOH = –4 mA
VOH
VOL
VCC
V
II
VI = VCC or GND
3.6 V
±5
µA
IOZ
VO = VCC or GND
3.6 V
±10
µA
ICC
VI = VCC or GND,
IO = 0
3.6 V
40
µA
One input at VCC – 0.6 V,
Other inputs at VCC or
GND
3 V to 3.6 V
750
µA
∆ICC
Ci
(1)
4
Control inputs
Data inputs
VI = VCC or GND
All typical values are at VCC = 3.3 V, TA = 25°C.
3.3 V
3
6
pF
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Co
Outputs
TEST CONDITIONS
MIN TYP (1)
VCC
VO = VCC or GND
3.3 V
MAX
UNIT
7
pF
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
(1)
VCC = 2.5 V
± 0.2 V
TO
(OUTPUT)
VCC = 1.8 V
tpd
A
Y
(1)
1
3.7
3.6
1
3
ns
ten
OE
Y
(1)
1
5.7
5.4
1
4.4
ns
tdis
OE
Y
(1)
1
5.2
4.6
1
4.1
ns
TYP
MIN MAX
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
PARAMETER
MIN
MAX
UNIT
MIN MAX
This information was not available at the time of publication.
Operating Characteristics
TA = 25°C
PARAMETER
Cpd
(1)
Power dissipation
capacitance
Outputs enabled
Outputs disabled
TEST
CONDITIONS
CL = 50 pF, f = 10 MHz
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
TYP
TYP
TYP
(1)
16
19
(1)
4
5
UNIT
pF
This information was not available at the time of publication.
5
SN74ALVC16244A
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCAS250O – JANUARY 1993 – REVISED OCTOBER 2005
PARAMETER MEASUREMENT INFORMATION
VLOAD
S1
RL
From Output
Under Test
Open
GND
CL
(see Note A)
RL
TEST
S1
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
VLOAD
GND
LOAD CIRCUIT
INPUT
VCC
1.8 V
2.5 V ± 0.2 V
2.7 V
3.3 V ± 0.3 V
VI
tr/tf
VCC
VCC
2.7 V
2.7 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
VM
VLOAD
CL
RL
V∆
VCC/2
VCC/2
1.5 V
1.5 V
2 × VCC
2 × VCC
6V
6V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
0.3 V
tw
VI
Timing
Input
VM
VM
VM
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VM
VM
0V
tPLH
Output
Control
(low-level
enabling)
tPLZ
VLOAD/2
VM
tPZH
VOH
VM
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VM
0V
Output
Waveform 1
S1 at VLOAD
(see Note B)
tPHL
VM
VI
VM
tPZL
VI
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VI
Data
Input
VM
0V
0V
tsu
Output
VI
VM
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + V∆
VOL
tPHZ
VOH
VM
VOH − V∆
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
SN74ALVC16244ADGGR
ACTIVE
TSSOP
DGG
48
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVC16244A
SN74ALVC16244ADL
ACTIVE
SSOP
DL
48
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVC16244A
SN74ALVC16244ADLR
ACTIVE
SSOP
DL
48
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
ALVC16244A
SN74ALVC16244AZQLR
NRND
BGA
MICROSTAR
JUNIOR
ZQL
56
1000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
VC244A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
27-Dec-2019
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SN74ALVC16244ADGGR TSSOP
SN74ALVC16244ADLR
SSOP
SN74ALVC16244AZQLR BGA MI
CROSTA
R JUNI
OR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
DGG
48
2000
330.0
24.4
8.6
13.0
1.8
12.0
24.0
Q1
DL
48
1000
330.0
32.4
11.35
16.2
3.1
16.0
32.0
Q1
ZQL
56
1000
330.0
16.4
4.8
7.3
1.5
8.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Feb-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74ALVC16244ADGGR
TSSOP
DGG
48
2000
367.0
367.0
45.0
SN74ALVC16244ADLR
SSOP
DL
48
1000
367.0
367.0
55.0
ZQL
56
1000
350.0
350.0
43.0
SN74ALVC16244AZQLR BGA MICROSTAR
JUNIOR
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
0,50
48
0,08 M
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
1
0,25
24
0°– 8°
A
0,75
0,50
Seating Plane
0,15
0,05
1,20 MAX
PINS **
0,10
48
56
64
A MAX
12,60
14,10
17,10
A MIN
12,40
13,90
16,90
DIM
4040078 / F 12/97
NOTES: A.
B.
C.
D.
All linear dimensions are in millimeters.
This drawing is subject to change without notice.
Body dimensions do not include mold protrusion not to exceed 0,15.
Falls within JEDEC MO-153
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
PACKAGE OUTLINE
ZQL0056A
JRBGA - 1 mm max height
SCALE 2.100
PLASTIC BALL GRID ARRAY
4.6
4.4
B
A
BALL A1 CORNER
7.1
6.9
1 MAX
C
SEATING PLANE
0.35
TYP
0.15
BALL TYP
0.1 C
3.25 TYP
(0.625) TYP
SYMM
K
(0.575) TYP
J
H
G
5.85
TYP
SYMM
F
E
D
C
56X
NOTE 3
B
A
0.65 TYP
BALL A1 CORNER
1
2
3
4
5
0.45
0.35
0.15
0.08
C B A
C
6
0.65 TYP
4219711/B 01/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. No metal in this area, indicates orientation.
www.ti.com
EXAMPLE BOARD LAYOUT
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
(0.65) TYP
56X ( 0.33)
2
1
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
EXPOSED METAL
( 0.33)
METAL
( 0.33)
SOLDER MASK
OPENING
EXPOSED METAL
SOLDER MASK
DEFINED
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4219711/B 01/2017
NOTES: (continued)
4. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For information, see Texas Instruments literature number SPRAA99 (www.ti.com/lit/spraa99).
www.ti.com
EXAMPLE STENCIL DESIGN
ZQL0056A
JRBGA - 1 mm max height
PLASTIC BALL GRID ARRAY
56X ( 0.33)
(0.65) TYP
1
2
3
4
5
6
A
(0.65) TYP
B
C
D
E
SYMM
F
G
H
J
K
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4219711/B 01/2017
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
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