Texas Instruments | SN74LVCZ32240A (Rev. A) | Datasheet | Texas Instruments SN74LVCZ32240A (Rev. A) Datasheet

Texas Instruments SN74LVCZ32240A (Rev. A) Datasheet
Not Recommended for New Designs
www.ti.com
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES421A – JANUARY 2003 – REVISED JULY 2005
FEATURES
•
•
•
•
•
Member of the Texas Instruments Widebus+™
Family
Operates From 2.7 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.2 ns at 3.3 V
Ioff and Power-Up 3-State Support Hot
Insertion
•
•
•
Supports Mixed-Mode Signal Operation on All
Ports (5-V Input/Output Voltage With
3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
This 32-bit buffer/driver is designed for 2.7-V to 3.6-V VCC operation.
The SN74LVCZ32240A is designed specifically to improve both the performance and density of 3-state memory
address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as eight 4-bit buffers, four 8-bit buffers, two 16-bit buffers, or one 32-bit buffer. This
device provides inverting outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
During power up or power down, when VCC is between 0 and 1.5 V, the device is in the high-impedance state.
However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down
(VCC = 0 V). The power-up 3-state circuitry places the outputs in the high-impedance state during power up and
power down, which prevents driver conflict.
ORDERING INFORMATION
PACKAGE (1)
TA
–40°C to 85°C
(1)
LFBGA – GKE
Tape and reel
ORDERABLE PART NUMBER
SN74LVCZ32240AGKER
TOP-SIDE MARKING
ZC240A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Not Recommended for New Designs
www.ti.com
SCES421A – JANUARY 2003 – REVISED JULY 2005
GKE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
TERMINAL ASSIGNMENTS
1
2
A
1Y2
1Y1
B
1Y4
1Y3
C
2Y2
2Y1
D
2Y4
2Y3
E
3Y2
3Y1
F
3Y4
3Y3
G
4Y2
4Y1
H
4Y3
J
5Y2
K
3
4
5
6
1OE
2OE
1A1
1A2
GND
GND
1A3
1A4
1VCC
1VCC
2A1
2A2
GND
GND
2A3
2A4
GND
GND
3A1
3A2
1VCC
1VCC
3A3
3A4
GND
GND
4A1
4A2
4Y4
4OE
3OE
4A4
4A3
5Y1
5OE
6OE
5A1
5A2
5Y4
5Y3
GND
GND
5A3
5A4
L
6Y2
6Y1
2VCC
2VCC
6A1
6A2
M
6Y4
6Y3
GND
GND
6A3
6A4
N
7Y2
7Y1
GND
GND
7A1
7A2
P
7Y4
7Y3
2VCC
2VCC
7A3
7A4
R
8Y2
8Y1
GND
GND
8A1
8A2
T
8Y3
8Y4
8OE
7OE
8A4
8A3
FUNCTION TABLE
(EACH 4-BIT BUFFER)
INPUTS
2
OUTPUT
Y
OE
A
L
H
L
L
L
H
H
X
Z
Not Recommended for New Designs
www.ti.com
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES421A – JANUARY 2003 – REVISED JULY 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
5OE
5A1
5A2
5A3
5A4
6OE
6A1
6A2
6A3
6A4
A3
3OE
A5
A2
A6
A1
B5
B2
B6
B1
1Y1
3A1
1Y2
3A2
1Y3
3A3
1Y4
3A4
A4
4OE
C5
C2
C6
C1
D5
D2
D6
D1
2Y1
4A1
2Y2
4A2
2Y3
4A3
2Y4
4A4
J3
7OE
J5
J2
J6
J1
K5
K2
K6
K1
5Y1
7A1
5Y2
7A2
5Y3
7A3
5Y4
7A4
J4
8OE
L5
L2
L6
L1
M5
M2
M6
M1
6Y1
8A1
6Y2
8A2
6Y3
8A3
6Y4
8A4
H4
E5
E2
E6
E1
F5
F2
F6
F1
3Y1
3Y2
3Y3
3Y4
H3
G5
G2
G6
G1
H6
H1
H5
H2
4Y1
4Y2
4Y3
4Y4
T4
N5
N2
N6
N1
P5
P2
P6
P1
7Y1
7Y2
7Y3
7Y4
T3
R5
R2
R6
R1
T6
T1
T5
T2
8Y1
8Y2
8Y3
8Y4
3
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Not Recommended for New Designs
www.ti.com
SCES421A – JANUARY 2003 – REVISED JULY 2005
Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
VCC
Supply voltage range
–0.5
6.5
V
VI
Input voltage range (2)
–0.5
6.5
V
–0.5
6.5
V
–0.5
VCC + 0.5
state (2)
UNIT
VO
Voltage range applied to any output in the high-impedance or power-off
VO
Voltage range applied to any output in the high or low state (2) (3)
IIK
Input clamp current
VI < 0
–50
mA
IOK
Output clamp current
VO < 0
–50
mA
IO
Continuous output current
Continuous current through each VCC or GND
θJA
Package thermal impedance (4)
Tstg
Storage temperature range
(1)
(2)
(3)
(4)
–65
V
±50
mA
±100
mA
40
°C/W
150
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of VCC is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions (1)
VCC
Supply voltage
VIH
High-level input voltage
VCC = 2.7 V to 3.6 V
VIL
Low-level input voltage
VCC = 2.7 V to 3.6 V
VI
Input voltage
MIN
MAX
2.7
3.6
2
V
0.8
V
5.5
V
High or low state
0
VCC
3-state
0
5.5
Output voltage
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
∆t/∆VCC
Power-up ramp rate
150
TA
Operating free-air temperature
–40
4
V
0
VO
(1)
UNIT
VCC = 2.7 V
–12
VCC = 3 V
–24
VCC = 2.7 V
12
VCC = 3 V
24
10
V
mA
mA
ns/V
µs/V
85
All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
°C
Not Recommended for New Designs
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES421A – JANUARY 2003 – REVISED JULY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –100 µA
VOH
II
2.2
3V
2.4
IOH = –24 mA
3V
2.2
IOL = 100 µA
2.7 V to 3.6 V
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3V
0.55
VI = 0 to 5.5 V
VI or VO = 5.5 V
IOZ
VO = 0 to 5.5 V
UNIT
VCC – 0.2
2.7 V
Ioff
V
0.2
V
3.6 V
±5
A
0
±5
A
3.6 V
±5
µA
IOZPU
VO = 0.5 V to 2.5 V,
OE = don't care
0 to 1.5 V
±5
µA
IOZPD
VO = 0.5 V to 2.5 V,
OE = don't care
1.5 V to 0
±5
µA
VI = VCC or GND
ICC
IO = 0
3.6 V ≤ VI ≤ 5.5 V (2)
∆ICC
(1)
(2)
2.7 V to 3.6 V
IOH = –12 mA
VOL
MIN TYP (1) MAX
VCC
200
3.6 V
One input at VCC – 0.6 V, Other inputs at VCC or GND
200
2.7 V to 3.6 V
100
µA
µA
Ci
VI = VCC or GND
3.3 V
4.5
pF
Co
VO = VCC or GND
3.3 V
6
pF
All typical values are at VCC = 3.3 V, TA = 25°C.
This applies in the disabled state only.
Switching Characteristics
over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1)
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
ten
OE
tdis
OE
PARAMETER
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN
MAX
Y
1
Y
1.5
Y
1.5
UNIT
MIN
MAX
4.5
1
4.2
ns
5
1.5
4.7
ns
6.2
1.5
5.9
ns
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF (unless otherwise noted) (see Figure 1)
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
FROM
(INPUT)
TO
(OUTPUT)
tpd
A
Y
1
4.4
1
4.1
ns
ten
OE
Y
1
4.8
1
4.5
ns
tdis
OE
Y
1.4
5.9
1.4
5.6
ns
PARAMETER
MIN
MAX
MIN
UNIT
MAX
Operating Characteristics
TA = 25°C
TEST
CONDITIONS
PARAMETER
Cpd
Power dissipation capacitance per buffer/driver
Outputs enabled
Outputs disabled
f = 10 MHz
VCC = 3.3 V
TYP
31
3.5
UNIT
pF
5
Not Recommended for New Designs
SN74LVCZ32240A
32-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES421A – JANUARY 2003 – REVISED JULY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V and 3.3 V ± 0.3 V
2 × VCC
S1
500 Ω
From Output
Under Test
Open
TEST
tpd
tPLZ/tPZL
tPHZ/tPZH
GND
CL = 30 pF or 50 pF
(see Note A)
500 Ω
S1
Open
2 × VCC
GND
LOAD CIRCUIT
tw
VCC
Timing
Input
VCC/2
VCC/2
VCC/2
0V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2
VCC/2
0V
tPLH
Output
Control
(low-level
enabling)
VCC/2
VOL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
tPLZ
VCC
VCC/2
tPZH
VOH
VCC/2
0V
Output
Waveform 1
S1 at 2 × VCC
(see Note B)
tPHL
VCC/2
VCC
VCC/2
tPZL
VCC
Input
VOLTAGE WAVEFORMS
PULSE DURATION
th
VCC
Data
Input
VCC/2
0V
0V
tsu
Output
VCC
VCC/2
Input
Output
Waveform 2
S1 at GND
(see Note B)
VOL + 0.3 V
VOL
tPHZ
VOH
VCC/2
VOH − 0.3 V
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Aug-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
SN74LVCZ32240AGKER
NRND
Package Type Package Pins Package
Drawing
Qty
LFBGA
GKE
96
1000
Eco Plan
Lead/Ball Finish
(2)
TBD
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
SNPB
Level-2-235C-1 YEAR
(4/5)
-40 to 85
ZC240A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
SN74LVCZ32240AGKER
Package Package Pins
Type Drawing
LFBGA
GKE
96
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
5.7
B0
(mm)
K0
(mm)
P1
(mm)
13.7
2.0
8.0
W
Pin1
(mm) Quadrant
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Sep-2019
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
SN74LVCZ32240AGKER
LFBGA
GKE
96
1000
336.6
336.6
41.3
Pack Materials-Page 2
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